| /* |
| * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * |
| * Redistributions of source code must retain the above copyright notice, this |
| * list of conditions and the following disclaimer. |
| * |
| * Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * |
| * Neither the name of ARM nor the names of its contributors may be used |
| * to endorse or promote products derived from this software without specific |
| * prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| * POSSIBILITY OF SUCH DAMAGE. |
| */ |
| #include <aem_generic.h> |
| #include <arch.h> |
| #include <asm_macros.S> |
| #include <assert_macros.S> |
| #include <cpu_macros.S> |
| |
| func aem_generic_core_pwr_dwn |
| /* Assert if cache is enabled */ |
| #if ENABLE_ASSERTIONS |
| ldcopr r0, SCTLR |
| tst r0, #SCTLR_C_BIT |
| ASM_ASSERT(eq) |
| #endif |
| /* --------------------------------------------- |
| * Flush L1 cache to PoU. |
| * --------------------------------------------- |
| */ |
| mov r0, #DC_OP_CISW |
| b dcsw_op_louis |
| endfunc aem_generic_core_pwr_dwn |
| |
| |
| func aem_generic_cluster_pwr_dwn |
| /* Assert if cache is enabled */ |
| #if ENABLE_ASSERTIONS |
| ldcopr r0, SCTLR |
| tst r0, #SCTLR_C_BIT |
| ASM_ASSERT(eq) |
| #endif |
| /* --------------------------------------------- |
| * Flush L1 and L2 caches to PoC. |
| * --------------------------------------------- |
| */ |
| mov r0, #DC_OP_CISW |
| b dcsw_op_all |
| endfunc aem_generic_cluster_pwr_dwn |
| |
| /* cpu_ops for Base AEM FVP */ |
| declare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \ |
| aem_generic_core_pwr_dwn, \ |
| aem_generic_cluster_pwr_dwn |