| /* |
| * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| |
| #include <assert.h> |
| #include <console.h> |
| #include <debug.h> |
| #include <mmio.h> |
| #include <plat_arm.h> |
| #include <platform.h> |
| #include <platform_def.h> |
| #include <platform_sp_min.h> |
| |
| #define BL32_END (uintptr_t)(&__BL32_END__) |
| |
| static entry_point_info_t bl33_image_ep_info; |
| |
| /* Weak definitions may be overridden in specific ARM standard platform */ |
| #pragma weak sp_min_early_platform_setup |
| #pragma weak sp_min_platform_setup |
| #pragma weak sp_min_plat_arch_setup |
| |
| |
| /******************************************************************************* |
| * Return a pointer to the 'entry_point_info' structure of the next image for the |
| * security state specified. BL33 corresponds to the non-secure image type |
| * while BL32 corresponds to the secure image type. A NULL pointer is returned |
| * if the image does not exist. |
| ******************************************************************************/ |
| entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) |
| { |
| entry_point_info_t *next_image_info; |
| |
| next_image_info = &bl33_image_ep_info; |
| |
| /* |
| * None of the images on the ARM development platforms can have 0x0 |
| * as the entrypoint |
| */ |
| if (next_image_info->pc) |
| return next_image_info; |
| else |
| return NULL; |
| } |
| |
| /******************************************************************************* |
| * Perform early platform setup. |
| ******************************************************************************/ |
| void arm_sp_min_early_platform_setup(void *from_bl2, |
| void *plat_params_from_bl2) |
| { |
| /* Initialize the console to provide early debug support */ |
| console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, |
| ARM_CONSOLE_BAUDRATE); |
| |
| #if RESET_TO_SP_MIN |
| /* There are no parameters from BL2 if SP_MIN is a reset vector */ |
| assert(from_bl2 == NULL); |
| assert(plat_params_from_bl2 == NULL); |
| |
| /* Populate entry point information for BL33 */ |
| SET_PARAM_HEAD(&bl33_image_ep_info, |
| PARAM_EP, |
| VERSION_1, |
| 0); |
| /* |
| * Tell SP_MIN where the non-trusted software image |
| * is located and the entry state information |
| */ |
| bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); |
| bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); |
| SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); |
| |
| #else /* RESET_TO_SP_MIN */ |
| |
| /* |
| * Check params passed from BL2 should not be NULL, |
| */ |
| bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; |
| assert(params_from_bl2 != NULL); |
| assert(params_from_bl2->h.type == PARAM_BL_PARAMS); |
| assert(params_from_bl2->h.version >= VERSION_2); |
| |
| bl_params_node_t *bl_params = params_from_bl2->head; |
| |
| /* |
| * Copy BL33 entry point information. |
| * They are stored in Secure RAM, in BL2's address space. |
| */ |
| while (bl_params) { |
| if (bl_params->image_id == BL33_IMAGE_ID) { |
| bl33_image_ep_info = *bl_params->ep_info; |
| break; |
| } |
| |
| bl_params = bl_params->next_params_info; |
| } |
| |
| if (bl33_image_ep_info.pc == 0) |
| panic(); |
| |
| #endif /* RESET_TO_SP_MIN */ |
| |
| } |
| |
| void sp_min_early_platform_setup(void *from_bl2, |
| void *plat_params_from_bl2) |
| { |
| arm_sp_min_early_platform_setup(from_bl2, plat_params_from_bl2); |
| |
| /* |
| * Initialize Interconnect for this cluster during cold boot. |
| * No need for locks as no other CPU is active. |
| */ |
| plat_arm_interconnect_init(); |
| |
| /* |
| * Enable Interconnect coherency for the primary CPU's cluster. |
| * Earlier bootloader stages might already do this (e.g. Trusted |
| * Firmware's BL1 does it) but we can't assume so. There is no harm in |
| * executing this code twice anyway. |
| * Platform specific PSCI code will enable coherency for other |
| * clusters. |
| */ |
| plat_arm_interconnect_enter_coherency(); |
| } |
| |
| /******************************************************************************* |
| * Perform any SP_MIN platform runtime setup prior to SP_MIN exit. |
| * Common to ARM standard platforms. |
| ******************************************************************************/ |
| void arm_sp_min_plat_runtime_setup(void) |
| { |
| /* Initialize the runtime console */ |
| console_init(PLAT_ARM_SP_MIN_RUN_UART_BASE, |
| PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ, ARM_CONSOLE_BAUDRATE); |
| } |
| |
| /******************************************************************************* |
| * Perform platform specific setup for SP_MIN |
| ******************************************************************************/ |
| void sp_min_platform_setup(void) |
| { |
| /* Initialize the GIC driver, cpu and distributor interfaces */ |
| plat_arm_gic_driver_init(); |
| plat_arm_gic_init(); |
| |
| /* |
| * Do initial security configuration to allow DRAM/device access |
| * (if earlier BL has not already done so). |
| */ |
| #if RESET_TO_SP_MIN |
| plat_arm_security_setup(); |
| #endif |
| |
| /* Enable and initialize the System level generic timer */ |
| mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, |
| CNTCR_FCREQ(0) | CNTCR_EN); |
| |
| /* Allow access to the System counter timer module */ |
| arm_configure_sys_timer(); |
| |
| /* Initialize power controller before setting up topology */ |
| plat_arm_pwrc_setup(); |
| } |
| |
| void sp_min_plat_runtime_setup(void) |
| { |
| arm_sp_min_plat_runtime_setup(); |
| } |
| |
| /******************************************************************************* |
| * Perform the very early platform specific architectural setup here. At the |
| * moment this only initializes the MMU |
| ******************************************************************************/ |
| void sp_min_plat_arch_setup(void) |
| { |
| |
| arm_setup_page_tables(BL32_BASE, |
| (BL32_END - BL32_BASE), |
| BL_CODE_BASE, |
| BL_CODE_END, |
| BL_RO_DATA_BASE, |
| BL_RO_DATA_END |
| #if USE_COHERENT_MEM |
| , BL_COHERENT_RAM_BASE, |
| BL_COHERENT_RAM_END |
| #endif |
| ); |
| |
| enable_mmu_secure(0); |
| } |