Merge changes If2743827,I163f8169,I97a69650 into integration
* changes:
feat(imx8m): add 3600 MTps DDR PLL rate
fix(imx8m): align 3200 MTps rate with U-Boot
fix(imx8m): handle 3734 in addition to 3733 and 3732 MTps rates
diff --git a/drivers/renesas/common/io/io_rcar.c b/drivers/renesas/common/io/io_rcar.c
index 45ef386..0c49ec9 100644
--- a/drivers/renesas/common/io/io_rcar.c
+++ b/drivers/renesas/common/io/io_rcar.c
@@ -244,8 +244,16 @@
dstl = cert + RCAR_CERT_INFO_DST_OFFSET;
break;
}
+ val = mmio_read_32(size);
+ if (val > (UINT32_MAX / 4)) {
+ ERROR("BL2: %s[%d] uint32 overflow!\n",
+ __func__, __LINE__);
+ *dst = 0;
+ *len = 0;
+ return;
+ }
- *len = mmio_read_32(size) * 4U;
+ *len = val * 4U;
dsth = dstl + 4U;
*dst = ((uintptr_t) mmio_read_32(dsth) << 32) +
((uintptr_t) mmio_read_32(dstl));
@@ -253,7 +261,14 @@
}
size = cert + RCAR_CERT_INFO_SIZE_OFFSET;
- *len = mmio_read_32(size) * 4U;
+ val = mmio_read_32(size);
+ if (val > (UINT32_MAX / 4)) {
+ ERROR("BL2: %s[%d] uint32 overflow!\n", __func__, __LINE__);
+ *dst = 0;
+ *len = 0;
+ return;
+ }
+ *len = val * 4U;
dstl = cert + RCAR_CERT_INFO_DST_OFFSET;
dsth = dstl + 4U;
*dst = ((uintptr_t) mmio_read_32(dsth) << 32) +
@@ -276,7 +291,7 @@
prot_end = prot_start + DRAM_PROTECTED_SIZE;
- if (dst < dram_start || dst > dram_end - len) {
+ if (dst < dram_start || len > dram_end || dst > dram_end - len) {
ERROR("BL2: dst address is on the protected area.\n");
result = IO_FAIL;
goto done;
@@ -288,8 +303,9 @@
result = IO_FAIL;
}
- if (dst < prot_start && dst > prot_start - len) {
- ERROR("BL2: loaded data is on the protected area.\n");
+ if (len > prot_start || (dst < prot_start && dst > prot_start - len)) {
+ ERROR("BL2: %s[%d] loaded data is on the protected area.\n",
+ __func__, __LINE__);
result = IO_FAIL;
}
done:
@@ -435,17 +451,17 @@
#endif
rcar_image_number = header[0];
- for (i = 0; i < rcar_image_number + 2; i++) {
- rcar_image_header[i] = header[i * 2 + 1];
- rcar_image_header_prttn[i] = header[i * 2 + 2];
- }
-
if (rcar_image_number == 0 || rcar_image_number > RCAR_MAX_BL3X_IMAGE) {
WARN("Firmware Image Package header check failed.\n");
rc = IO_FAIL;
goto error;
}
+ for (i = 0; i < rcar_image_number + 2; i++) {
+ rcar_image_header[i] = header[i * 2 + 1];
+ rcar_image_header_prttn[i] = header[i * 2 + 2];
+ }
+
rc = io_seek(handle, IO_SEEK_SET, offset + RCAR_SECTOR6_CERT_OFFSET);
if (rc != IO_SUCCESS) {
WARN("Firmware Image Package header failed to seek cert\n");
diff --git a/fdts/fvp-base-psci-common.dtsi b/fdts/fvp-base-psci-common.dtsi
index ff31ba7..583bba7 100644
--- a/fdts/fvp-base-psci-common.dtsi
+++ b/fdts/fvp-base-psci-common.dtsi
@@ -244,6 +244,9 @@
<0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 43 &gic 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 44 &gic 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 46 &gic 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
};
};
diff --git a/fdts/rtsm_ve-motherboard.dtsi b/fdts/rtsm_ve-motherboard.dtsi
index 0a824b3..5a34aae 100644
--- a/fdts/rtsm_ve-motherboard.dtsi
+++ b/fdts/rtsm_ve-motherboard.dtsi
@@ -230,6 +230,25 @@
interrupts = <42>;
};
+ virtio@140000 {
+ compatible = "virtio,mmio";
+ reg = <0x140000 0x200>;
+ interrupts = <43>;
+ };
+
+ virtio@150000 {
+ compatible = "virtio,mmio";
+ reg = <0x150000 0x200>;
+ interrupts = <44>;
+ };
+
+ virtio@200000 {
+ compatible = "virtio,mmio";
+ reg = <0x200000 0x200>;
+ interrupts = <46>;
+ status = "disabled";
+ };
+
rtc@170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x170000 0x1000>;
diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h
index c3a3a7c..9ed6a8b 100644
--- a/include/services/ffa_svc.h
+++ b/include/services/ffa_svc.h
@@ -34,7 +34,7 @@
#define FFA_VERSION_MAJOR U(1)
#define FFA_VERSION_MAJOR_SHIFT 16
#define FFA_VERSION_MAJOR_MASK U(0x7FFF)
-#define FFA_VERSION_MINOR U(1)
+#define FFA_VERSION_MINOR U(2)
#define FFA_VERSION_MINOR_SHIFT 0
#define FFA_VERSION_MINOR_MASK U(0xFFFF)
#define FFA_VERSION_BIT31_MASK U(0x1u << 31)
@@ -119,6 +119,8 @@
#define FFA_FNUM_SECONDARY_EP_REGISTER U(0x87)
#define FFA_FNUM_MEM_PERM_GET U(0x88)
#define FFA_FNUM_MEM_PERM_SET U(0x89)
+
+/* FF-A v1.2 */
#define FFA_FNUM_PARTITION_INFO_GET_REGS U(0x8B)
#define FFA_FNUM_EL3_INTR_HANDLE U(0x8C)
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
index e159248..ee6c260 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
@@ -20,7 +20,7 @@
attribute {
spmc_id = <0x8000>;
maj_ver = <0x1>;
- min_ver = <0x1>;
+ min_ver = <0x2>;
exec_state = <0x0>;
load_address = <0x0 0x6000000>;
entrypoint = <0x0 0x6000000>;
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
index 041dade..17a2fd1 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,7 +20,7 @@
attribute {
spmc_id = <0x8000>;
maj_ver = <0x1>;
- min_ver = <0x1>;
+ min_ver = <0x2>;
exec_state = <0x0>;
load_address = <0x0 0x6000000>;
entrypoint = <0x0 0x6000000>;
diff --git a/plat/arm/board/rdn2/fdts/rdn2_stmm_sel0_manifest.dts b/plat/arm/board/rdn2/fdts/rdn2_stmm_sel0_manifest.dts
index 2cf3f75..6119706 100644
--- a/plat/arm/board/rdn2/fdts/rdn2_stmm_sel0_manifest.dts
+++ b/plat/arm/board/rdn2/fdts/rdn2_stmm_sel0_manifest.dts
@@ -38,7 +38,7 @@
xlat-granule = <0>; /* 4KiB */
boot-order = <0>;
messaging-method = <0x3>; /* Direct request/response supported. */
- power-management-messages = <0x1>;
+ power-management-messages = <0>;
gp-register-num = <0>;
device-regions {
diff --git a/plat/arm/board/tc/fdts/tc_spmc_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_manifest.dts
index b64e076..8ef6330 100644
--- a/plat/arm/board/tc/fdts/tc_spmc_manifest.dts
+++ b/plat/arm/board/tc/fdts/tc_spmc_manifest.dts
@@ -13,7 +13,7 @@
attribute {
spmc_id = <0x8000>;
maj_ver = <0x1>;
- min_ver = <0x1>;
+ min_ver = <0x2>;
exec_state = <0x0>;
load_address = <0x0 0xfd000000>;
entrypoint = <0x0 0xfd000000>;
diff --git a/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
index 382f0e1..73314ee 100644
--- a/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
@@ -13,7 +13,7 @@
attribute {
spmc_id = <0x8000>;
maj_ver = <0x1>;
- min_ver = <0x1>;
+ min_ver = <0x2>;
exec_state = <0x0>;
load_address = <0x0 0xfd000000>;
entrypoint = <0x0 0xfd000000>;
diff --git a/plat/arm/board/tc/plat_tc_mbedtls_config.h b/plat/arm/board/tc/plat_tc_mbedtls_config.h
index f0aa60b..773629c 100644
--- a/plat/arm/board/tc/plat_tc_mbedtls_config.h
+++ b/plat/arm/board/tc/plat_tc_mbedtls_config.h
@@ -22,11 +22,7 @@
#endif
#define MBEDTLS_PSA_CRYPTO_C
-#define MBEDTLS_HMAC_DRBG_C
-#define MBEDTLS_ENTROPY_C
-#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
-#define MBEDTLS_NO_PLATFORM_ENTROPY
-#define MBEDTLS_TEST_NULL_ENTROPY
+#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
#define MBEDTLS_ECP_C
#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index ff7809d..aac7ece 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -9,6 +9,7 @@
#include <libfdt.h>
#include <tc_plat.h>
+#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/arm/css/css_mhu_doorbell.h>
@@ -19,6 +20,36 @@
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
+#ifdef PLATFORM_TEST_TFM_TESTSUITE
+#include <psa/crypto_platform.h>
+#include <psa/crypto_types.h>
+#include <psa/crypto_values.h>
+#endif /* PLATFORM_TEST_TFM_TESTSUITE */
+
+#ifdef PLATFORM_TEST_TFM_TESTSUITE
+/*
+ * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
+ * mbedTLS config option) so we need to provide an implementation of
+ * mbedtls_psa_external_get_random(). Provide a fake one, since we do not
+ * actually use any of external RNG and this function is only needed during
+ * the execution of TF-M testsuite during exporting the public part of the
+ * delegated attestation key.
+ */
+psa_status_t mbedtls_psa_external_get_random(
+ mbedtls_psa_external_random_context_t *context,
+ uint8_t *output, size_t output_size,
+ size_t *output_length)
+{
+ for (size_t i = 0U; i < output_size; i++) {
+ output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU);
+ }
+
+ *output_length = output_size;
+
+ return PSA_SUCCESS;
+}
+#endif /* PLATFORM_TEST_TFM_TESTSUITE */
+
static scmi_channel_plat_info_t tc_scmi_plat_info[] = {
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
diff --git a/plat/intel/soc/common/include/socfpga_reset_manager.h b/plat/intel/soc/common/include/socfpga_reset_manager.h
index 9d06a3d..93cc945 100644
--- a/plat/intel/soc/common/include/socfpga_reset_manager.h
+++ b/plat/intel/soc/common/include/socfpga_reset_manager.h
@@ -155,6 +155,8 @@
#define RSTMGR_HDSKACK_F2SDRAM0ACK 0x00000800
#define RSTMGR_HDSKACK_FPGA2SOCACK 0x00001000
#define RSTMGR_HDSKACK_FPGAHSACK_DASRT 0x00000000
+#define RSTMGR_HDSKACK_LWSOC2FPGAACK_DASRT 0x00000000
+#define RSTMGR_HDSKACK_SOC2FPGAACK_DASRT 0x00000000
#define RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT 0x00000000
#define RSTMGR_HDSKACK_FPGA2SOCACK_DASRT 0x00000000
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
index bd63e02..7aa6b70 100644
--- a/plat/intel/soc/common/soc/socfpga_reset_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -130,6 +130,7 @@
}
#endif
+#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
static int poll_idle_status_by_clkcycles(uint32_t addr, uint32_t mask,
uint32_t match, uint32_t delay_clk_cycles)
{
@@ -144,6 +145,7 @@
}
return -ETIMEDOUT;
}
+#endif
static void socfpga_s2f_bridge_mask(uint32_t mask,
uint32_t *brg_mask,
@@ -425,12 +427,18 @@
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
/* Enable SOC2FPGA bridge */
if (brg_mask & RSTMGR_BRGMODRSTMASK_SOC2FPGA) {
- /* Write Reset Manager hdskreq[soc2fpga_flush_req] = 1 */
- NOTICE("Set S2F hdskreq ...\n");
+ /*
+ * To request handshake
+ * Write Reset Manager hdskreq[soc2fpga_flush_req] = 1
+ */
+ INFO("Set S2F hdskreq ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_SOC2FPGAREQ);
- /* Read Reset Manager hdskack[soc2fpga] = 1 */
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[soc2fpga] = 1
+ */
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_SOC2FPGAACK, RSTMGR_HDSKACK_SOC2FPGAACK,
300);
@@ -439,13 +447,19 @@
ERROR("S2F bridge enable: Timeout hdskack\n");
}
- /* Write Reset Manager hdskreq[soc2fpga_flush_req] = 0 */
- NOTICE("Clear S2F hdskreq ...\n");
+ /*
+ * To clear idle request
+ * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
+ */
+ INFO("Clear S2F hdskreq ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_SOC2FPGAREQ);
- /* Write Reset Manager brgmodrst[soc2fpga] = 1 */
- NOTICE("Assert S2F ...\n");
+ /*
+ * To assert reset
+ * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
+ */
+ INFO("Assert S2F ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_SOC2FPGA);
@@ -454,20 +468,29 @@
/* dummy delay */
}
- /* Write Reset Manager brgmodrst[soc2fpga] = 0 */
- NOTICE("Deassert S2F ...\n");
+ /*
+ * To deassert reset
+ * Write Reset Manager brgmodrst[soc2fpga] = 0
+ */
+ INFO("Deassert S2F ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_SOC2FPGA);
}
/* Enable LWSOC2FPGA bridge */
if (brg_mask & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA) {
- /* Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 1 */
- NOTICE("Set LWS2F hdskreq ...\n");
+ /*
+ * To request handshake
+ * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 1
+ */
+ INFO("Set LWS2F hdskreq ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
- /* Read Reset Manager hdskack[lwsoc2fpga] = 1 */
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[lwsoc2fpga] = 1
+ */
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_LWSOC2FPGAACK, RSTMGR_HDSKACK_LWSOC2FPGAACK,
300);
@@ -476,13 +499,19 @@
ERROR("LWS2F bridge enable: Timeout hdskack\n");
}
- /* Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0 */
- NOTICE("Clear LWS2F hdskreq ...\n");
+ /*
+ * To clear idle request
+ * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0
+ */
+ INFO("Clear LWS2F hdskreq ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
- /* Write Reset Manager brgmodrst[lwsoc2fpga] = 1 */
- NOTICE("Assert LWS2F ...\n");
+ /*
+ * To assert reset
+ * Write Reset Manager brgmodrst[lwsoc2fpga] = 1
+ */
+ INFO("Assert LWS2F ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_LWHPS2FPGA);
@@ -491,8 +520,11 @@
/* dummy delay */
}
- /* Write Reset Manager brgmodrst[lwsoc2fpga] = 0 */
- NOTICE("Deassert LWS2F ...\n");
+ /*
+ * To deassert reset
+ * Write Reset Manager brgmodrst[lwsoc2fpga] = 0
+ */
+ INFO("Deassert LWS2F ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_LWHPS2FPGA);
}
@@ -521,16 +553,25 @@
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
/* Enable FPGA2SOC bridge */
if (brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC) {
- /* Write Reset Manager hdsken[fpgahsen] = 1 */
- NOTICE("Set FPGA hdsken(fpgahsen) ...\n");
+ /*
+ * To request handshake
+ * Write Reset Manager hdsken[fpgahsen] = 1
+ */
+ INFO("Set FPGA hdsken(fpgahsen) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
- /* Write Reset Manager hdskreq[fpgahsreq] = 1 */
- NOTICE("Set FPGA hdskreq(fpgahsreq) ...\n");
+ /*
+ * To request handshake
+ * Write Reset Manager hdskreq[fpgahsreq] = 1
+ */
+ INFO("Set FPGA hdskreq(fpgahsreq) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
- /* Read Reset Manager hdskack[fpgahsack] = 1 */
- NOTICE("Get FPGA hdskack(fpgahsack) ...\n");
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[fpgahsack] = 1
+ */
+ INFO("Get FPGA hdskack(fpgahsack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
300);
@@ -539,13 +580,19 @@
ERROR("FPGA bridge fpga handshake fpgahsreq: Timeout\n");
}
- /* Write Reset Manager hdskreq[f2s_flush_req] = 1 */
- NOTICE("Set F2S hdskreq(f2s_flush_req) ...\n");
+ /*
+ * To fence and drain traffic
+ * Write Reset Manager hdskreq[f2s_flush_req] = 1
+ */
+ INFO("Set F2S hdskreq(f2s_flush_req) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_FPGA2SOCREQ);
- /* Read Reset Manager hdskack[f2s_flush_ack] = 1 */
- NOTICE("Get F2S hdskack(f2s_flush_ack) ...\n");
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[f2s_flush_ack] = 1
+ */
+ INFO("Get F2S hdskack(f2s_flush_ack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK,
300);
@@ -554,17 +601,26 @@
ERROR("F2S bridge fpga handshake f2sdram_flush_req: Timeout\n");
}
- /* Write Reset Manager hdskreq[fpgahsreq] = 1 */
- NOTICE("Clear FPGA hdskreq(fpgahsreq) ...\n");
+ /*
+ * To clear idle request
+ * Write Reset Manager hdskreq[fpgahsreq] = 1
+ */
+ INFO("Clear FPGA hdskreq(fpgahsreq) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
- /* Write Reset Manager hdskreq[f2s_flush_req] = 1 */
- NOTICE("Clear F2S hdskreq(f2s_flush_req) ...\n");
+ /*
+ * To clear idle request
+ * Write Reset Manager hdskreq[f2s_flush_req] = 1
+ */
+ INFO("Clear F2S hdskreq(f2s_flush_req) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_FPGA2SOCREQ);
- /* Read Reset Manager hdskack[f2s_flush_ack] = 0 */
- NOTICE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[f2s_flush_ack] = 0
+ */
+ INFO("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
300);
@@ -573,8 +629,11 @@
ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
}
- /* Read Reset Manager hdskack[fpgahsack] = 0 */
- NOTICE("Get FPGA hdskack(fpgahsack) ...\n");
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[fpgahsack] = 0
+ */
+ INFO("Get FPGA hdskack(fpgahsack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
300);
@@ -583,8 +642,11 @@
ERROR("F2S bridge fpga handshake fpgahsack: Timeout\n");
}
- /* Write Reset Manager brgmodrst[fpga2soc] = 1 */
- NOTICE("Assert F2S ...\n");
+ /*
+ * To assert reset
+ * Write Reset Manager brgmodrst[fpga2soc] = 1
+ */
+ INFO("Assert F2S ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
/* ToDo: Shall use udelay for product release */
@@ -592,28 +654,40 @@
/* dummy delay */
}
- /* Write Reset Manager brgmodrst[fpga2soc] = 0 */
- NOTICE("Deassert F2S ...\n");
+ /*
+ * To deassert reset
+ * Write Reset Manager brgmodrst[fpga2soc] = 0
+ */
+ INFO("Deassert F2S ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
/* Write System Manager f2s bridge control register[f2soc_enable] = 1 */
- NOTICE("Deassert F2S f2soc_enable ...\n");
+ INFO("Deassert F2S f2soc_enable ...\n");
mmio_setbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
SYSMGR_F2S_BRIDGE_CTRL_EN);
}
/* Enable FPGA2SDRAM bridge */
if (brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0) {
- /* Write Reset Manager hdsken[fpgahsen] = 1 */
- NOTICE("Set F2SDRAM hdsken(fpgahsen) ...\n");
+ /*
+ * To request handshake
+ * Write Reset Manager hdsken[fpgahsen] = 1
+ */
+ INFO("Set F2SDRAM hdsken(fpgahsen) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
- /* Write Reset Manager hdskreq[fpgahsreq] = 1 */
- NOTICE("Set F2SDRAM hdskreq(fpgahsreq) ...\n");
+ /*
+ * To request handshake
+ * Write Reset Manager hdskreq[fpgahsreq] = 1
+ */
+ INFO("Set F2SDRAM hdskreq(fpgahsreq) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
- /* Read Reset Manager hdskack[fpgahsack] = 1 */
- NOTICE("Get F2SDRAM hdskack(fpgahsack) ...\n");
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[fpgahsack] = 1
+ */
+ INFO("Get F2SDRAM hdskack(fpgahsack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
300);
@@ -622,13 +696,19 @@
ERROR("F2SDRAM bridge fpga handshake fpgahsreq: Timeout\n");
}
- /* Write Reset Manager hdskreq[f2sdram_flush_req] = 1 */
- NOTICE("Set F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
+ /*
+ * To fence and drain traffic
+ * Write Reset Manager hdskreq[f2sdram_flush_req] = 1
+ */
+ INFO("Set F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_F2SDRAM0REQ);
- /* Read Reset Manager hdskack[f2sdram_flush_ack] = 1 */
- NOTICE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[f2sdram_flush_ack] = 1
+ */
+ INFO("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK,
300);
@@ -637,16 +717,25 @@
ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_req: Timeout\n");
}
- /* Write Reset Manager hdskreq[fpgahsreq] = 1 */
- NOTICE("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
+ /*
+ * To clear idle request
+ * Write Reset Manager hdskreq[fpgahsreq] = 1
+ */
+ INFO("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
- /* Write Reset Manager hdskreq[f2sdram_flush_req] = 1 */
- NOTICE("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
+ /*
+ * To clear idle request
+ * Write Reset Manager hdskreq[f2sdram_flush_req] = 1
+ */
+ INFO("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ);
- /* Read Reset Manager hdskack[f2sdram_flush_ack] = 0 */
- NOTICE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[f2sdram_flush_ack] = 0
+ */
+ INFO("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT,
300);
@@ -655,8 +744,11 @@
ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_ack: Timeout\n");
}
- /* Read Reset Manager hdskack[fpgahsack] = 0 */
- NOTICE("Get F2SDRAM hdskack(fpgahsack) ...\n");
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[fpgahsack] = 0
+ */
+ INFO("Get F2SDRAM hdskack(fpgahsack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
300);
@@ -665,8 +757,11 @@
ERROR("F2SDRAM bridge fpga handshake fpgahsack: Timeout\n");
}
- /* Write Reset Manager brgmodrst[fpga2sdram] = 1 */
- NOTICE("Assert F2SDRAM ...\n");
+ /*
+ * To assert reset
+ * Write Reset Manager brgmodrst[fpga2sdram] = 1
+ */
+ INFO("Assert F2SDRAM ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_F2SSDRAM0);
@@ -675,8 +770,11 @@
/* dummy delay */
}
- /* Write Reset Manager brgmodrst[fpga2sdram] = 0 */
- NOTICE("Deassert F2SDRAM ...\n");
+ /*
+ * To deassert reset
+ * Write Reset Manager brgmodrst[fpga2sdram] = 0
+ */
+ INFO("Deassert F2SDRAM ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_F2SSDRAM0);
@@ -684,7 +782,7 @@
* Clear fpga2sdram_manager_main_SidebandManager_FlagOutClr0
* f2s_ready_latency_enable
*/
- NOTICE("Clear F2SDRAM f2s_ready_latency_enable ...\n");
+ INFO("Clear F2SDRAM f2s_ready_latency_enable ...\n");
mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
FLAGOUTCLR0_F2SDRAM0_ENABLE);
}
@@ -773,9 +871,86 @@
uint32_t f2s_idleack = 0;
uint32_t f2s_respempty = 0;
uint32_t f2s_cmdidle = 0;
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ uint32_t delay = 0;
+#endif
+
/* Disable s2f bridge */
socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ /* Disable SOC2FPGA bridge */
+ if (brg_mask & RSTMGR_BRGMODRSTMASK_SOC2FPGA) {
+ /*
+ * To clear handshake
+ * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
+ */
+ INFO("Set S2F hdskreq ...\n");
+ mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
+ RSTMGR_HDSKREQ_SOC2FPGAREQ);
+
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[soc2fpga] = 0
+ */
+ ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
+ RSTMGR_HDSKACK_SOC2FPGAACK, RSTMGR_HDSKACK_SOC2FPGAACK_DASRT,
+ 300);
+
+ if (ret < 0) {
+ ERROR("S2F bridge enable: Timeout hdskack\n");
+ }
+
+ /*
+ * To assert reset
+ * Write Reset Manager brgmodrst[soc2fpga] = 1
+ */
+ INFO("Assert S2F ...\n");
+ mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
+ RSTMGR_BRGMODRST_SOC2FPGA);
+
+ /* ToDo: Shall use udelay for product release */
+ for (delay = 0; delay < 1000; delay++) {
+ /* dummy delay */
+ }
+ }
+
+ /* Disable LWSOC2FPGA bridge */
+ if (brg_mask & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA) {
+ /*
+ * To clear handshake
+ * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0
+ */
+ INFO("Set LWS2F hdskreq ...\n");
+ mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
+ RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
+
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[lwsoc2fpga] = 0
+ */
+ ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
+ RSTMGR_HDSKACK_LWSOC2FPGAACK, RSTMGR_HDSKACK_LWSOC2FPGAACK_DASRT,
+ 300);
+
+ if (ret < 0) {
+ ERROR("LWS2F bridge enable: Timeout hdskack\n");
+ }
+
+ /*
+ * To assert reset
+ * Write Reset Manager brgmodrst[lwsoc2fpga] = 1
+ */
+ INFO("Assert LWS2F ...\n");
+ mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
+ RSTMGR_BRGMODRST_LWHPS2FPGA);
+
+ /* ToDo: Shall use udelay for product release */
+ for (delay = 0; delay < 1000; delay++) {
+ /* dummy delay */
+ }
+ }
+#else
if (brg_mask != 0U) {
mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET),
noc_mask);
@@ -798,11 +973,152 @@
mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 0);
}
+#endif
/* Disable f2s bridge */
socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
&f2s_force_drain, &f2s_en,
&f2s_idleack, &f2s_respempty, &f2s_cmdidle);
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ /* Disable FPGA2SOC bridge */
+ if (brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC) {
+ /*
+ * To request handshake
+ * Write Reset Manager hdsken[fpgahsen] = 1
+ */
+ INFO("Set FPGA hdsken(fpgahsen) ...\n");
+ mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
+
+ /*
+ * To clear handshake request
+ * Write Reset Manager hdskreq[fpgahsreq] = 0
+ */
+ INFO("Clear FPGA hdskreq(fpgahsreq) ...\n");
+ mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
+
+ /*
+ * To clear handshake request
+ * Write Reset Manager hdskreq[f2s_flush_req] = 0
+ */
+ INFO("Clear F2S hdskreq(f2s_flush_req) ...\n");
+ mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
+ RSTMGR_HDSKREQ_FPGA2SOCREQ);
+
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[f2s_flush_ack] = 0
+ */
+ INFO("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
+ ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
+ RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
+ 300);
+
+ if (ret < 0) {
+ ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
+ }
+
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[fpgahsack] = 0
+ */
+ INFO("Get FPGA hdskack(fpgahsack) ...\n");
+ ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
+ RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
+ 300);
+
+ if (ret < 0) {
+ ERROR("F2S bridge fpga handshake fpgahsack: Timeout\n");
+ }
+
+ /*
+ * To assert reset
+ * Write Reset Manager brgmodrst[fpga2soc] = 1
+ */
+ INFO("Assert F2S ...\n");
+ mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
+
+ /* ToDo: Shall use udelay for product release */
+ for (delay = 0; delay < 1000; delay++) {
+ /* dummy delay */
+ }
+
+ /* Write System Manager f2s bridge control register[f2soc_enable] = 0 */
+ INFO("Assert F2S f2soc_enable ...\n");
+ mmio_clrbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
+ SYSMGR_F2S_BRIDGE_CTRL_EN);
+ }
+
+ /* Disable FPGA2SDRAM bridge */
+ if (brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0) {
+ /*
+ * To request handshake
+ * Write Reset Manager hdsken[fpgahsen] = 1
+ */
+ INFO("Set F2SDRAM hdsken(fpgahsen) ...\n");
+ mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
+
+ /*
+ * To clear handshake request
+ * Write Reset Manager hdskreq[fpgahsreq] = 0
+ */
+ INFO("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
+ mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
+
+ /*
+ * To clear handshake request
+ * Write Reset Manager hdskreq[f2sdram_flush_req] = 0
+ */
+ INFO("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
+ mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ);
+
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[f2sdram_flush_ack] = 0
+ */
+ INFO("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
+ ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
+ RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT,
+ 300);
+
+ if (ret < 0) {
+ ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_ack: Timeout\n");
+ }
+
+ /*
+ * To poll idle status
+ * Read Reset Manager hdskack[fpgahsack] = 0
+ */
+ INFO("Get F2SDRAM hdskack(fpgahsack) ...\n");
+ ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
+ RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
+ 300);
+
+ if (ret < 0) {
+ ERROR("F2SDRAM bridge fpga handshake fpgahsack: Timeout\n");
+ }
+
+ /*
+ * To assert reset
+ * Write Reset Manager brgmodrst[fpga2sdram] = 1
+ */
+ INFO("Assert F2SDRAM ...\n");
+ mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
+ RSTMGR_BRGMODRST_F2SSDRAM0);
+
+ /* ToDo: Shall use udelay for product release */
+ for (delay = 0; delay < 1000; delay++) {
+ /* dummy delay */
+ }
+
+ /*
+ * Assert fpga2sdram_manager_main_SidebandManager_FlagOutClr0
+ * f2s_ready_latency_enable
+ */
+ INFO("Assert F2SDRAM f2s_ready_latency_enable ...\n");
+ mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
+ FLAGOUTCLR0_F2SDRAM0_ENABLE);
+ }
+#else
if (brg_mask != 0U) {
if (mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST)) & brg_mask) {
@@ -831,7 +1147,7 @@
/* Bridge reset */
#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
- /* Software must never write a 0x1 to FPGA2SOC_MASK bit */
+ /* Software must never write a 0x1 to FPGA2SOC_M0ASK bit */
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
brg_mask & ~RSTMGR_FIELD(BRG, FPGA2SOC));
#else
@@ -845,6 +1161,7 @@
mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
f2s_idlereq);
}
+#endif
return ret;
}
diff --git a/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c b/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c
index 1d6863f..64a10f1 100644
--- a/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c
+++ b/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <mtk_iommu_plat.h>
+#include <mtk_iommu_priv.h>
#include <mtk_mmap_pool.h>
#include <platform_def.h>
@@ -42,7 +42,7 @@
#define MMU_DEV_PCIE_0 (0)
#define IFR_CFG_GROUP_NUM (1)
-static struct mtk_smi_larb_config mt8188_larb_cfg[SMI_LARB_NUM] = {
+static struct mtk_smi_larb_config mt8188_larb_cfg[] = {
[SMI_L0_ID] = LARB_CFG_ENTRY(SMI_LARB_0_BASE, 7, 0),
[SMI_L1_ID] = LARB_CFG_ENTRY(SMI_LARB_1_BASE, 7, 0),
[SMI_L2_ID] = LARB_CFG_ENTRY(SMI_LARB_2_BASE, 5, 0),
@@ -80,12 +80,24 @@
static uint32_t mt8188_ifr_mst_cfg_offs[IFR_CFG_GROUP_NUM] = {
PERICFG_AO_IOMMU_1,
};
-static struct mtk_ifr_mst_config mt8188_ifr_mst_cfg[MMU_DEV_NUM] = {
+static struct mtk_ifr_mst_config mt8188_ifr_mst_cfg[] = {
[MMU_DEV_PCIE_0] = IFR_MST_CFG_ENTRY(0, 18),
};
struct mtk_smi_larb_config *g_larb_cfg = &mt8188_larb_cfg[0];
+const unsigned int g_larb_num = ARRAY_SIZE(mt8188_larb_cfg);
+
+static struct mtk_secure_iommu_config mt8188_secure_iommu_config[] = {
+ SEC_IOMMU_CFG_ENTRY(VDO_SECURE_IOMMU_BASE),
+ SEC_IOMMU_CFG_ENTRY(VPP_SECURE_IOMMU_BASE),
+};
+
+struct mtk_secure_iommu_config *g_sec_iommu_cfg = &mt8188_secure_iommu_config[0];
+const unsigned int g_sec_iommu_num = ARRAY_SIZE(mt8188_secure_iommu_config);
+
struct mtk_ifr_mst_config *g_ifr_mst_cfg = &mt8188_ifr_mst_cfg[0];
+const unsigned int g_ifr_mst_num = ARRAY_SIZE(mt8188_ifr_mst_cfg);
+
uint32_t *g_ifr_mst_cfg_base = &mt8188_ifr_mst_cfg_base[0];
uint32_t *g_ifr_mst_cfg_offs = &mt8188_ifr_mst_cfg_offs[0];
diff --git a/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.h b/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.h
index a59e0c7..a3f38a5 100644
--- a/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.h
+++ b/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.h
@@ -7,18 +7,13 @@
#ifndef IOMMU_PLAT_H
#define IOMMU_PLAT_H
-#include <mtk_iommu_priv.h>
-
/* mm iommu */
-#define SMI_LARB_NUM (26)
-extern struct mtk_smi_larb_config *g_larb_cfg;
+#define ATF_MTK_SMI_LARB_CFG_SUPPORT
-/* infra iommu */
-#define MMU_DEV_NUM (1)
-extern struct mtk_ifr_mst_config *g_ifr_mst_cfg;
-extern uint32_t *g_ifr_mst_cfg_base;
-extern uint32_t *g_ifr_mst_cfg_offs;
+/* mm iommu, sec bank dump */
+#define ATF_MTK_IOMMU_CFG_SUPPORT
-extern void mtk_infra_iommu_enable_protect(void);
+/* infra iommu */
+#define ATF_MTK_INFRA_MASTER_CFG_SUPPORT
#endif /* IOMMU_PLAT_H */
diff --git a/plat/mediatek/drivers/iommu/mtk_iommu_priv.h b/plat/mediatek/drivers/iommu/mtk_iommu_priv.h
index 3404d31..bae3694 100644
--- a/plat/mediatek/drivers/iommu/mtk_iommu_priv.h
+++ b/plat/mediatek/drivers/iommu/mtk_iommu_priv.h
@@ -9,6 +9,7 @@
#include <common/debug.h>
#include <lib/mmio.h>
+#include <mtk_iommu_plat.h>
#include <mtk_sip_svc.h>
#define LARB_CFG_ENTRY(bs, p_nr, dom) \
@@ -22,9 +23,13 @@
#define IFR_MST_CFG_ENTRY(idx, bit) \
{ .cfg_addr_idx = (idx), .r_mmu_en_bit = (bit), }
+#define SEC_IOMMU_CFG_ENTRY(s_bs) \
+ { .base = (s_bs), }
+
enum IOMMU_ATF_CMD {
IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to enable iommu */
IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master to enable iommu */
+ IOMMU_ATF_CMD_GET_SECURE_IOMMU_STATUS, /* For secure iommu translation fault report */
IOMMU_ATF_CMD_COUNT,
};
@@ -41,4 +46,30 @@
uint8_t r_mmu_en_bit;
};
+struct mtk_secure_iommu_config {
+ uint32_t base;
+};
+
+
+#ifdef ATF_MTK_SMI_LARB_CFG_SUPPORT
+/* mm smi larb security feature is used */
+extern struct mtk_smi_larb_config *g_larb_cfg;
+extern const unsigned int g_larb_num;
+#endif
+
+#ifdef ATF_MTK_INFRA_MASTER_CFG_SUPPORT
+/* infra iommu is used */
+extern struct mtk_ifr_mst_config *g_ifr_mst_cfg;
+extern const unsigned int g_ifr_mst_num;
+extern uint32_t *g_ifr_mst_cfg_base;
+extern uint32_t *g_ifr_mst_cfg_offs;
+extern void mtk_infra_iommu_enable_protect(void);
+#endif
+
+#ifdef ATF_MTK_IOMMU_CFG_SUPPORT
+/* secure iommu is used */
+extern struct mtk_secure_iommu_config *g_sec_iommu_cfg;
+extern const unsigned int g_sec_iommu_num;
+#endif
+
#endif /* IOMMU_PRIV_H */
diff --git a/plat/mediatek/drivers/iommu/mtk_iommu_smc.c b/plat/mediatek/drivers/iommu/mtk_iommu_smc.c
index e998725..7d70114 100644
--- a/plat/mediatek/drivers/iommu/mtk_iommu_smc.c
+++ b/plat/mediatek/drivers/iommu/mtk_iommu_smc.c
@@ -5,7 +5,7 @@
*/
#include <stddef.h>
-#include <mtk_iommu_plat.h>
+#include <mtk_iommu_priv.h>
/* defination */
/* smi larb */
@@ -23,12 +23,23 @@
/* infra master */
#define IFR_CFG_MMU_EN_MSK(r_bit) (0x3 << (r_bit))
+/* secure iommu */
+#define MMU_INT_CONTROL0 (0x120)
+#define INT_CLR BIT(12)
+#define MMU_FAULT_ST1 (0x134)
+#define MMU_AXI_0_ERR_MASK GENMASK(6, 0)
+#define MMU_AXI_FAULT_STATUS(bus) (0x13c + (bus) * 8)
+#define MMU_AXI_INVLD_PA(bus) (0x140 + (bus) * 8)
+#define MMU_AXI_INT_ID(bus) (0x150 + (bus) * 4)
+
/* smi larb configure */
/*
* If multimedia security config is enabled, the SMI config register must be
* configurated in security world.
* And the SRAM path is also configurated here to enhance security.
*/
+#ifdef ATF_MTK_SMI_LARB_CFG_SUPPORT
+
static void mtk_smi_larb_port_config_to_sram(
const struct mtk_smi_larb_config *larb,
uint32_t port_id)
@@ -55,7 +66,7 @@
uint32_t to_sram;
uint8_t mmu_en;
- if (larb_id >= SMI_LARB_NUM) {
+ if (larb_id >= g_larb_num) {
return MTK_SIP_E_INVALID_PARAM;
}
@@ -75,6 +86,11 @@
return MTK_SIP_E_SUCCESS;
}
+#endif /* ATF_MTK_SMI_LARB_CFG_SUPPORT */
+
+/* infra iommu configure */
+#ifdef ATF_MTK_INFRA_MASTER_CFG_SUPPORT
+
static int mtk_infra_master_config_sec(uint32_t dev_id_msk, uint32_t enable)
{
const struct mtk_ifr_mst_config *ifr_cfg;
@@ -82,11 +98,11 @@
mtk_infra_iommu_enable_protect();
- if (dev_id_msk >= BIT(MMU_DEV_NUM)) {
+ if (dev_id_msk >= BIT(g_ifr_mst_num)) {
return MTK_SIP_E_INVALID_PARAM;
}
- for (dev_id = 0U; dev_id < MMU_DEV_NUM; dev_id++) {
+ for (dev_id = 0U; dev_id < g_ifr_mst_num; dev_id++) {
if ((dev_id_msk & BIT(dev_id)) == 0U) {
continue;
}
@@ -105,10 +121,50 @@
return MTK_SIP_E_SUCCESS;
}
+#endif /* ATF_MTK_INFRA_MASTER_CFG_SUPPORT */
+
+/* secure iommu */
+#ifdef ATF_MTK_IOMMU_CFG_SUPPORT
+/* Report secure IOMMU fault status to normal world for the debug version */
+static int mtk_secure_iommu_fault_report(uint32_t sec_mmu_base,
+ uint32_t *f_sta, uint32_t *f_pa,
+ uint32_t *f_id)
+{
+ const struct mtk_secure_iommu_config *mmu_cfg = NULL;
+ uint32_t __maybe_unused bus_id, fault_type;
+ uint32_t i;
+ int ret = MTK_SIP_E_NOT_SUPPORTED;
+
+ for (i = 0; i < g_sec_iommu_num; i++) {
+ if (g_sec_iommu_cfg[i].base == sec_mmu_base) {
+ mmu_cfg = &g_sec_iommu_cfg[i];
+ break;
+ }
+ }
+
+ if (!mmu_cfg)
+ return MTK_SIP_E_INVALID_PARAM;
+#if DEBUG
+ fault_type = mmio_read_32(mmu_cfg->base + MMU_FAULT_ST1);
+ bus_id = (fault_type & MMU_AXI_0_ERR_MASK) ? 0 : 1;
+
+ if (f_sta)
+ *f_sta = mmio_read_32(mmu_cfg->base + MMU_AXI_FAULT_STATUS(bus_id));
+ if (f_pa)
+ *f_pa = mmio_read_32(mmu_cfg->base + MMU_AXI_INVLD_PA(bus_id));
+ if (f_id)
+ *f_id = mmio_read_32(mmu_cfg->base + MMU_AXI_INT_ID(bus_id));
+ ret = MTK_SIP_E_SUCCESS;
+#endif
+ mmio_setbits_32(mmu_cfg->base + MMU_INT_CONTROL0, INT_CLR);
+
+ return ret;
+}
+#endif /* ATF_MTK_IOMMU_CFG_SUPPORT */
-static u_register_t mtk_iommu_handler(u_register_t x1, u_register_t x2,
- u_register_t x3, u_register_t x4,
- void *handle, struct smccc_res *smccc_ret)
+u_register_t mtk_iommu_handler(u_register_t x1, u_register_t x2,
+ u_register_t x3, u_register_t x4,
+ void *handle, struct smccc_res *smccc_ret)
{
uint32_t cmd_id = x1, mdl_id = x2, val = x3;
int ret = MTK_SIP_E_NOT_SUPPORTED;
@@ -117,12 +173,25 @@
(void)handle;
switch (cmd_id) {
+#ifdef ATF_MTK_SMI_LARB_CFG_SUPPORT
case IOMMU_ATF_CMD_CONFIG_SMI_LARB:
ret = mtk_smi_larb_port_config_sec(mdl_id, val);
break;
+#endif
+#ifdef ATF_MTK_INFRA_MASTER_CFG_SUPPORT
case IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU:
ret = mtk_infra_master_config_sec(mdl_id, val);
break;
+#endif
+#ifdef ATF_MTK_IOMMU_CFG_SUPPORT
+ case IOMMU_ATF_CMD_GET_SECURE_IOMMU_STATUS:
+ (void)val;
+ ret = mtk_secure_iommu_fault_report(mdl_id,
+ (uint32_t *)&smccc_ret->a1,
+ (uint32_t *)&smccc_ret->a2,
+ (uint32_t *)&smccc_ret->a3);
+ break;
+#endif
default:
break;
}
diff --git a/plat/mediatek/drivers/iommu/mtk_iommu_smc.h b/plat/mediatek/drivers/iommu/mtk_iommu_smc.h
new file mode 100644
index 0000000..9537dbe
--- /dev/null
+++ b/plat/mediatek/drivers/iommu/mtk_iommu_smc.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IOMMU_SMC_H
+#define IOMMU_SMC_H
+
+#include <mtk_sip_svc.h>
+
+u_register_t mtk_iommu_handler(u_register_t x1, u_register_t x2,
+ u_register_t x3, u_register_t x4,
+ void *handle, struct smccc_res *smccc_ret);
+#endif
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index 0a7ae6d..71a4e97 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -107,7 +107,13 @@
#define CIRQ_SPI_START (96)
/*******************************************************************************
- * MM IOMMU & SMI related constants
+ * MM IOMMU related constants
+ ******************************************************************************/
+#define VDO_SECURE_IOMMU_BASE (IO_PHYS + 0x0c028000 + 0x4000)
+#define VPP_SECURE_IOMMU_BASE (IO_PHYS + 0x04018000 + 0x4000)
+
+/*******************************************************************************
+ * SMI larb constants
******************************************************************************/
#define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000)
#define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000)
diff --git a/plat/xilinx/versal_net/include/plat_ipi.h b/plat/xilinx/versal_net/include/plat_ipi.h
index 9f9947e..e0fe723 100644
--- a/plat/xilinx/versal_net/include/plat_ipi.h
+++ b/plat/xilinx/versal_net/include/plat_ipi.h
@@ -24,7 +24,15 @@
#define IPI_ID_3 5U
#define IPI_ID_4 6U
#define IPI_ID_5 7U
-#define IPI_ID_MAX 8U
+#define IPI_ID_PMC_NOBUF 8U
+#define IPI_ID_6_NOBUF_95 9U
+#define IPI_ID_1_NOBUF 10U
+#define IPI_ID_2_NOBUF 11U
+#define IPI_ID_3_NOBUF 12U
+#define IPI_ID_4_NOBUF 13U
+#define IPI_ID_5_NOBUF 14U
+#define IPI_ID_6_NOBUF_101 15U
+#define IPI_ID_MAX 16U
/*********************************************************************
* IPI message buffers
@@ -68,5 +76,21 @@
#define IPI4_TRIG_BIT (1 << 6)
#define IPI5_REG_BASE (0xEB380000U)
#define IPI5_TRIG_BIT (1 << 7)
+#define PMC_NOBUF_REG_BASE (0xEB390000U)
+#define PMC_NOBUF_TRIG_BIT (1 << 8)
+#define IPI6_NOBUF_95_REG_BASE (0xEB3A0000U)
+#define IPI6_NOBUF_95_TRIG_BIT (1 << 9)
+#define IPI1_NOBUF_REG_BASE (0xEB3B0000U)
+#define IPI1_NOBUF_TRIG_BIT (1 << 10)
+#define IPI2_NOBUF_REG_BASE (0xEB3B1000U)
+#define IPI2_NOBUF_TRIG_BIT (1 << 11)
+#define IPI3_NOBUF_REG_BASE (0xEB3B2000U)
+#define IPI3_NOBUF_TRIG_BIT (1 << 12)
+#define IPI4_NOBUF_REG_BASE (0xEB3B3000U)
+#define IPI4_NOBUF_TRIG_BIT (1 << 13)
+#define IPI5_NOBUF_REG_BASE (0xEB3B4000U)
+#define IPI5_NOBUF_TRIG_BIT (1 << 14)
+#define IPI6_NOBUF_101_REG_BASE (0xEB3B5000U)
+#define IPI6_NOBUF_101_TRIG_BIT (1 << 15)
#endif /* PLAT_IPI_H */
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index f299189..65ebaaa 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -93,7 +93,9 @@
plat/arm/common/arm_common.c \
plat/common/plat_gicv3.c \
${PLAT_PATH}/aarch64/versal_net_helpers.S \
- ${PLAT_PATH}/aarch64/versal_net_common.c
+ ${PLAT_PATH}/aarch64/versal_net_common.c \
+ ${PLAT_PATH}/plat_topology.c \
+ ${XLAT_TABLES_LIB_SRCS}
BL31_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/cortex_a78_ae.S \
@@ -116,10 +118,8 @@
plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
plat/xilinx/common/versal.c \
${PLAT_PATH}/bl31_versal_net_setup.c \
- ${PLAT_PATH}/plat_topology.c \
common/fdt_fixup.c \
common/fdt_wrappers.c \
${LIBFDT_SRCS} \
${PLAT_PATH}/sip_svc_setup.c \
- ${PLAT_PATH}/versal_net_gicv3.c \
- ${XLAT_TABLES_LIB_SRCS}
+ ${PLAT_PATH}/versal_net_gicv3.c
diff --git a/plat/xilinx/versal_net/tsp/tsp-versal_net.mk b/plat/xilinx/versal_net/tsp/tsp-versal_net.mk
index 87638ab..ab7871c 100644
--- a/plat/xilinx/versal_net/tsp/tsp-versal_net.mk
+++ b/plat/xilinx/versal_net/tsp/tsp-versal_net.mk
@@ -8,6 +8,3 @@
PLAT_XILINX_COMMON := plat/xilinx/common/
include ${PLAT_XILINX_COMMON}/tsp/tsp.mk
-
-BL32_SOURCES += plat/xilinx/versal_net/plat_topology.c \
- ${XLAT_TABLES_LIB_SRCS}
diff --git a/plat/xilinx/versal_net/versal_net_ipi.c b/plat/xilinx/versal_net/versal_net_ipi.c
index e8d8fb7..7c38921 100644
--- a/plat/xilinx/versal_net/versal_net_ipi.c
+++ b/plat/xilinx/versal_net/versal_net_ipi.c
@@ -63,6 +63,62 @@
.ipi_reg_base = IPI5_REG_BASE,
.secure_only = 0,
},
+
+ /* PMC_NOBUF IPI */
+ [IPI_ID_PMC_NOBUF] = {
+ .ipi_bit_mask = PMC_NOBUF_TRIG_BIT,
+ .ipi_reg_base = PMC_NOBUF_REG_BASE,
+ .secure_only = IPI_SECURE_MASK,
+ },
+
+ /* IPI6 IPI */
+ [IPI_ID_6_NOBUF_95] = {
+ .ipi_bit_mask = IPI6_NOBUF_95_TRIG_BIT,
+ .ipi_reg_base = IPI6_NOBUF_95_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI1 NO BUF IPI */
+ [IPI_ID_1_NOBUF] = {
+ .ipi_bit_mask = IPI1_NOBUF_TRIG_BIT,
+ .ipi_reg_base = IPI1_NOBUF_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI2 NO BUF IPI */
+ [IPI_ID_2_NOBUF] = {
+ .ipi_bit_mask = IPI2_NOBUF_TRIG_BIT,
+ .ipi_reg_base = IPI2_NOBUF_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI3 NO BUF IPI */
+ [IPI_ID_3_NOBUF] = {
+ .ipi_bit_mask = IPI3_NOBUF_TRIG_BIT,
+ .ipi_reg_base = IPI3_NOBUF_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI4 NO BUF IPI */
+ [IPI_ID_4_NOBUF] = {
+ .ipi_bit_mask = IPI4_NOBUF_TRIG_BIT,
+ .ipi_reg_base = IPI4_NOBUF_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI5 NO BUF IPI */
+ [IPI_ID_5_NOBUF] = {
+ .ipi_bit_mask = IPI5_NOBUF_TRIG_BIT,
+ .ipi_reg_base = IPI5_NOBUF_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI6 NO BUF IPI */
+ [IPI_ID_6_NOBUF_101] = {
+ .ipi_bit_mask = IPI6_NOBUF_101_TRIG_BIT,
+ .ipi_reg_base = IPI6_NOBUF_101_REG_BASE,
+ .secure_only = 0,
+ },
};
/* versal_net_ipi_config_table_init() - Initialize versal_net IPI configuration
diff --git a/services/std_svc/spm/el3_spmc/spmc_main.c b/services/std_svc/spm/el3_spmc/spmc_main.c
index 42747bf..7978f08 100644
--- a/services/std_svc/spm/el3_spmc/spmc_main.c
+++ b/services/std_svc/spm/el3_spmc/spmc_main.c
@@ -1902,6 +1902,11 @@
if (ret != 0) {
WARN("Missing Power Management Messages entry.\n");
} else {
+ if ((sp->runtime_el == S_EL0) && (config_32 != 0)) {
+ ERROR("Power messages not supported for S-EL0 SP\n");
+ return -EINVAL;
+ }
+
/*
* Ensure only the currently supported power messages have
* been requested.
diff --git a/services/std_svc/spm/el3_spmc/spmc_pm.c b/services/std_svc/spm/el3_spmc/spmc_pm.c
index c7e864f..517d6d5 100644
--- a/services/std_svc/spm/el3_spmc/spmc_pm.c
+++ b/services/std_svc/spm/el3_spmc/spmc_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,7 +36,7 @@
}
/*******************************************************************************
- * This CPU has been turned on. Enter the SP to initialise S-EL1.
+ * This CPU has been turned on. Enter the SP to initialise S-EL0 or S-EL1.
******************************************************************************/
static void spmc_cpu_on_finish_handler(u_register_t unused)
{
@@ -49,6 +49,19 @@
/* Sanity check for a NULL pointer dereference. */
assert(sp != NULL);
+ /* Obtain a reference to the SP execution context */
+ ec = &sp->ec[get_ec_index(sp)];
+
+ /*
+ * In case of a S-EL0 SP, only initialise the context data structure for
+ * the secure world on this cpu and return.
+ */
+ if (sp->runtime_el == S_EL0) {
+ /* Assign the context of the SP to this CPU */
+ cm_set_context(&(ec->cpu_ctx), SECURE);
+ return;
+ }
+
/* Initialize entry point information for the SP. */
SET_PARAM_HEAD(&sec_ec_ep_info, PARAM_EP, VERSION_1,
SECURE | EP_ST_ENABLE);