Merge "fix(tc): enable FEAT_MTE2" into integration
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 962c362..e47b082 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -450,7 +450,7 @@
*
* handler = (base + off) + (index << log2(size))
*/
- adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
+ adr_l x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
lsl w10, w15, #RT_SVC_SIZE_LOG2
ldr x15, [x11, w10, uxtw]
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index cd61d01..40add91 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -52,13 +52,17 @@
${SPMC_SOURCES} \
${SPM_SOURCES}
+VENDOR_EL3_SRCS += services/el3/ven_el3_svc.c
+
ifeq (${ENABLE_PMF}, 1)
-BL31_SOURCES += lib/pmf/pmf_main.c
+BL31_SOURCES += lib/pmf/pmf_main.c \
+ ${VENDOR_EL3_SRCS}
endif
include lib/debugfs/debugfs.mk
ifeq (${USE_DEBUGFS},1)
- BL31_SOURCES += $(DEBUGFS_SRCS)
+BL31_SOURCES += ${DEBUGFS_SRCS} \
+ ${VENDOR_EL3_SRCS}
endif
ifeq (${PLATFORM_REPORT_CTX_MEM_USE},1)
diff --git a/bl31/bl31_traps.c b/bl31/bl31_traps.c
index 474b4d5..47a555a 100644
--- a/bl31/bl31_traps.c
+++ b/bl31/bl31_traps.c
@@ -36,7 +36,7 @@
{
u_register_t hcr_el2 = read_hcr_el2();
- return ((read_feat_vhe_id_field() != 0U) && ((hcr_el2 & HCR_TGE_BIT) != 0U));
+ return ((is_feat_vhe_present()) && ((hcr_el2 & HCR_TGE_BIT) != 0U));
}
/*
@@ -116,7 +116,7 @@
/* If FEAT_BTI is present, clear BTYPE bits */
new_spsr |= old_spsr & (SPSR_BTYPE_MASK_AARCH64 << SPSR_BTYPE_SHIFT_AARCH64);
- if (is_armv8_5_bti_present()) {
+ if (is_feat_bti_present()) {
new_spsr &= ~(SPSR_BTYPE_MASK_AARCH64 << SPSR_BTYPE_SHIFT_AARCH64);
}
diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk
index 427e39b..b1f4343 100644
--- a/bl32/sp_min/sp_min.mk
+++ b/bl32/sp_min/sp_min.mk
@@ -13,16 +13,17 @@
INCLUDES += -Iinclude/bl32/sp_min
-BL32_SOURCES += bl32/sp_min/sp_min_main.c \
- bl32/sp_min/aarch32/entrypoint.S \
- common/runtime_svc.c \
- plat/common/aarch32/plat_sp_min_common.c\
+BL32_SOURCES += bl32/sp_min/sp_min_main.c \
+ bl32/sp_min/aarch32/entrypoint.S \
+ common/runtime_svc.c \
+ plat/common/aarch32/plat_sp_min_common.c \
services/arm_arch_svc/arm_arch_svc_setup.c \
- services/std_svc/std_svc_setup.c \
+ services/std_svc/std_svc_setup.c \
${PSCI_LIB_SOURCES}
ifeq (${ENABLE_PMF}, 1)
-BL32_SOURCES += lib/pmf/pmf_main.c
+BL32_SOURCES += services/el3/ven_el3_svc.c \
+ lib/pmf/pmf_main.c
endif
ifneq (${ENABLE_FEAT_AMU},0)
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 7f01037..09088c9 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -70,37 +70,187 @@
#endif
}
-/****************************************************
- * Feature : FEAT_BTI (Branch Target Identification)
- ***************************************************/
-static void read_feat_bti(void)
+static unsigned int read_feat_rng_trap_id_field(void)
{
-#if (ENABLE_BTI == FEAT_STATE_ALWAYS)
- feat_detect_panic(is_armv8_5_bti_present(), "BTI");
-#endif
+ return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT,
+ ID_AA64PFR1_EL1_RNDR_TRAP_MASK);
}
-/**************************************************
- * Feature : FEAT_RME (Realm Management Extension)
- *************************************************/
-static void read_feat_rme(void)
+static unsigned int read_feat_bti_id_field(void)
{
-#if (ENABLE_RME == FEAT_STATE_ALWAYS)
- feat_detect_panic((get_armv9_2_feat_rme_support() !=
- ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED), "RME");
-#endif
+ return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_BT_SHIFT,
+ ID_AA64PFR1_EL1_BT_MASK);
}
-/******************************************************************
- * Feature : FEAT_RNG_TRAP (Trapping support for RNDR/RNDRRS)
- *****************************************************************/
-static void read_feat_rng_trap(void)
+static unsigned int read_feat_sb_id_field(void)
{
-#if (ENABLE_FEAT_RNG_TRAP == FEAT_STATE_ALWAYS)
- feat_detect_panic(is_feat_rng_trap_present(), "RNG_TRAP");
-#endif
+ return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT,
+ ID_AA64ISAR1_SB_MASK);
}
+static unsigned int read_feat_csv2_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2_SHIFT,
+ ID_AA64PFR0_CSV2_MASK);
+}
+
+static unsigned int read_feat_pmuv3_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT,
+ ID_AA64DFR0_PMUVER_MASK);
+}
+
+static unsigned int read_feat_vhe_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE_SHIFT,
+ ID_AA64MMFR1_EL1_VHE_MASK);
+}
+
+static unsigned int read_feat_sve_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE_SHIFT,
+ ID_AA64PFR0_SVE_MASK);
+}
+
+static unsigned int read_feat_ras_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS_SHIFT,
+ ID_AA64PFR0_RAS_MASK);
+}
+
+static unsigned int read_feat_dit_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT_SHIFT,
+ ID_AA64PFR0_DIT_MASK);
+}
+
+static unsigned int read_feat_amu_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU_SHIFT,
+ ID_AA64PFR0_AMU_MASK);
+}
+
+static unsigned int read_feat_mpam_version(void)
+{
+ return (unsigned int)((((read_id_aa64pfr0_el1() >>
+ ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
+ ((read_id_aa64pfr1_el1() >>
+ ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
+}
+
+static unsigned int read_feat_nv_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV_SHIFT,
+ ID_AA64MMFR2_EL1_NV_MASK);
+}
+
+static unsigned int read_feat_sel2_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2_SHIFT,
+ ID_AA64PFR0_SEL2_MASK);
+}
+
+static unsigned int read_feat_trf_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT_SHIFT,
+ ID_AA64DFR0_TRACEFILT_MASK);
+}
+static unsigned int get_armv8_5_mte_support(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_MTE_SHIFT,
+ ID_AA64PFR1_EL1_MTE_MASK);
+}
+static unsigned int read_feat_rng_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR_SHIFT,
+ ID_AA64ISAR0_RNDR_MASK);
+}
+static unsigned int read_feat_fgt_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT_SHIFT,
+ ID_AA64MMFR0_EL1_FGT_MASK);
+}
+static unsigned int read_feat_ecv_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV_SHIFT,
+ ID_AA64MMFR0_EL1_ECV_MASK);
+}
+static unsigned int read_feat_twed_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED_SHIFT,
+ ID_AA64MMFR1_EL1_TWED_MASK);
+}
+
+static unsigned int read_feat_hcx_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX_SHIFT,
+ ID_AA64MMFR1_EL1_HCX_MASK);
+}
+static unsigned int read_feat_tcr2_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX_SHIFT,
+ ID_AA64MMFR3_EL1_TCRX_MASK);
+}
+static unsigned int read_feat_s2pie_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE_SHIFT,
+ ID_AA64MMFR3_EL1_S2PIE_MASK);
+}
+static unsigned int read_feat_s1pie_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE_SHIFT,
+ ID_AA64MMFR3_EL1_S1PIE_MASK);
+}
+static unsigned int read_feat_s2poe_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE_SHIFT,
+ ID_AA64MMFR3_EL1_S2POE_MASK);
+}
+static unsigned int read_feat_s1poe_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE_SHIFT,
+ ID_AA64MMFR3_EL1_S1POE_MASK);
+}
+static unsigned int read_feat_brbe_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE_SHIFT,
+ ID_AA64DFR0_BRBE_MASK);
+}
+static unsigned int read_feat_trbe_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER_SHIFT,
+ ID_AA64DFR0_TRACEBUFFER_MASK);
+}
+static unsigned int read_feat_sme_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME_SHIFT,
+ ID_AA64PFR1_EL1_SME_MASK);
+}
+static unsigned int read_feat_gcs_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS_SHIFT,
+ ID_AA64PFR1_EL1_GCS_MASK);
+}
+
+static unsigned int read_feat_rme_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_FEAT_RME_SHIFT,
+ ID_AA64PFR0_FEAT_RME_MASK);
+}
+
+static unsigned int read_feat_pan_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN_SHIFT,
+ ID_AA64MMFR1_EL1_PAN_MASK);
+}
+
+static unsigned int read_feat_mtpmu_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
+ ID_AA64DFR0_MTPMU_MASK);
+
+}
+
/***********************************************************************************
* TF-A supports many Arm architectural features starting from arch version
* (8.0 till 8.7+). These features are mostly enabled through build flags. This
@@ -151,6 +301,7 @@
check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), "RAS", 1, 2);
/* v8.3 features */
+ /* TODO: Pauth yet to convert to tri-state feat detect logic */
read_feat_pauth();
/* v8.4 features */
@@ -170,8 +321,9 @@
check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), "MTE2",
MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY);
check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), "RNG", 1, 1);
- read_feat_bti();
- read_feat_rng_trap();
+ check_feature(ENABLE_BTI, read_feat_bti_id_field(), "BTI", 1, 1);
+ check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(),
+ "RNG_TRAP", 1, 1);
/* v8.6 features */
check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(),
@@ -219,8 +371,7 @@
/* v9.4 features */
check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);
-
- read_feat_rme();
+ check_feature(ENABLE_RME, read_feat_rme_id_field(), "RME", 1, 1);
if (tainted) {
panic();
diff --git a/docs/components/arm-sip-service.rst b/docs/components/arm-sip-service.rst
index b51a94d..74a40a3 100644
--- a/docs/components/arm-sip-service.rst
+++ b/docs/components/arm-sip-service.rst
@@ -15,19 +15,20 @@
The Arm SiP implementation offers the following services:
-- Performance Measurement Framework (PMF)
- Execution State Switching service
-- DebugFS interface
Source definitions for Arm SiP service are located in the ``arm_sip_svc.h`` header
file.
-Performance Measurement Framework (PMF)
----------------------------------------
++----------------------------+----------------------------+---------------------------------------+
+| ARM_SIP_SVC_VERSION_MAJOR | ARM_SIP_SVC_VERSION_MINOR | Changes |
++============================+============================+=======================================+
+| 1 | 0 | Move DebugFS and PMF to the new vendor|
+| | | specific FID range. The old FID range |
+| | | for these services are deprecated |
++----------------------------+----------------------------+---------------------------------------+
-The :ref:`Performance Measurement Framework <firmware_design_pmf>`
-allows callers to retrieve timestamps captured at various paths in TF-A
-execution.
+*Table 1: Showing different versions of arm-sip-service and changes done with each version*
Execution State Switching service
---------------------------------
@@ -88,348 +89,8 @@
and 1 populated with the supplied *Cookie hi* and *Cookie lo* values,
respectively.
-DebugFS interface
------------------
-
-The optional DebugFS interface is accessed through an SMC SiP service. Refer
-to the component documentation for details.
-
-String parameters are passed through a shared buffer using a specific union:
-
-.. code:: c
-
- union debugfs_parms {
- struct {
- char fname[MAX_PATH_LEN];
- } open;
-
- struct mount {
- char srv[MAX_PATH_LEN];
- char where[MAX_PATH_LEN];
- char spec[MAX_PATH_LEN];
- } mount;
-
- struct {
- char path[MAX_PATH_LEN];
- dir_t dir;
- } stat;
-
- struct {
- char oldpath[MAX_PATH_LEN];
- char newpath[MAX_PATH_LEN];
- } bind;
- };
-
-Format of the dir_t structure as such:
-
-.. code:: c
-
- typedef struct {
- char name[NAMELEN];
- long length;
- unsigned char mode;
- unsigned char index;
- unsigned char dev;
- qid_t qid;
- } dir_t;
-
-
-* Identifiers
-
-======================== =============================================
-SMC_OK 0
-SMC_UNK -1
-DEBUGFS_E_INVALID_PARAMS -2
-======================== =============================================
-
-======================== =============================================
-MOUNT 0
-CREATE 1
-OPEN 2
-CLOSE 3
-READ 4
-WRITE 5
-SEEK 6
-BIND 7
-STAT 8
-INIT 10
-VERSION 11
-======================== =============================================
-
-MOUNT
-~~~~~
-
-Description
-^^^^^^^^^^^
-This operation mounts a blob of data pointed to by path stored in `src`, at
-filesystem location pointed to by path stored in `where`, using driver pointed
-to by path in `spec`.
-
-Parameters
-^^^^^^^^^^
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``MOUNT``
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if mount operation failed
-=============== ==========================================================
-
-OPEN
-~~~~
-
-Description
-^^^^^^^^^^^
-This operation opens the file path pointed to by `fname`.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``OPEN``
-uint32_t mode
-======== ============================================================
-
-mode can be one of:
-
-.. code:: c
-
- enum mode {
- O_READ = 1 << 0,
- O_WRITE = 1 << 1,
- O_RDWR = 1 << 2,
- O_BIND = 1 << 3,
- O_DIR = 1 << 4,
- O_STAT = 1 << 5
- };
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if open operation failed
-
-uint32_t w1: file descriptor id on success.
-=============== ==========================================================
-
-CLOSE
-~~~~~
-
-Description
-^^^^^^^^^^^
-
-This operation closes a file described by a file descriptor obtained by a
-previous call to OPEN.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``CLOSE``
-uint32_t File descriptor id returned by OPEN
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if close operation failed
-=============== ==========================================================
-
-READ
-~~~~
-
-Description
-^^^^^^^^^^^
-
-This operation reads a number of bytes from a file descriptor obtained by
-a previous call to OPEN.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``READ``
-uint32_t File descriptor id returned by OPEN
-uint32_t Number of bytes to read
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-On success, the read data is retrieved from the shared buffer after the
-operation.
-
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if read operation failed
-
-uint32_t w1: number of bytes read on success.
-=============== ==========================================================
-
-SEEK
-~~~~
-
-Description
-^^^^^^^^^^^
-
-Move file pointer for file described by given `file descriptor` of given
-`offset` related to `whence`.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``SEEK``
-uint32_t File descriptor id returned by OPEN
-sint32_t offset in the file relative to whence
-uint32_t whence
-======== ============================================================
-
-whence can be one of:
-
-========= ============================================================
-KSEEK_SET 0
-KSEEK_CUR 1
-KSEEK_END 2
-========= ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if seek operation failed
-=============== ==========================================================
-
-BIND
-~~~~
-
-Description
-^^^^^^^^^^^
-
-Create a link from `oldpath` to `newpath`.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``BIND``
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if bind operation failed
-=============== ==========================================================
-
-STAT
-~~~~
-
-Description
-^^^^^^^^^^^
-
-Perform a stat operation on provided file `name` and returns the directory
-entry statistics into `dir`.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``STAT``
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if stat operation failed
-=============== ==========================================================
-
-INIT
-~~~~
-
-Description
-^^^^^^^^^^^
-Initial call to setup the shared exchange buffer. Notice if successful once,
-subsequent calls fail after a first initialization. The caller maps the same
-page frame in its virtual space and uses this buffer to exchange string
-parameters with filesystem primitives.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``INIT``
-uint64_t Physical address of the shared buffer.
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ======================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if already initialized,
- or internal error occurred.
-=============== ======================================================
-
-VERSION
-~~~~~~~
-
-Description
-^^^^^^^^^^^
-Returns the debugfs interface version if implemented in TF-A.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``VERSION``
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ======================================================
-int32_t w0 == SMC_OK on success
-
- w0 == SMC_UNK if interface is not implemented
-
-uint32_t w1: On success, debugfs interface version, 32 bits
- value with major version number in upper 16 bits and
- minor version in lower 16 bits.
-=============== ======================================================
-
-* CREATE(1) and WRITE (5) command identifiers are unimplemented and
- return `SMC_UNK`.
-
--------------
-*Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.*
.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
diff --git a/docs/components/index.rst b/docs/components/index.rst
index 30d80fc..18522f8 100644
--- a/docs/components/index.rst
+++ b/docs/components/index.rst
@@ -26,3 +26,5 @@
realm-management-extension
rmm-el3-comms-spec
granule-protection-tables-design
+ ven-el3-service
+ ven-el3-debugfs
diff --git a/docs/components/ven-el3-debugfs.rst b/docs/components/ven-el3-debugfs.rst
new file mode 100644
index 0000000..8629d70
--- /dev/null
+++ b/docs/components/ven-el3-debugfs.rst
@@ -0,0 +1,343 @@
+DebugFS interface
+=================
+
+The optional DebugFS interface is accessed through a Vendor specific EL3 service. Refer
+to the component documentation for details.
+
+String parameters are passed through a shared buffer using a specific union:
+
+.. code:: c
+
+ union debugfs_parms {
+ struct {
+ char fname[MAX_PATH_LEN];
+ } open;
+
+ struct mount {
+ char srv[MAX_PATH_LEN];
+ char where[MAX_PATH_LEN];
+ char spec[MAX_PATH_LEN];
+ } mount;
+
+ struct {
+ char path[MAX_PATH_LEN];
+ dir_t dir;
+ } stat;
+
+ struct {
+ char oldpath[MAX_PATH_LEN];
+ char newpath[MAX_PATH_LEN];
+ } bind;
+ };
+
+Format of the dir_t structure as such:
+
+.. code:: c
+
+ typedef struct {
+ char name[NAMELEN];
+ long length;
+ unsigned char mode;
+ unsigned char index;
+ unsigned char dev;
+ qid_t qid;
+ } dir_t;
+
+
+* Identifiers
+
+======================== =============================================
+SMC_OK 0
+SMC_UNK -1
+DEBUGFS_E_INVALID_PARAMS -2
+======================== =============================================
+
+======================== =============================================
+MOUNT 0
+CREATE 1
+OPEN 2
+CLOSE 3
+READ 4
+WRITE 5
+SEEK 6
+BIND 7
+STAT 8
+INIT 10
+VERSION 11
+======================== =============================================
+
+MOUNT
+~~~~~
+
+Description
+^^^^^^^^^^^
+This operation mounts a blob of data pointed to by path stored in `src`, at
+filesystem location pointed to by path stored in `where`, using driver pointed
+to by path in `spec`.
+
+Parameters
+^^^^^^^^^^
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``MOUNT``
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if mount operation failed
+=============== ==========================================================
+
+OPEN
+~~~~
+
+Description
+^^^^^^^^^^^
+This operation opens the file path pointed to by `fname`.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``OPEN``
+uint32_t mode
+======== ============================================================
+
+mode can be one of:
+
+.. code:: c
+
+ enum mode {
+ O_READ = 1 << 0,
+ O_WRITE = 1 << 1,
+ O_RDWR = 1 << 2,
+ O_BIND = 1 << 3,
+ O_DIR = 1 << 4,
+ O_STAT = 1 << 5
+ };
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if open operation failed
+
+uint32_t w1: file descriptor id on success.
+=============== ==========================================================
+
+CLOSE
+~~~~~
+
+Description
+^^^^^^^^^^^
+
+This operation closes a file described by a file descriptor obtained by a
+previous call to OPEN.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``CLOSE``
+uint32_t File descriptor id returned by OPEN
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if close operation failed
+=============== ==========================================================
+
+READ
+~~~~
+
+Description
+^^^^^^^^^^^
+
+This operation reads a number of bytes from a file descriptor obtained by
+a previous call to OPEN.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``READ``
+uint32_t File descriptor id returned by OPEN
+uint32_t Number of bytes to read
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+On success, the read data is retrieved from the shared buffer after the
+operation.
+
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if read operation failed
+
+uint32_t w1: number of bytes read on success.
+=============== ==========================================================
+
+SEEK
+~~~~
+
+Description
+^^^^^^^^^^^
+
+Move file pointer for file described by given `file descriptor` of given
+`offset` related to `whence`.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``SEEK``
+uint32_t File descriptor id returned by OPEN
+sint32_t offset in the file relative to whence
+uint32_t whence
+======== ============================================================
+
+whence can be one of:
+
+========= ============================================================
+KSEEK_SET 0
+KSEEK_CUR 1
+KSEEK_END 2
+========= ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if seek operation failed
+=============== ==========================================================
+
+BIND
+~~~~
+
+Description
+^^^^^^^^^^^
+
+Create a link from `oldpath` to `newpath`.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``BIND``
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if bind operation failed
+=============== ==========================================================
+
+STAT
+~~~~
+
+Description
+^^^^^^^^^^^
+
+Perform a stat operation on provided file `name` and returns the directory
+entry statistics into `dir`.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``STAT``
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if stat operation failed
+=============== ==========================================================
+
+INIT
+~~~~
+
+Description
+^^^^^^^^^^^
+Initial call to setup the shared exchange buffer. Notice if successful once,
+subsequent calls fail after a first initialization. The caller maps the same
+page frame in its virtual space and uses this buffer to exchange string
+parameters with filesystem primitives.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``INIT``
+uint64_t Physical address of the shared buffer.
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ======================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if already initialized,
+ or internal error occurred.
+=============== ======================================================
+
+VERSION
+~~~~~~~
+
+Description
+^^^^^^^^^^^
+Returns the debugfs interface version if implemented in TF-A.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``VERSION``
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ======================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == SMC_UNK if interface is not implemented
+
+uint32_t w1: On success, debugfs interface version, 32 bits
+ value with major version number in upper 16 bits and
+ minor version in lower 16 bits.
+=============== ======================================================
+
+* CREATE(1) and WRITE (5) command identifiers are unimplemented and
+ return `SMC_UNK`.
+
+--------------
+
+*Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/components/ven-el3-service.rst b/docs/components/ven-el3-service.rst
new file mode 100644
index 0000000..13449ba
--- /dev/null
+++ b/docs/components/ven-el3-service.rst
@@ -0,0 +1,78 @@
+Vendor Specific EL3 Monitor Service Calls
+=========================================
+
+This document enumerates and describes the Vendor Specific EL3 Monitor Service
+Calls.
+
+These are Service Calls defined by the vendor of the EL3 Monitor.
+They are accessed via ``SMC`` ("SMC calls") instruction executed from Exception
+Levels below EL3. SMC calls for Vendor Specific EL3 Monitor Services:
+
+- Follow `SMC Calling Convention`_;
+- Use SMC function IDs that fall in the vendor-specific EL3 range, which are
+
++---------------------------+--------------------------------------------------+
+| SMC Function Identifier | Service Type |
++===========================+==================================================+
+| 0x87000000 - 0x8700FFFF | SMC32: Vendor Specific EL3 Monitor Service Calls |
++---------------------------+--------------------------------------------------+
+| 0xC7000000 - 0xC700FFFF | SMC64: Vendor Specific EL3 Monitor Service Calls |
++---------------------------+--------------------------------------------------+
+
+Vendor-specific EL3 monitor services are as follows:
+
++-----------------------------------+-----------------------+---------------------------------------------+
+| SMC Function Identifier | Service Type | FID's Usage |
++===================================+=======================+=============================================+
+| 0x87000010 - 0x8700001F (SMC32) | DebugFS Interface | | 0 - 11 are in use. |
++-----------------------------------+ | | 12 - 15 are reserved for future expansion.|
+| 0xC7000010 - 0xC700001F (SMC64) | | |
++-----------------------------------+-----------------------+---------------------------------------------+
+| 0x87000020 - 0x8700002F (SMC32) | Performance | | 0,1 is in use. |
++-----------------------------------+ Measurement Framework | | 2 - 15 are reserved for future expansion. |
+| 0xC7000020 - 0xC700002F (SMC64) | (PMF) | |
++-----------------------------------+-----------------------+---------------------------------------------+
+| 0x87000030 - 0x8700FFFF (SMC32) | Reserved | | reserved for future expansion |
++-----------------------------------+ | |
+| 0xC7000030 - 0xC700FFFF (SMC64) | | |
++-----------------------------------+-----------------------+---------------------------------------------+
+
+Source definitions for vendor-specific EL3 Monitor Service Calls used by TF-A are located in
+the ``ven_el3_svc.h`` header file.
+
++----------------------------+----------------------------+--------------------------------+
+| VEN_EL3_SVC_VERSION_MAJOR | VEN_EL3_SVC_VERSION_MINOR | Changes |
++============================+============================+================================+
+| 1 | 0 | Added Debugfs and PMF services.|
++----------------------------+----------------------------+--------------------------------+
+
+*Table 1: Showing different versions of Vendor-specific service and changes done with each version*
+
+Each sub service will have its own version, one FID allocated for sub service version.
+
+Some ground rules when one should update top level version.
+ - VEN_EL3_SVC_VERSION_MAJOR is incremented when any of the sub service version discovery
+ FID changes or the FID that was allocated for discovery changes. So any breaking subfeature
+ discovery changes will lead to major version update.
+ - VEN_EL3_SVC_VERSION_MINOR is incremented when we add a new FID or a new sub service.
+ For example adding an new monitor service at 0x30, Debugfs starts at 0x10 and PMF
+ starts at 0x20 next one will start at 0x30, this will need a update to minor version.
+
+Performance Measurement Framework (PMF)
+---------------------------------------
+
+The :ref:`Performance Measurement Framework <firmware_design_pmf>`
+allows callers to retrieve timestamps captured at various paths in TF-A
+execution.
+
+DebugFS interface
+-----------------
+
+The optional DebugFS interface is accessed through Vendor specific EL3 service. Refer
+to :ref:`DebugFS interface` documentation for further details and usage.
+
+--------------
+
+*Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.*
+
+.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
diff --git a/docs/getting_started/rt-svc-writers-guide.rst b/docs/getting_started/rt-svc-writers-guide.rst
index fe64558..4d4ec22 100644
--- a/docs/getting_started/rt-svc-writers-guide.rst
+++ b/docs/getting_started/rt-svc-writers-guide.rst
@@ -49,8 +49,11 @@
Fast 1 CPU Service calls
Fast 2 SiP Service calls
Fast 3 OEM Service calls
- Fast 4 Standard Service calls
- Fast 5-47 Reserved for future use
+ Fast 4 Standard Secure Service calls
+ Fast 5 Standard Hypervisor Service Calls
+ Fast 6 Vendor Specific Hypervisor Service Calls
+ Fast 7 Vendor Specific EL3 Monitor Calls
+ Fast 8-47 Reserved for future use
Fast 48-49 Trusted Application calls
Fast 50-63 Trusted OS calls
@@ -312,9 +315,17 @@
the BL31 support for these services. Or a reference to the document that will
provide this information....
+Additional References:
+----------------------
+
+#. :ref:`ARM SiP Services <arm sip services>`
+#. :ref:`Vendor Specific EL3 Monitor Service Calls`
+
--------------
-*Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.*
.. _SMCCC: https://developer.arm.com/docs/den0028/latest
.. _PSCI: https://developer.arm.com/documentation/den0022/latest/
+.. _ARM SiP Services: arm-sip-service.rst
+.. _Vendor Specific EL3 Monitor Service Calls: ven-el3-service.rst
diff --git a/drivers/arm/smmu/smmu_v3.c b/drivers/arm/smmu/smmu_v3.c
index 6932e61..ef04c4d 100644
--- a/drivers/arm/smmu/smmu_v3.c
+++ b/drivers/arm/smmu/smmu_v3.c
@@ -97,7 +97,7 @@
#if ENABLE_RME
- if (get_armv9_2_feat_rme_support() != 0U) {
+ if (is_feat_rme_present()) {
if ((mmio_read_32(smmu_base + SMMU_ROOT_IDR0) &
SMMU_ROOT_IDR0_ROOT_IMPL) == 0U) {
WARN("Skip SMMU GPC configuration.\n");
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index 7e759d81..73b2d76 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -111,18 +111,18 @@
#define ID_DFR0_PERFMON_PMUV3P5 U(6)
#define ID_DFR0_COPTRC_SHIFT U(12)
#define ID_DFR0_COPTRC_MASK U(0xf)
-#define ID_DFR0_COPTRC_SUPPORTED U(1)
+#define COPTRC_IMPLEMENTED U(1)
#define ID_DFR0_COPTRC_LENGTH U(4)
#define ID_DFR0_TRACEFILT_SHIFT U(28)
#define ID_DFR0_TRACEFILT_MASK U(0xf)
-#define ID_DFR0_TRACEFILT_SUPPORTED U(1)
+#define TRACEFILT_IMPLEMENTED U(1)
#define ID_DFR0_TRACEFILT_LENGTH U(4)
/* ID_DFR1_EL1 definitions */
#define ID_DFR1_MTPMU_SHIFT U(0)
#define ID_DFR1_MTPMU_MASK U(0xf)
-#define ID_DFR1_MTPMU_SUPPORTED U(1)
-#define ID_DFR1_MTPMU_DISABLED U(15)
+#define MTPMU_IMPLEMENTED U(1)
+#define MTPMU_NOT_IMPLEMENTED U(15)
/* ID_MMFR3 definitions */
#define ID_MMFR3_PAN_SHIFT U(16)
@@ -141,14 +141,13 @@
#define ID_PFR0_AMU_SHIFT U(20)
#define ID_PFR0_AMU_LENGTH U(4)
#define ID_PFR0_AMU_MASK U(0xf)
-#define ID_PFR0_AMU_NOT_SUPPORTED U(0x0)
#define ID_PFR0_AMU_V1 U(0x1)
#define ID_PFR0_AMU_V1P1 U(0x2)
#define ID_PFR0_DIT_SHIFT U(24)
#define ID_PFR0_DIT_LENGTH U(4)
#define ID_PFR0_DIT_MASK U(0xf)
-#define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT)
+#define DIT_IMPLEMENTED (U(1) << ID_PFR0_DIT_SHIFT)
/* ID_PFR1 definitions */
#define ID_PFR1_VIRTEXT_SHIFT U(12)
@@ -166,7 +165,7 @@
/* ID_PFR2 definitions */
#define ID_PFR2_SSBS_SHIFT U(4)
#define ID_PFR2_SSBS_MASK U(0xf)
-#define SSBS_UNAVAILABLE U(0)
+#define SSBS_NOT_IMPLEMENTED U(0)
/* SCTLR definitions */
#define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h
index b52e4d0..8e39529 100644
--- a/include/arch/aarch32/arch_features.h
+++ b/include/arch/aarch32/arch_features.h
@@ -12,132 +12,112 @@
#include <arch_helpers.h>
#include <common/feat_detect.h>
-#define ISOLATE_FIELD(reg, feat) \
- ((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK)))
+#define ISOLATE_FIELD(reg, feat, mask) \
+ ((unsigned int)(((reg) >> (feat)) & mask))
-static inline bool is_armv7_gentimer_present(void)
-{
- return ISOLATE_FIELD(read_id_pfr1(), ID_PFR1_GENTIMER) != 0U;
-}
-
-static inline bool is_armv8_2_ttcnp_present(void)
-{
- return ISOLATE_FIELD(read_id_mmfr4(), ID_MMFR4_CNP) != 0U;
-}
-
-static unsigned int read_feat_amu_id_field(void)
-{
- return ISOLATE_FIELD(read_id_pfr0(), ID_PFR0_AMU);
-}
-
-static inline bool is_feat_amu_supported(void)
-{
- if (ENABLE_FEAT_AMU == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_AMU == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_amu_id_field() >= ID_PFR0_AMU_V1;
+#define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \
+static inline bool is_ ## name ## _supported(void) \
+{ \
+ if ((guard) == FEAT_STATE_DISABLED) { \
+ return false; \
+ } \
+ if ((guard) == FEAT_STATE_ALWAYS) { \
+ return true; \
+ } \
+ return read_func(); \
}
-static inline bool is_feat_amuv1p1_supported(void)
-{
- if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_amu_id_field() >= ID_PFR0_AMU_V1P1;
+#define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
+static inline bool is_ ## name ## _present(void) \
+{ \
+ return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
+ ? true : false; \
}
-static inline unsigned int read_feat_trf_id_field(void)
-{
- return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_TRACEFILT);
-}
-
-static inline bool is_feat_trf_supported(void)
-{
- if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
+#define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \
+CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
+CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard)
- if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
- return read_feat_trf_id_field() != 0U;
-}
-
-static inline unsigned int read_feat_coptrc_id_field(void)
-{
- return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_COPTRC);
-}
+/*
+ * +----------------------------+
+ * | Features supported |
+ * +----------------------------+
+ * | GENTIMER |
+ * +----------------------------+
+ * | FEAT_TTCNP |
+ * +----------------------------+
+ * | FEAT_AMU |
+ * +----------------------------+
+ * | FEAT_AMUV1P1 |
+ * +----------------------------+
+ * | FEAT_TRF |
+ * +----------------------------+
+ * | FEAT_SYS_REG_TRACE |
+ * +----------------------------+
+ * | FEAT_DIT |
+ * +----------------------------+
+ * | FEAT_PAN |
+ * +----------------------------+
+ * | FEAT_SSBS |
+ * +----------------------------+
+ * | FEAT_PMUV3 |
+ * +----------------------------+
+ * | FEAT_MTPMU |
+ * +----------------------------+
+ */
-static inline bool is_feat_sys_reg_trace_supported(void)
+/* GENTIMER */
+static inline bool is_armv7_gentimer_present(void)
{
- if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_coptrc_id_field() != 0U;
+ return ISOLATE_FIELD(read_id_pfr1(), ID_PFR1_GENTIMER_SHIFT,
+ ID_PFR1_GENTIMER_MASK) != 0U;
}
-static inline unsigned int read_feat_dit_id_field(void)
-{
- return ISOLATE_FIELD(read_id_pfr0(), ID_PFR0_DIT);
-}
+/* FEAT_TTCNP: Translation table common not private */
+CREATE_FEATURE_PRESENT(feat_ttcnp, id_mmfr4, ID_MMFR4_CNP_SHIFT,
+ ID_MMFR4_CNP_MASK, 1U)
-static inline bool is_feat_dit_supported(void)
-{
- if (ENABLE_FEAT_DIT == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_AMU: Activity Monitors Extension */
+CREATE_FEATURE_FUNCS(feat_amu, id_pfr0, ID_PFR0_AMU_SHIFT,
+ ID_PFR0_AMU_MASK, ID_PFR0_AMU_V1, ENABLE_FEAT_AMU)
- if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_AMUV1P1: AMU Extension v1.1 */
+CREATE_FEATURE_FUNCS(feat_amuv1p1, id_pfr0, ID_PFR0_AMU_SHIFT,
+ ID_PFR0_AMU_MASK, ID_PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
- return read_feat_dit_id_field() != 0U;
-}
+/* FEAT_TRF: Tracefilter */
+CREATE_FEATURE_FUNCS(feat_trf, id_dfr0, ID_DFR0_TRACEFILT_SHIFT,
+ ID_DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS)
-static inline unsigned int read_feat_pan_id_field(void)
-{
- return ISOLATE_FIELD(read_id_mmfr3(), ID_MMFR3_PAN);
-}
+/* FEAT_SYS_REG_TRACE */
+CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_dfr0, ID_DFR0_COPTRC_SHIFT,
+ ID_DFR0_COPTRC_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS)
-static inline bool is_feat_pan_supported(void)
-{
- if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_DIT: Data independent timing */
+CREATE_FEATURE_FUNCS(feat_dit, id_pfr0, ID_PFR0_DIT_SHIFT,
+ ID_PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT)
- if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_PAN: Privileged access never */
+CREATE_FEATURE_FUNCS(feat_pan, id_mmfr3, ID_MMFR3_PAN_SHIFT,
+ ID_MMFR3_PAN_MASK, 1U, ENABLE_FEAT_PAN)
- return read_feat_pan_id_field() != 0U;
-}
+/* FEAT_SSBS: Speculative store bypass safe */
+CREATE_FEATURE_PRESENT(feat_ssbs, id_pfr2, ID_PFR2_SSBS_SHIFT,
+ ID_PFR2_SSBS_MASK, 1U)
-static inline bool is_feat_pan_present(void)
-{
- return read_feat_pan_id_field() != 0U;
-}
+/* FEAT_PMUV3 */
+CREATE_FEATURE_PRESENT(feat_pmuv3, id_dfr0, ID_DFR0_PERFMON_SHIFT,
+ ID_DFR0_PERFMON_MASK, 3U)
-static inline unsigned int is_feat_ssbs_present(void)
+/* FEAT_MTPMU */
+static inline bool is_feat_mtpmu_present(void)
{
- return ((read_id_pfr2() >> ID_PFR2_SSBS_SHIFT) &
- ID_PFR2_SSBS_MASK) != SSBS_UNAVAILABLE;
+ unsigned int mtpmu = ISOLATE_FIELD(read_id_dfr1(), ID_DFR1_MTPMU_SHIFT,
+ ID_DFR1_MTPMU_MASK);
+ return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED);
}
+CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
/*
* TWED, ECV, CSV2, RAS are only used by the AArch64 EL2 context switch
@@ -179,29 +159,4 @@
static inline bool is_feat_ebep_present(void) { return false; }
static inline bool is_feat_sebep_present(void) { return false; }
-static inline unsigned int read_feat_pmuv3_id_field(void)
-{
- return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_PERFMON);
-}
-
-static inline unsigned int read_feat_mtpmu_id_field(void)
-{
- return ISOLATE_FIELD(read_id_dfr1(), ID_DFR1_MTPMU);
-}
-
-static inline bool is_feat_mtpmu_supported(void)
-{
- if (DISABLE_MTPMU == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- unsigned int mtpmu = read_feat_mtpmu_id_field();
-
- return mtpmu != 0U && mtpmu != ID_DFR1_MTPMU_DISABLED;
-}
-
#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch32/asm_macros.S b/include/arch/aarch32/asm_macros.S
index 3ba86e9..bccd2a7 100644
--- a/include/arch/aarch32/asm_macros.S
+++ b/include/arch/aarch32/asm_macros.S
@@ -241,4 +241,13 @@
cmp \temp, \bot
bhs div2
.endm
+
+ /*
+ * Helper macro to instruction adr <reg>, <symbol> where <symbol> is
+ * within the range +/- 4 GB.
+ */
+ .macro adr_l, dst, sym
+ adrp \dst, \sym
+ add \dst, \dst, :lo12:\sym
+ .endm
#endif /* ASM_MACROS_S */
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S
index 697eb82..41eeabb 100644
--- a/include/arch/aarch32/el3_common_macros.S
+++ b/include/arch/aarch32/el3_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -76,7 +76,7 @@
orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS)
ldcopr r1, ID_DFR0
ubfx r1, r1, #ID_DFR0_COPTRC_SHIFT, #ID_DFR0_COPTRC_LENGTH
- cmp r1, #ID_DFR0_COPTRC_SUPPORTED
+ cmp r1, #COPTRC_IMPLEMENTED
bne 1f
orr r0, r0, #NSTRCDIS_BIT
1:
@@ -143,7 +143,7 @@
SDCR_SCCD_BIT) & ~SDCR_TTRF_BIT)
ldcopr r1, ID_DFR0
ubfx r1, r1, #ID_DFR0_TRACEFILT_SHIFT, #ID_DFR0_TRACEFILT_LENGTH
- cmp r1, #ID_DFR0_TRACEFILT_SUPPORTED
+ cmp r1, #TRACEFILT_IMPLEMENTED
bne 1f
orr r0, r0, #SDCR_TTRF_BIT
1:
@@ -182,7 +182,7 @@
*/
ldcopr r0, ID_PFR0
and r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT)
- cmp r0, #ID_PFR0_DIT_SUPPORTED
+ cmp r0, #DIT_IMPLEMENTED
bne 1f
mrs r0, cpsr
orr r0, r0, #CPSR_DIT_BIT
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 5508ebb..ea9aa51 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -179,7 +179,6 @@
#define ID_AA64PFR0_AMU_SHIFT U(44)
#define ID_AA64PFR0_AMU_MASK ULL(0xf)
-#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0)
#define ID_AA64PFR0_AMU_V1 ULL(0x1)
#define ID_AA64PFR0_AMU_V1P1 U(0x2)
@@ -191,8 +190,8 @@
#define ID_AA64PFR0_SVE_SHIFT U(32)
#define ID_AA64PFR0_SVE_MASK ULL(0xf)
-#define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1)
#define ID_AA64PFR0_SVE_LENGTH U(4)
+#define SVE_IMPLEMENTED ULL(0x1)
#define ID_AA64PFR0_SEL2_SHIFT U(36)
#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
@@ -203,23 +202,21 @@
#define ID_AA64PFR0_DIT_SHIFT U(48)
#define ID_AA64PFR0_DIT_MASK ULL(0xf)
#define ID_AA64PFR0_DIT_LENGTH U(4)
-#define ID_AA64PFR0_DIT_SUPPORTED U(1)
+#define DIT_IMPLEMENTED ULL(1)
#define ID_AA64PFR0_CSV2_SHIFT U(56)
#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
#define ID_AA64PFR0_CSV2_LENGTH U(4)
-#define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2)
-#define ID_AA64PFR0_CSV2_3_SUPPORTED ULL(0x3)
+#define CSV2_2_IMPLEMENTED ULL(0x2)
+#define CSV2_3_IMPLEMENTED ULL(0x3)
#define ID_AA64PFR0_FEAT_RME_SHIFT U(52)
#define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf)
#define ID_AA64PFR0_FEAT_RME_LENGTH U(4)
-#define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0)
-#define ID_AA64PFR0_FEAT_RME_V1 U(1)
+#define RME_NOT_IMPLEMENTED ULL(0)
#define ID_AA64PFR0_RAS_SHIFT U(28)
#define ID_AA64PFR0_RAS_MASK ULL(0xf)
-#define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0)
#define ID_AA64PFR0_RAS_LENGTH U(4)
/* Exception level handling */
@@ -230,12 +227,13 @@
/* ID_AA64DFR0_EL1.TraceVer definitions */
#define ID_AA64DFR0_TRACEVER_SHIFT U(4)
#define ID_AA64DFR0_TRACEVER_MASK ULL(0xf)
-#define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1)
#define ID_AA64DFR0_TRACEVER_LENGTH U(4)
+
#define ID_AA64DFR0_TRACEFILT_SHIFT U(40)
#define ID_AA64DFR0_TRACEFILT_MASK U(0xf)
-#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1)
#define ID_AA64DFR0_TRACEFILT_LENGTH U(4)
+#define TRACEFILT_IMPLEMENTED ULL(1)
+
#define ID_AA64DFR0_PMUVER_LENGTH U(4)
#define ID_AA64DFR0_PMUVER_SHIFT U(8)
#define ID_AA64DFR0_PMUVER_MASK U(0xf)
@@ -251,24 +249,24 @@
/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
#define ID_AA64DFR0_PMS_SHIFT U(32)
#define ID_AA64DFR0_PMS_MASK ULL(0xf)
-#define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1)
-#define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0)
+#define SPE_IMPLEMENTED ULL(0x1)
+#define SPE_NOT_IMPLEMENTED ULL(0x0)
/* ID_AA64DFR0_EL1.TraceBuffer definitions */
#define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44)
#define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf)
-#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1)
+#define TRACEBUFFER_IMPLEMENTED ULL(1)
/* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */
#define ID_AA64DFR0_MTPMU_SHIFT U(48)
#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
-#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
-#define ID_AA64DFR0_MTPMU_DISABLED ULL(15)
+#define MTPMU_IMPLEMENTED ULL(1)
+#define MTPMU_NOT_IMPLEMENTED ULL(15)
/* ID_AA64DFR0_EL1.BRBE definitions */
#define ID_AA64DFR0_BRBE_SHIFT U(52)
#define ID_AA64DFR0_BRBE_MASK ULL(0xf)
-#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1)
+#define BRBE_IMPLEMENTED ULL(1)
/* ID_AA64DFR1_EL1 definitions */
#define ID_AA64DFR1_EBEP_SHIFT U(48)
@@ -294,8 +292,8 @@
#define ID_AA64ISAR1_SB_SHIFT U(36)
#define ID_AA64ISAR1_SB_MASK ULL(0xf)
-#define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1)
-#define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0)
+#define SB_IMPLEMENTED ULL(0x1)
+#define SB_NOT_IMPLEMENTED ULL(0x0)
/* ID_AA64ISAR2_EL1 definitions */
#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
@@ -323,52 +321,41 @@
#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
-#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
+#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
+#define ECV_IMPLEMENTED ULL(0x1)
#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
-#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
+#define FGT_IMPLEMENTED ULL(0x1)
+#define FGT_NOT_IMPLEMENTED ULL(0x0)
#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
-#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
-#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
-#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2)
+#define TGRAN16_IMPLEMENTED ULL(0x1)
/* ID_AA64MMFR1_EL1 definitions */
#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
-#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
+#define TWED_IMPLEMENTED ULL(0x1)
#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
-#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
-#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
+#define PAN_IMPLEMENTED ULL(0x1)
+#define PAN2_IMPLEMENTED ULL(0x2)
+#define PAN3_IMPLEMENTED ULL(0x3)
#define ID_AA64MMFR1_EL1_VHE_SHIFT U(8)
#define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf)
#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40)
#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
-#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0)
+#define HCX_IMPLEMENTED ULL(0x1)
/* ID_AA64MMFR2_EL1 definitions */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
@@ -388,9 +375,7 @@
#define ID_AA64MMFR2_EL1_NV_SHIFT U(24)
#define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf)
-#define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2)
+#define NV2_IMPLEMENTED ULL(0x2)
/* ID_AA64MMFR3_EL1 definitions */
#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3
@@ -414,11 +399,11 @@
#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
-#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
+#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
-#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
+#define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */
#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
@@ -434,8 +419,7 @@
#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
#define GCS_IMPLEMENTED ULL(1)
-#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
-#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
+#define RNG_TRAP_IMPLEMENTED ULL(0x1)
/* ID_AA64PFR2_EL1 definitions */
#define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0)
@@ -468,9 +452,9 @@
#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
#define ID_AA64PFR1_EL1_SME_WIDTH U(4)
-#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0)
-#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
-#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2)
+#define SME_IMPLEMENTED ULL(0x1)
+#define SME2_IMPLEMENTED ULL(0x2)
+#define SME_NOT_IMPLEMENTED ULL(0x0)
/* ID_PFR1_EL1 definitions */
#define ID_PFR1_VIRTEXT_SHIFT U(12)
@@ -1102,11 +1086,11 @@
/* ID_AA64SMFR0_EL1 definitions */
#define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63)
#define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1)
-#define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1)
+#define SME_FA64_IMPLEMENTED U(0x1)
#define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55)
#define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf)
-#define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0)
-#define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1)
+#define SME_INST_IMPLEMENTED ULL(0x0)
+#define SME2_INST_IMPLEMENTED ULL(0x1)
/* SMCR_ELx definitions */
#define SMCR_ELX_LEN_SHIFT U(0)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 7582fc6..ddc1c80 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -12,27 +12,125 @@
#include <arch_helpers.h>
#include <common/feat_detect.h>
-#define ISOLATE_FIELD(reg, feat) \
- ((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK))
+#define ISOLATE_FIELD(reg, feat, mask) \
+ ((unsigned int)(((reg) >> (feat)) & mask))
-#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \
-static inline bool is_ ## name ## _supported(void) \
-{ \
- if ((guard) == FEAT_STATE_DISABLED) { \
- return false; \
- } \
- if ((guard) == FEAT_STATE_ALWAYS) { \
- return true; \
- } \
- return read_func() >= (idvalue); \
+#define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \
+static inline bool is_ ## name ## _supported(void) \
+{ \
+ if ((guard) == FEAT_STATE_DISABLED) { \
+ return false; \
+ } \
+ if ((guard) == FEAT_STATE_ALWAYS) { \
+ return true; \
+ } \
+ return read_func(); \
}
-#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \
-static unsigned int read_ ## name ## _id_field(void) \
-{ \
- return ISOLATE_FIELD(read_ ## idreg(), idfield); \
-} \
-CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard)
+#define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
+static inline bool is_ ## name ## _present(void) \
+{ \
+ return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
+ ? true : false; \
+}
+
+#define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \
+CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
+CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard)
+
+
+/* +----------------------------+
+ * | Features supported |
+ * +----------------------------+
+ * | GENTIMER |
+ * +----------------------------+
+ * | FEAT_PAN |
+ * +----------------------------+
+ * | FEAT_VHE |
+ * +----------------------------+
+ * | FEAT_TTCNP |
+ * +----------------------------+
+ * | FEAT_UAO |
+ * +----------------------------+
+ * | FEAT_PACQARMA3 |
+ * +----------------------------+
+ * | FEAT_PAUTH |
+ * +----------------------------+
+ * | FEAT_TTST |
+ * +----------------------------+
+ * | FEAT_BTI |
+ * +----------------------------+
+ * | FEAT_MTE2 |
+ * +----------------------------+
+ * | FEAT_SSBS |
+ * +----------------------------+
+ * | FEAT_NMI |
+ * +----------------------------+
+ * | FEAT_GCS |
+ * +----------------------------+
+ * | FEAT_EBEP |
+ * +----------------------------+
+ * | FEAT_SEBEP |
+ * +----------------------------+
+ * | FEAT_SEL2 |
+ * +----------------------------+
+ * | FEAT_TWED |
+ * +----------------------------+
+ * | FEAT_FGT |
+ * +----------------------------+
+ * | FEAT_EC/ECV2 |
+ * +----------------------------+
+ * | FEAT_RNG |
+ * +----------------------------+
+ * | FEAT_TCR2 |
+ * +----------------------------+
+ * | FEAT_S2POE |
+ * +----------------------------+
+ * | FEAT_S1POE |
+ * +----------------------------+
+ * | FEAT_S2PIE |
+ * +----------------------------+
+ * | FEAT_S1PIE |
+ * +----------------------------+
+ * | FEAT_AMU/AMUV1P1 |
+ * +----------------------------+
+ * | FEAT_MPAM |
+ * +----------------------------+
+ * | FEAT_HCX |
+ * +----------------------------+
+ * | FEAT_RNG_TRAP |
+ * +----------------------------+
+ * | FEAT_RME |
+ * +----------------------------+
+ * | FEAT_SB |
+ * +----------------------------+
+ * | FEAT_CSV2/CSV3 |
+ * +----------------------------+
+ * | FEAT_SPE |
+ * +----------------------------+
+ * | FEAT_SVE |
+ * +----------------------------+
+ * | FEAT_RAS |
+ * +----------------------------+
+ * | FEAT_DIT |
+ * +----------------------------+
+ * | FEAT_SYS_REG_TRACE |
+ * +----------------------------+
+ * | FEAT_TRF |
+ * +----------------------------+
+ * | FEAT_NV/NV2 |
+ * +----------------------------+
+ * | FEAT_BRBE |
+ * +----------------------------+
+ * | FEAT_TRBE |
+ * +----------------------------+
+ * | FEAT_SME/SME2 |
+ * +----------------------------+
+ * | FEAT_PMUV3 |
+ * +----------------------------+
+ * | FEAT_MTPMU |
+ * +----------------------------+
+ */
static inline bool is_armv7_gentimer_present(void)
{
@@ -40,38 +138,28 @@
return true;
}
+/* FEAT_PAN: Privileged access never */
CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
- ENABLE_FEAT_PAN)
-static inline bool is_feat_pan_present(void)
-{
- return read_feat_pan_id_field() != 0U;
-}
+ ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN)
+/* FEAT_VHE: Virtualization Host Extensions */
CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
- ENABLE_FEAT_VHE)
+ ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE)
-static inline bool is_armv8_2_ttcnp_present(void)
-{
- return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
- ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
-}
+/* FEAT_TTCNP: Translation table common not private */
+CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT,
+ ID_AA64MMFR2_EL1_CNP_MASK, 1U)
-static inline bool is_feat_uao_present(void)
-{
- return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_UAO_SHIFT) &
- ID_AA64MMFR2_EL1_UAO_MASK) != 0U;
-}
-
-static inline bool is_feat_pacqarma3_present(void)
-{
- uint64_t mask_id_aa64isar2 =
- (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
- (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT);
+/* FEAT_UAO: User access override */
+CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT,
+ ID_AA64MMFR2_EL1_UAO_MASK, 1U)
- /* If any of the fields is not zero, QARMA3 algorithm is present */
- return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U;
-}
+/* If any of the fields is not zero, QARMA3 algorithm is present */
+CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0,
+ ((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
+ (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U)
+/* PAUTH */
static inline bool is_armv8_3_pauth_present(void)
{
uint64_t mask_id_aa64isar1 =
@@ -88,89 +176,81 @@
is_feat_pacqarma3_present());
}
-static inline bool is_armv8_4_ttst_present(void)
-{
- return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
- ID_AA64MMFR2_EL1_ST_MASK) == 1U;
-}
+/* FEAT_TTST: Small translation tables */
+CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT,
+ ID_AA64MMFR2_EL1_ST_MASK, 1U)
-static inline bool is_armv8_5_bti_present(void)
-{
- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) &
- ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
-}
-
-static inline unsigned int get_armv8_5_mte_support(void)
-{
- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
- ID_AA64PFR1_EL1_MTE_MASK);
-}
-static inline unsigned int is_feat_mte2_present(void)
-{
- return get_armv8_5_mte_support() >= MTE_IMPLEMENTED_ELX;
-}
+/* FEAT_BTI: Branch target identification */
+CREATE_FEATURE_PRESENT(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT,
+ ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED)
-static inline bool is_feat_ssbs_present(void)
-{
- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
- ID_AA64PFR1_EL1_SSBS_MASK) != SSBS_UNAVAILABLE;
-}
+/* FEAT_MTE2: Memory tagging extension */
+CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
+ ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2)
-static inline bool is_feat_nmi_present(void)
-{
- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_NMI_SHIFT) &
- ID_AA64PFR1_EL1_NMI_MASK) == NMI_IMPLEMENTED;
-}
+/* FEAT_SSBS: Speculative store bypass safe */
+CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT,
+ ID_AA64PFR1_EL1_SSBS_MASK, 1U)
-static inline bool is_feat_gcs_present(void)
-{
- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_GCS_SHIFT) &
- ID_AA64PFR1_EL1_GCS_MASK) == GCS_IMPLEMENTED;
-}
+/* FEAT_NMI: Non-maskable interrupts */
+CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT,
+ ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED)
-static inline bool is_feat_ebep_present(void)
-{
- return ((read_id_aa64dfr1_el1() >> ID_AA64DFR1_EBEP_SHIFT) &
- ID_AA64DFR1_EBEP_MASK) == EBEP_IMPLEMENTED;
-}
+/* FEAT_EBEP */
+CREATE_FEATURE_PRESENT(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT,
+ ID_AA64DFR1_EBEP_MASK, EBEP_IMPLEMENTED)
-static inline bool is_feat_sebep_present(void)
-{
- return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_SEBEP_SHIFT) &
- ID_AA64DFR0_SEBEP_MASK) == SEBEP_IMPLEMENTED;
-}
+/* FEAT_SEBEP */
+CREATE_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT,
+ ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED)
-CREATE_FEATURE_FUNCS_VER(feat_mte2, get_armv8_5_mte_support, MTE_IMPLEMENTED_ELX,
- ENABLE_FEAT_MTE2)
+/* FEAT_SEL2: Secure EL2 */
CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
- ENABLE_FEAT_SEL2)
+ ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2)
+
+/* FEAT_TWED: Delayed trapping of WFE */
CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
- ENABLE_FEAT_TWED)
+ ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED)
+
+/* FEAT_FGT: Fine-grained traps */
CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
- ENABLE_FEAT_FGT)
+ ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT)
+
+/* FEAT_ECV: Enhanced Counter Virtualization */
CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
- ENABLE_FEAT_ECV)
-CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,
- ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
+ ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV)
+CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
+ ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
+/* FEAT_RNG: Random number generator */
CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
- ENABLE_FEAT_RNG)
+ ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG)
+
+/* FEAT_TCR2: Support TCR2_ELx regs */
CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
- ENABLE_FEAT_TCR2)
+ ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2)
+/* FEAT_S2POE */
CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
- ENABLE_FEAT_S2POE)
+ ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE)
+
+/* FEAT_S1POE */
CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
- ENABLE_FEAT_S1POE)
+ ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE)
+
static inline bool is_feat_sxpoe_supported(void)
{
return is_feat_s1poe_supported() || is_feat_s2poe_supported();
}
+/* FEAT_S2PIE */
CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
- ENABLE_FEAT_S2PIE)
+ ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE)
+
+/* FEAT_S1PIE */
CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
- ENABLE_FEAT_S1PIE)
+ ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE)
+
static inline bool is_feat_sxpie_supported(void)
{
return is_feat_s1pie_supported() || is_feat_s2pie_supported();
@@ -178,13 +258,15 @@
/* FEAT_GCS: Guarded Control Stack */
CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
- ENABLE_FEAT_GCS)
+ ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS)
/* FEAT_AMU: Activity Monitors Extension */
CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
- ENABLE_FEAT_AMU)
-CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
- ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
+ ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU)
+
+/* FEAT_AMUV1P1: AMU Extension v1.1 */
+CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
+ ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
/*
* Return MPAM version:
@@ -195,46 +277,32 @@
* 0x11: v1.1 Armv8.4 or later
*
*/
-static inline unsigned int read_feat_mpam_version(void)
+static inline bool is_feat_mpam_present(void)
{
- return (unsigned int)((((read_id_aa64pfr0_el1() >>
+ unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >>
ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
- ((read_id_aa64pfr1_el1() >>
- ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
+ ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT)
+ & ID_AA64PFR1_MPAM_FRAC_MASK));
+ return ret;
}
-CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U,
- ENABLE_FEAT_MPAM)
+CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM)
/* FEAT_HCX: Extended Hypervisor Configuration Register */
CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
- ENABLE_FEAT_HCX)
+ ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX)
-static inline bool is_feat_rng_trap_present(void)
-{
- return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) &
- ID_AA64PFR1_EL1_RNDR_TRAP_MASK)
- == ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED);
-}
+/* FEAT_RNG_TRAP: Trapping support */
+CREATE_FEATURE_PRESENT(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT,
+ ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED)
-static inline unsigned int get_armv9_2_feat_rme_support(void)
-{
- /*
- * Return the RME version, zero if not supported. This function can be
- * used as both an integer value for the RME version or compared to zero
- * to detect RME presence.
- */
- return (unsigned int)(read_id_aa64pfr0_el1() >>
- ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK;
-}
+/* Return the RME version, zero if not supported. */
+CREATE_FEATURE_FUNCS(feat_rme, id_aa64pfr0_el1, ID_AA64PFR0_FEAT_RME_SHIFT,
+ ID_AA64PFR0_FEAT_RME_MASK, 1U, ENABLE_RME)
-/*********************************************************************************
- * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction)
- ********************************************************************************/
-static inline unsigned int read_feat_sb_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT);
-}
+/* FEAT_SB: Speculation barrier instruction */
+CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT,
+ ID_AA64ISAR1_SB_MASK, 1U)
/*
* FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59]
@@ -248,109 +316,94 @@
* implemented.
* 0b0011 - Feature FEAT_CSV2_3 is implemented.
*/
-static inline unsigned int read_feat_csv2_id_field(void)
-{
- return (unsigned int)(read_id_aa64pfr0_el1() >>
- ID_AA64PFR0_CSV2_SHIFT) & ID_AA64PFR0_CSV2_MASK;
-}
-CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field,
- ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2)
-CREATE_FEATURE_FUNCS_VER(feat_csv2_3, read_feat_csv2_id_field,
- ID_AA64PFR0_CSV2_3_SUPPORTED, ENABLE_FEAT_CSV2_3)
+CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT,
+ ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2)
+CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT,
+ ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3)
/* FEAT_SPE: Statistical Profiling Extension */
CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
- ENABLE_SPE_FOR_NS)
+ ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS)
/* FEAT_SVE: Scalable Vector Extension */
CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
- ENABLE_SVE_FOR_NS)
+ ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS)
/* FEAT_RAS: Reliability, Accessibility, Serviceability */
-CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1,
- ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS)
+CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT,
+ ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS)
/* FEAT_DIT: Data Independent Timing instructions */
-CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1,
- ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT)
+CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT,
+ ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT)
-CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1,
- ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS)
+/* FEAT_SYS_REG_TRACE */
+CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, ID_AA64DFR0_TRACEVER_SHIFT,
+ ID_AA64DFR0_TRACEVER_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS)
/* FEAT_TRF: TraceFilter */
CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
- ENABLE_TRF_FOR_NS)
+ ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS)
/* FEAT_NV2: Enhanced Nested Virtualization */
-CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0)
-CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field,
- ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS)
+CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT,
+ ID_AA64MMFR2_EL1_NV_MASK, 1U, 0U)
+CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT,
+ ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS)
/* FEAT_BRBE: Branch Record Buffer Extension */
CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
- ENABLE_BRBE_FOR_NS)
+ ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS)
/* FEAT_TRBE: Trace Buffer Extension */
CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
- ENABLE_TRBE_FOR_NS)
+ ID_AA64DFR0_TRACEBUFFER_MASK, 1U, ENABLE_TRBE_FOR_NS)
-static inline unsigned int read_feat_sme_fa64_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64smfr0_el1(),
- ID_AA64SMFR0_EL1_SME_FA64_SHIFT);
-}
+/* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */
+CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT,
+ ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U)
+
/* FEAT_SMEx: Scalar Matrix Extension */
CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
- ENABLE_SME_FOR_NS)
-CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field,
- ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS)
+ ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS)
+
+CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
+ ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS)
/*******************************************************************************
* Function to get hardware granularity support
******************************************************************************/
-static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void)
+static inline bool is_feat_tgran4K_present(void)
{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
- ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
+ unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
+ ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK);
+ return (tgranx < 8U);
}
-static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
- ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
-}
+CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT,
+ ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED)
-static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void)
+static inline bool is_feat_tgran64K_present(void)
{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
- ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
+ unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
+ ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK);
+ return (tgranx < 8U);
}
-static inline unsigned int read_feat_pmuv3_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT);
-}
+/* FEAT_PMUV3 */
+CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT,
+ ID_AA64DFR0_PMUVER_MASK, 1U)
-static inline unsigned int read_feat_mtpmu_id_field(void)
+/* FEAT_MTPMU */
+static inline bool is_feat_mtpmu_present(void)
{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT);
+ unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
+ ID_AA64DFR0_MTPMU_MASK);
+ return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED);
}
-static inline bool is_feat_mtpmu_supported(void)
-{
- if (DISABLE_MTPMU == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- unsigned int mtpmu = read_feat_mtpmu_id_field();
-
- return (mtpmu != 0U) && (mtpmu != ID_AA64DFR0_MTPMU_DISABLED);
-}
+CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S
index d09ad0f..ec2acd5 100644
--- a/include/arch/aarch64/asm_macros.S
+++ b/include/arch/aarch64/asm_macros.S
@@ -317,4 +317,12 @@
#endif
.endm
+ /*
+ * Helper macro to instruction adr <reg>, <symbol> where <symbol> is
+ * within the range +/- 4 GB.
+ */
+ .macro adr_l, dst, sym
+ adrp \dst, \sym
+ add \dst, \dst, :lo12:\sym
+ .endm
#endif /* ASM_MACROS_S */
diff --git a/include/arch/aarch64/el2_common_macros.S b/include/arch/aarch64/el2_common_macros.S
index 9609c0d..9f82399 100644
--- a/include/arch/aarch64/el2_common_macros.S
+++ b/include/arch/aarch64/el2_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -157,7 +157,7 @@
*/
mrs x0, id_aa64pfr0_el1
ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
- cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
+ cmp x0, #DIT_IMPLEMENTED
bne 1f
mov x0, #DIT_BIT
msr DIT, x0
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 26c7578..1a3e9b6 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -133,7 +133,7 @@
#if ENABLE_FEAT_DIT > 1
cbz x0, 1f
#else
- cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
+ cmp x0, #DIT_IMPLEMENTED
ASM_ASSERT(eq)
#endif
diff --git a/include/lib/debugfs.h b/include/lib/debugfs.h
index 8ed237a..9415962 100644
--- a/include/lib/debugfs.h
+++ b/include/lib/debugfs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -61,12 +61,24 @@
/* Debugfs version returned through SMC interface */
#define DEBUGFS_VERSION (0x000000001U)
-/* Function ID for accessing the debugfs interface */
-#define DEBUGFS_FID_VALUE (0x30U)
+/* Function ID for accessing the debugfs interface from
+ * Vendor-Specific EL3 Range.
+ */
+#define DEBUGFS_FID_VALUE (0x10U)
#define is_debugfs_fid(_fid) \
(((_fid) & FUNCID_NUM_MASK) == DEBUGFS_FID_VALUE)
+
+/* Function ID for accessing the debugfs interface from arm sip.
+ * This is now deprecated FID and will be removed after 2.12 release.
+ */
+#define DEBUGFS_FID_VALUE_DEPRECATED (0x30U)
+
+#define is_debugfs_fid_deprecated(_fid) \
+ (((_fid) & FUNCID_NUM_MASK) == DEBUGFS_FID_VALUE_DEPRECATED)
+
+
/* Error code for debugfs SMC interface failures */
#define DEBUGFS_E_INVALID_PARAMS (-2)
#define DEBUGFS_E_DENIED (-3)
diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h
index 9d901e2..38841d9 100644
--- a/include/lib/pmf/pmf.h
+++ b/include/lib/pmf/pmf.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,19 +36,35 @@
#define PMF_NO_CACHE_MAINT U(0)
/*
- * Defines for PMF SMC function ids.
+ * Defines for PMF SMC function ids used with arm-sip
+ * range, this is now deprecated and will be removed.
*/
-#define PMF_SMC_GET_TIMESTAMP_32 U(0x82000010)
-#define PMF_SMC_GET_TIMESTAMP_64 U(0xC2000010)
+#define PMF_SMC_GET_TIMESTAMP_32_DEP U(0x82000010)
+#define PMF_SMC_GET_TIMESTAMP_64_DEP U(0xC2000010)
+
+#define PMF_FID_VALUE_DEPRECATED U(0x10)
+#define is_pmf_fid_deprecated(_fid) \
+ (((_fid) & FUNCID_NUM_MASK) == PMF_FID_VALUE_DEPRECATED)
+
+/*
+ * Defines for PMF SMC function ids used with Vendor-Specific
+ * EL3 range.
+ */
+#define PMF_SMC_GET_TIMESTAMP_32 U(0x87000020)
+#define PMF_SMC_GET_TIMESTAMP_64 U(0xC7000020)
#define PMF_NUM_SMC_CALLS 2
+#define PMF_SMC_GET_VERSION_32 U(0x87000021)
+#define PMF_SMC_GET_VERSION_64 U(0xC7000021)
+
+#define PMF_SMC_VERSION U(0x00000001)
+
/*
* The macros below are used to identify
* PMF calls from the SMC function ID.
*/
-#define PMF_FID_MASK U(0xffe0)
-#define PMF_FID_VALUE U(0)
-#define is_pmf_fid(_fid) (((_fid) & PMF_FID_MASK) == PMF_FID_VALUE)
+#define PMF_FID_VALUE U(0x20)
+#define is_pmf_fid(_fid) (((_fid) & FUNCID_NUM_MASK) == PMF_FID_VALUE)
/* Following are the supported PMF service IDs */
#define PMF_PSCI_STAT_SVC_ID 0
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index c493105..775c2b2 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,7 +20,7 @@
SMCCC_VERSION_MINOR_SHIFT))
#define SMCCC_MAJOR_VERSION U(1)
-#define SMCCC_MINOR_VERSION U(4)
+#define SMCCC_MINOR_VERSION U(5)
/*******************************************************************************
* Bit definitions inside the function id as per the SMC calling convention
@@ -95,6 +95,8 @@
#define OEN_STD_HYP_END U(5)
#define OEN_VEN_HYP_START U(6) /* Vendor Hypervisor Service calls */
#define OEN_VEN_HYP_END U(6)
+#define OEN_VEN_EL3_START U(7) /* Vendor Specific EL3 Monitor Calls */
+#define OEN_VEN_EL3_END U(7)
#define OEN_TAP_START U(48) /* Trusted Applications */
#define OEN_TAP_END U(49)
#define OEN_TOS_START U(50) /* Trusted OS */
diff --git a/include/plat/arm/common/arm_sip_svc.h b/include/plat/arm/common/arm_sip_svc.h
index a6fd42b..bca224d 100644
--- a/include/plat/arm/common/arm_sip_svc.h
+++ b/include/plat/arm/common/arm_sip_svc.h
@@ -16,12 +16,14 @@
/* U(0x8200ff02) is reserved */
#define ARM_SIP_SVC_VERSION U(0x8200ff03)
+/* Deprecated FID's Range and will be removed */
/* PMF_SMC_GET_TIMESTAMP_32 0x82000010 */
/* PMF_SMC_GET_TIMESTAMP_64 0xC2000010 */
/* Function ID for requesting state switch of lower EL */
#define ARM_SIP_SVC_EXE_STATE_SWITCH U(0x82000020)
+/* Deprecated FID's Range and will be removed */
/* DEBUGFS_SMC_32 0x82000030U */
/* DEBUGFS_SMC_64 0xC2000030U */
@@ -32,8 +34,8 @@
*/
/* ARM SiP Service Calls version numbers */
-#define ARM_SIP_SVC_VERSION_MAJOR U(0x0)
-#define ARM_SIP_SVC_VERSION_MINOR U(0x2)
+#define ARM_SIP_SVC_VERSION_MAJOR U(0x1)
+#define ARM_SIP_SVC_VERSION_MINOR U(0x0)
/*
* Arm SiP SMC calls that are primarily used for testing purposes.
diff --git a/include/services/ven_el3_svc.h b/include/services/ven_el3_svc.h
new file mode 100644
index 0000000..e030b68
--- /dev/null
+++ b/include/services/ven_el3_svc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef VEN_EL3_SVC_H
+#define VEN_EL3_SVC_H
+
+/*
+ * Function Identifier value ranges for Vendor-Specific
+ * EL3 Monitor Service Calls.
+ */
+/* VEN_EL3_SMC_32 0x87000000U */
+/* VEN_EL3_SMC_64 0xC7000000U */
+
+
+/* Function Identifier values of general queries */
+#define VEN_EL3_SVC_UID 0x8700ff01
+/* 0x8700ff02 is reserved */
+#define VEN_EL3_SVC_VERSION 0x8700ff03
+
+#define VEN_EL3_SVC_VERSION_MAJOR 1
+#define VEN_EL3_SVC_VERSION_MINOR 0
+
+/* DEBUGFS_SMC_32 0x87000010U */
+/* DEBUGFS_SMC_64 0xC7000010U */
+
+/* PMF_SMC_GET_TIMESTAMP_32 0x87000020U */
+/* PMF_SMC_GET_TIMESTAMP_64 0xC7000020U */
+
+#endif /* VEN_EL3_SVC_H */
diff --git a/lib/cpus/aarch64/cortex_gelas.S b/lib/cpus/aarch64/cortex_gelas.S
index dc704f2..8870019 100644
--- a/lib/cpus/aarch64/cortex_gelas.S
+++ b/lib/cpus/aarch64/cortex_gelas.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,7 +42,7 @@
mrs x0, ID_AA64PFR1_EL1
ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
#ID_AA64PFR1_EL1_SME_WIDTH
- cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED
+ cmp x0, #SME_NOT_IMPLEMENTED
b.eq 1f
msr CORTEX_GELAS_SVCRSM, xzr
msr CORTEX_GELAS_SVCRZA, xzr
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index 1ae3180..3aa4f15 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -165,13 +165,13 @@
and w2, w2, w3
/* Get the cpu_ops end location */
- adr x5, (__CPU_OPS_END__ + CPU_MIDR)
+ adr_l x5, (__CPU_OPS_END__ + CPU_MIDR)
/* Initialize the return parameter */
mov x0, #0
1:
/* Get the cpu_ops start location */
- adr x4, (__CPU_OPS_START__ + CPU_MIDR)
+ adr_l x4, (__CPU_OPS_START__ + CPU_MIDR)
2:
/* Check if we have reached end of list */
diff --git a/lib/cpus/aarch64/travis.S b/lib/cpus/aarch64/travis.S
index 2abefe9..ba06f55 100644
--- a/lib/cpus/aarch64/travis.S
+++ b/lib/cpus/aarch64/travis.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -38,7 +38,7 @@
mrs x0, ID_AA64PFR1_EL1
ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
#ID_AA64PFR1_EL1_SME_WIDTH
- cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED
+ cmp x0, #SME_NOT_IMPLEMENTED
b.eq 1f
msr TRAVIS_SVCRSM, xzr
msr TRAVIS_SVCRZA, xzr
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 301c60c..132888c 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -149,7 +149,7 @@
trf_init_el3();
}
- if (read_feat_pmuv3_id_field() >= 3U) {
+ if (is_feat_pmuv3_present()) {
pmuv3_init_el3();
}
#endif /* IMAGE_BL32 */
diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c
index b1409b9..98d57e9 100644
--- a/lib/extensions/sme/sme.c
+++ b/lib/extensions/sme/sme.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -53,7 +53,7 @@
* using SMCR_EL2 and SMCR_EL1.
*/
smcr_el3 = SMCR_ELX_LEN_MAX;
- if (read_feat_sme_fa64_id_field() != 0U) {
+ if (is_feat_sme_fa64_present()) {
VERBOSE("[SME] FA64 enabled\n");
smcr_el3 |= SMCR_ELX_FA64_BIT;
}
diff --git a/lib/pmf/pmf_smc.c b/lib/pmf/pmf_smc.c
index f3dd112..ac7f53a 100644
--- a/lib/pmf/pmf_smc.c
+++ b/lib/pmf/pmf_smc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,7 +36,8 @@
x2 = (uint32_t)x2;
x3 = (uint32_t)x3;
- if (smc_fid == PMF_SMC_GET_TIMESTAMP_32) {
+ if (smc_fid == PMF_SMC_GET_TIMESTAMP_32 ||
+ smc_fid == PMF_SMC_GET_TIMESTAMP_32_DEP) {
/*
* Return error code and the captured
* time-stamp to the caller.
@@ -48,8 +49,13 @@
SMC_RET3(handle, rc, (uint32_t)ts_value,
(uint32_t)(ts_value >> 32));
}
+
+ if (smc_fid == PMF_SMC_GET_VERSION_32) {
+ SMC_RET2(handle, SMC_OK, PMF_SMC_VERSION);
+ }
} else {
- if (smc_fid == PMF_SMC_GET_TIMESTAMP_64) {
+ if (smc_fid == PMF_SMC_GET_TIMESTAMP_64 ||
+ smc_fid == PMF_SMC_GET_TIMESTAMP_64_DEP) {
/*
* Return error code and the captured
* time-stamp to the caller.
@@ -60,6 +66,10 @@
(unsigned int)x3, &ts_value);
SMC_RET2(handle, rc, ts_value);
}
+
+ if (smc_fid == PMF_SMC_GET_VERSION_64) {
+ SMC_RET2(handle, SMC_OK, PMF_SMC_VERSION);
+ }
}
WARN("Unimplemented PMF Call: 0x%x \n", smc_fid);
diff --git a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
index 5a2120b..b462de0 100644
--- a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
+++ b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,7 +27,7 @@
{
uintptr_t ret;
- if (is_armv8_4_ttst_present()) {
+ if (is_feat_ttst_present()) {
ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
} else {
ret = MIN_VIRT_ADDR_SPACE_SIZE;
diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c
index 4dbfc11..f4195f4 100644
--- a/lib/xlat_tables/aarch64/xlat_tables.c
+++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -87,7 +87,7 @@
{
uintptr_t ret;
- if (is_armv8_4_ttst_present())
+ if (is_feat_ttst_present())
ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
else
ret = MIN_VIRT_ADDR_SPACE_SIZE;
diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
index 920754b..b63543c 100644
--- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -248,7 +248,7 @@
/* Set TTBR0 bits as well */
ttbr0 = (uint64_t)(uintptr_t) base_table;
- if (is_armv8_2_ttcnp_present()) {
+ if (is_feat_ttcnp_present()) {
/* Enable CnP bit so as to share page tables with all PEs. */
ttbr0 |= TTBR_CNP_BIT;
}
diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
index bb6a35c..18e001b 100644
--- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,19 +22,14 @@
*/
bool xlat_arch_is_granule_size_supported(size_t size)
{
- unsigned int tgranx;
-
if (size == PAGE_SIZE_4KB) {
- tgranx = read_id_aa64mmfr0_el0_tgran4_field();
/* MSB of TGRAN4 field will be '1' for unsupported feature */
- return (tgranx < 8U);
+ return is_feat_tgran4K_present();
} else if (size == PAGE_SIZE_16KB) {
- tgranx = read_id_aa64mmfr0_el0_tgran16_field();
- return (tgranx >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED);
+ return is_feat_tgran16K_present();
} else if (size == PAGE_SIZE_64KB) {
- tgranx = read_id_aa64mmfr0_el0_tgran64_field();
/* MSB of TGRAN64 field will be '1' for unsupported feature */
- return (tgranx < 8U);
+ return is_feat_tgran64K_present();
} else {
return false;
}
@@ -135,7 +130,7 @@
{
uintptr_t ret;
- if (is_armv8_4_ttst_present())
+ if (is_feat_ttst_present())
ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
else
ret = MIN_VIRT_ADDR_SPACE_SIZE;
@@ -312,7 +307,7 @@
/* Set TTBR bits as well */
ttbr0 = (uint64_t) base_table;
- if (is_armv8_2_ttcnp_present()) {
+ if (is_feat_ttcnp_present()) {
/* Enable CnP bit so as to share page tables with all PEs. */
ttbr0 |= TTBR_CNP_BIT;
}
diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c
index 3a9c058..971dba4 100644
--- a/lib/xlat_tables_v2/xlat_tables_core.c
+++ b/lib/xlat_tables_v2/xlat_tables_core.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -214,7 +214,7 @@
/* Set GP bit for block and page code entries
* if BTI mechanism is implemented.
*/
- if (is_armv8_5_bti_present() &&
+ if (is_feat_bti_present() &&
((attr & (MT_TYPE_MASK | MT_RW |
MT_EXECUTE_NEVER)) == MT_CODE)) {
desc |= GP;
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 07e69e6..a0e284f 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -7,70 +7,53 @@
include common/fdt_wrappers.mk
# Use the GICv3 driver on the FVP by default
-FVP_USE_GIC_DRIVER := FVP_GICV3
+FVP_USE_GIC_DRIVER := FVP_GICV3
# Default cluster count for FVP
-FVP_CLUSTER_COUNT := 2
+FVP_CLUSTER_COUNT := 2
# Default number of CPUs per cluster on FVP
FVP_MAX_CPUS_PER_CLUSTER := 4
# Default number of threads per CPU on FVP
-FVP_MAX_PE_PER_CPU := 1
+FVP_MAX_PE_PER_CPU := 1
# Disable redistributor frame of inactive/fused CPU cores by marking it as read
# only; enable redistributor frames of all CPU cores by default.
-FVP_GICR_REGION_PROTECTION := 0
+FVP_GICR_REGION_PROTECTION := 0
-FVP_DT_PREFIX := fvp-base-gicv3-psci
+FVP_DT_PREFIX := fvp-base-gicv3-psci
# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
# the FVP platform. This option defaults to 256.
-FVP_TRUSTED_SRAM_SIZE := 256
+FVP_TRUSTED_SRAM_SIZE := 256
# Macro to enable helpers for running SPM tests. Disabled by default.
PLAT_TEST_SPM := 0
-# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's
-# progbits limit. We need a way to build all useful configurations while waiting
-# on the fvp to increase its SRAM size. The problem is twofild:
-# 1. the cleanup that introduced these enables cleaned up tf-a a little too
-# well and things that previously (incorrectly) were enabled, no longer are.
-# A bunch of CI configs build subtly incorrectly and this combo makes it
-# necessary to forcefully and unconditionally enable them here.
-# 2. the progbits limit is exceeded only when the tsp is involved. However,
-# there are tsp CI configs that run on very high architecture revisions so
-# disabling everything isn't an option.
-# The fix is to enable everything, as before. When the tsp is included, though,
-# we need to slim the size down. In that case, disable all optional features,
-# that will not be present in CI when the tsp is.
-# Similarly, DRTM support is only tested on v8.0 models. Disable everything just
-# for it.
-# TODO: make all of this unconditional (or only base the condition on
-# ARM_ARCH_* when the makefile supports it).
-ifneq (${DRTM_SUPPORT}, 1)
-ifneq (${SPD}, tspd)
- ENABLE_FEAT_AMU := 2
- ENABLE_FEAT_AMUv1p1 := 2
- ENABLE_FEAT_HCX := 2
- ENABLE_FEAT_RNG := 2
- ENABLE_FEAT_TWED := 2
- ENABLE_FEAT_GCS := 2
+# By default dont build CPUs with no FVP model.
+BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0
+
+ENABLE_FEAT_AMU := 2
+ENABLE_FEAT_AMUv1p1 := 2
+ENABLE_FEAT_HCX := 2
+ENABLE_FEAT_RNG := 2
+ENABLE_FEAT_TWED := 2
+ENABLE_FEAT_GCS := 2
+
ifeq (${ARCH}, aarch64)
+
ifeq (${SPM_MM}, 0)
ifeq (${CTX_INCLUDE_FPREGS}, 0)
- ENABLE_SME_FOR_NS := 2
- ENABLE_SME2_FOR_NS := 2
-endif
-endif
+ ENABLE_SME_FOR_NS := 2
+ ENABLE_SME2_FOR_NS := 2
endif
endif
-# enable unconditionally for all builds
-ifeq (${ARCH}, aarch64)
- ENABLE_BRBE_FOR_NS := 2
- ENABLE_TRBE_FOR_NS := 2
+ ENABLE_BRBE_FOR_NS := 2
+ ENABLE_TRBE_FOR_NS := 2
endif
+
ENABLE_SYS_REG_TRACE_FOR_NS := 2
ENABLE_FEAT_CSV2_2 := 2
ENABLE_FEAT_CSV2_3 := 2
@@ -87,7 +70,6 @@
ENABLE_FEAT_S1PIE := 2
ENABLE_FEAT_S2POE := 2
ENABLE_FEAT_S1POE := 2
-endif
# The FVP platform depends on this macro to build with correct GIC driver.
$(eval $(call add_define,FVP_USE_GIC_DRIVER))
@@ -211,16 +193,21 @@
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/cortex_x2.S \
- lib/cpus/aarch64/cortex_x4.S \
- lib/cpus/aarch64/cortex_gelas.S \
- lib/cpus/aarch64/nevis.S \
- lib/cpus/aarch64/travis.S
+ lib/cpus/aarch64/cortex_x4.S
endif
# AArch64/AArch32 cores
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
lib/cpus/aarch64/cortex_a75.S
endif
+#Build AArch64-only CPUs with no FVP model yet.
+ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1)
+ FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_hermes.S \
+ lib/cpus/aarch64/cortex_gelas.S \
+ lib/cpus/aarch64/nevis.S \
+ lib/cpus/aarch64/travis.S
+endif
+
else
FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \
lib/cpus/aarch32/cortex_a57.S \
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 877ae8f..58a14ab 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -217,7 +217,7 @@
#ifdef __aarch64__
#if ENABLE_RME
/* BL2 runs in EL3 when RME enabled. */
- assert(get_armv9_2_feat_rme_support() != 0U);
+ assert(is_feat_rme_present());
enable_mmu_el3(0);
/* Initialise and enable granule protection after MMU. */
diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c
index 09226f4..18e9381 100644
--- a/plat/arm/common/arm_sip_svc.c
+++ b/plat/arm/common/arm_sip_svc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,9 +22,11 @@
static int arm_sip_setup(void)
{
+#if ENABLE_PMF
if (pmf_setup() != 0) {
return 1;
}
+#endif /* ENABLE_PMF */
#if USE_DEBUGFS
@@ -60,12 +62,13 @@
int call_count = 0;
#if ENABLE_PMF
-
/*
* Dispatch PMF calls to PMF SMC handler and return its return
* value
*/
- if (is_pmf_fid(smc_fid)) {
+ if (is_pmf_fid_deprecated(smc_fid)) {
+ NOTICE("PMF Interface usage from arm-sip range is deprecated. \
+ Please migrate smc call to Vendor-specific el3 range.\n");
return pmf_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
handle, flags);
}
@@ -73,8 +76,9 @@
#endif /* ENABLE_PMF */
#if USE_DEBUGFS
-
- if (is_debugfs_fid(smc_fid)) {
+ if (is_debugfs_fid_deprecated(smc_fid)) {
+ NOTICE("Debugfs Interface usage from arm-sip range is deprecated. \
+ Please migrate smc call to vendor-specific el3 range.\n");
return debugfs_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
handle, flags);
}
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
index 86c4b81..cb57668 100644
--- a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
@@ -37,18 +37,8 @@
int apusys_kernel_apusys_rv_setup_reviser(void)
{
- static bool apusys_rv_setup_reviser_called;
-
spin_lock(&apusys_rv_lock);
- if (apusys_rv_setup_reviser_called) {
- WARN(MODULE_TAG "%s: already initialized\n", __func__);
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- apusys_rv_setup_reviser_called = true;
-
mmio_write_32(USERFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
mmio_write_32(SECUREFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
@@ -74,18 +64,8 @@
int apusys_kernel_apusys_rv_reset_mp(void)
{
- static bool apusys_rv_reset_mp_called;
-
spin_lock(&apusys_rv_lock);
- if (apusys_rv_reset_mp_called) {
- WARN(MODULE_TAG "%s: already initialized\n", __func__);
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- apusys_rv_reset_mp_called = true;
-
mmio_write_32(MD32_SYS_CTRL, MD32_SYS_CTRL_RST);
dsb();
@@ -106,18 +86,8 @@
int apusys_kernel_apusys_rv_setup_boot(void)
{
- static bool apusys_rv_setup_boot_called;
-
spin_lock(&apusys_rv_lock);
- if (apusys_rv_setup_boot_called) {
- WARN(MODULE_TAG "%s: already initialized\n", __func__);
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- apusys_rv_setup_boot_called = true;
-
mmio_write_32(MD32_BOOT_CTRL, APU_SEC_FW_IOVA);
mmio_write_32(MD32_PRE_DEFINE, (PREDEFINE_CACHE_TCM << PREDEF_1G_OFS) |
@@ -130,55 +100,17 @@
int apusys_kernel_apusys_rv_start_mp(void)
{
- static bool apusys_rv_start_mp_called;
-
spin_lock(&apusys_rv_lock);
-
- if (apusys_rv_start_mp_called) {
- WARN(MODULE_TAG "%s: already initialized\n", __func__);
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- apusys_rv_start_mp_called = true;
-
mmio_write_32(MD32_RUNSTALL, MD32_RUN);
-
spin_unlock(&apusys_rv_lock);
return 0;
}
-static bool watch_dog_is_timeout(void)
-{
- if (mmio_read_32(WDT_INT) != WDT_INT_W1C) {
- ERROR(MODULE_TAG "%s: WDT does not timeout\n", __func__);
- return false;
- }
- return true;
-}
-
int apusys_kernel_apusys_rv_stop_mp(void)
{
- static bool apusys_rv_stop_mp_called;
-
spin_lock(&apusys_rv_lock);
-
- if (apusys_rv_stop_mp_called) {
- WARN(MODULE_TAG "%s: already initialized\n", __func__);
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- if (watch_dog_is_timeout() == false) {
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- apusys_rv_stop_mp_called = true;
-
mmio_write_32(MD32_RUNSTALL, MD32_STALL);
-
spin_unlock(&apusys_rv_lock);
return 0;
@@ -186,19 +118,10 @@
int apusys_kernel_apusys_rv_setup_sec_mem(void)
{
- static bool apusys_rv_setup_sec_mem_called;
int ret;
spin_lock(&apusys_rv_lock);
- if (apusys_rv_setup_sec_mem_called) {
- WARN(MODULE_TAG "%s: already initialized\n", __func__);
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- apusys_rv_setup_sec_mem_called = true;
-
ret = set_apu_emi_mpu_region();
if (ret != 0) {
ERROR(MODULE_TAG "%s: set emimpu protection failed\n", __func__);
@@ -230,12 +153,6 @@
int apusys_kernel_apusys_rv_cg_gating(void)
{
spin_lock(&apusys_rv_lock);
-
- if (watch_dog_is_timeout() == false) {
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
mmio_write_32(MD32_CLK_CTRL, MD32_CLK_DIS);
spin_unlock(&apusys_rv_lock);
@@ -245,12 +162,6 @@
int apusys_kernel_apusys_rv_cg_ungating(void)
{
spin_lock(&apusys_rv_lock);
-
- if (watch_dog_is_timeout() == false) {
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN);
spin_unlock(&apusys_rv_lock);
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
index da5242a..f4ff763 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
@@ -271,15 +271,8 @@
int apusys_devapc_rcx_init(void)
{
- static bool apusys_devapc_rcx_init_called;
enum apusys_apc_err_status ret;
- if (apusys_devapc_rcx_init_called == true) {
- INFO(MODULE_TAG "%s: init more than once!\n", __func__);
- return -1;
- }
- apusys_devapc_rcx_init_called = true;
-
apusys_devapc_init("APUAPC_CTRL_RCX", APU_CTRL_DAPC_RCX_BASE);
apusys_devapc_init("APUAPC_NOC_RCX", APU_NOC_DAPC_RCX_BASE);
diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c
index cd83a98..60acb25 100644
--- a/plat/qemu/common/qemu_bl2_setup.c
+++ b/plat/qemu/common/qemu_bl2_setup.c
@@ -217,7 +217,7 @@
#if ENABLE_RME
/* BL2 runs in EL3 when RME enabled. */
- assert(get_armv9_2_feat_rme_support() != 0U);
+ assert(is_feat_rme_present());
enable_mmu_el3(0);
/* Initialise and enable granule protection after MMU. */
diff --git a/plat/xilinx/common/include/pm_client.h b/plat/xilinx/common/include/pm_client.h
index a87923f..e9c36c3 100644
--- a/plat/xilinx/common/include/pm_client.h
+++ b/plat/xilinx/common/include/pm_client.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,7 +31,6 @@
#if defined(PLAT_zynqmp)
enum pm_ret_status pm_set_suspend_mode(uint32_t mode);
-const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid);
#endif /* PLAT_zynqmp */
#endif /* PM_CLIENT_H */
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index 45b1f1c..48d9f5f 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,6 +36,9 @@
}
proc = pm_get_proc((uint32_t)cpu_id);
+ if (!proc) {
+ return PSCI_E_INTERN_FAIL;
+ }
/* Send request to PMC to wake up selected ACPU core */
(void)pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U,
@@ -59,6 +62,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (!proc) {
+ return;
+ }
+
for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@@ -96,6 +103,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (!proc) {
+ return;
+ }
+
for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@@ -190,6 +201,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (!proc) {
+ return;
+ }
+
for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index 94cb7f5..7260403 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -63,6 +63,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (!proc) {
+ return;
+ }
+
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@@ -143,6 +147,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (!proc) {
+ return;
+ }
+
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@@ -186,6 +194,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (!proc) {
+ return;
+ }
+
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c
index c6c6c4b..9fd00db 100644
--- a/plat/xilinx/zynqmp/plat_psci.c
+++ b/plat/xilinx/zynqmp/plat_psci.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,7 +42,11 @@
if (cpu_id == -1) {
return PSCI_E_INTERN_FAIL;
}
+
proc = pm_get_proc(cpu_id);
+ if (!proc) {
+ return PSCI_E_INTERN_FAIL;
+ }
/* Check the APU proc status before wakeup */
ret = pm_get_node_status(proc->node_id, buff);
@@ -64,6 +68,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (!proc) {
+ return;
+ }
+
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@@ -89,6 +97,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (!proc) {
+ return;
+ }
+
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@@ -121,6 +133,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (!proc) {
+ return;
+ }
+
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.c b/plat/xilinx/zynqmp/pm_service/pm_client.c
index 4afa01d..9d0e2c4 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_client.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_client.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -245,23 +245,6 @@
}
/**
- * pm_get_proc_by_node() - returns pointer to the proc structure.
- * @nid: node id of the processor.
- *
- * Return: pointer to a proc structure if proc is found, otherwise NULL.
- *
- */
-const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid)
-{
- for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) {
- if (nid == pm_procs_all[i].node_id) {
- return &pm_procs_all[i];
- }
- }
- return NULL;
-}
-
-/**
* pm_get_cpuid() - get the local cpu ID for a global node ID.
* @nid: node id of the processor.
*
diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index 57d211e..5456164 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,7 +54,7 @@
* If architectural SSBS is available on this PE, no firmware
* mitigation via SMCCC_ARCH_WORKAROUND_2 is required.
*/
- if (ssbs != SSBS_UNAVAILABLE)
+ if (ssbs != SSBS_NOT_IMPLEMENTED)
return 1;
/*
diff --git a/services/el3/ven_el3_svc.c b/services/el3/ven_el3_svc.c
new file mode 100644
index 0000000..32a3dc2
--- /dev/null
+++ b/services/el3/ven_el3_svc.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <lib/debugfs.h>
+#include <lib/pmf/pmf.h>
+#include <services/ven_el3_svc.h>
+#include <tools_share/uuid.h>
+
+/* vendor-specific EL3 UUID */
+DEFINE_SVC_UUID2(ven_el3_svc_uid,
+ 0xb6011dca, 0x57c4, 0x407e, 0x83, 0xf0,
+ 0xa7, 0xed, 0xda, 0xf0, 0xdf, 0x6c);
+
+static int ven_el3_svc_setup(void)
+{
+#if USE_DEBUGFS
+ if (debugfs_smc_setup() != 0) {
+ return 1;
+ }
+#endif /* USE_DEBUGFS */
+
+#if ENABLE_PMF
+ if (pmf_setup() != 0) {
+ return 1;
+ }
+#endif /* ENABLE_PMF */
+
+ return 0;
+}
+
+/*
+ * This function handles Arm defined vendor-specific EL3 Service Calls.
+ */
+static uintptr_t ven_el3_svc_handler(unsigned int smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+#if USE_DEBUGFS
+ /*
+ * Dispatch debugfs calls to debugfs SMC handler and return its
+ * return value.
+ */
+ if (is_debugfs_fid(smc_fid)) {
+ return debugfs_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
+ handle, flags);
+ }
+#endif /* USE_DEBUGFS */
+
+#if ENABLE_PMF
+
+ /*
+ * Dispatch PMF calls to PMF SMC handler and return its return
+ * value
+ */
+ if (is_pmf_fid(smc_fid)) {
+ return pmf_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
+ handle, flags);
+ }
+
+#endif /* ENABLE_PMF */
+
+ switch (smc_fid) {
+ case VEN_EL3_SVC_UID:
+ /* Return UID to the caller */
+ SMC_UUID_RET(handle, ven_el3_svc_uid);
+ break;
+ case VEN_EL3_SVC_VERSION:
+ SMC_RET2(handle, VEN_EL3_SVC_VERSION_MAJOR, VEN_EL3_SVC_VERSION_MINOR);
+ break;
+ default:
+ WARN("Unimplemented vendor-specific EL3 Service call: 0x%x\n", smc_fid);
+ SMC_RET1(handle, SMC_UNK);
+ break;
+ }
+}
+
+/* Define a runtime service descriptor for fast SMC calls */
+DECLARE_RT_SVC(
+ ven_el3_svc,
+ OEN_VEN_EL3_START,
+ OEN_VEN_EL3_END,
+ SMC_TYPE_FAST,
+ ven_el3_svc_setup,
+ ven_el3_svc_handler
+);
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index 033e868..6ccb003 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -202,7 +202,7 @@
int rc;
/* Make sure RME is supported. */
- assert(get_armv9_2_feat_rme_support() != 0U);
+ assert(is_feat_rme_present());
rmm_ep_info = bl31_plat_get_next_image_ep_info(REALM);
if (rmm_ep_info == NULL) {