blob: 31fcfe2de85b7a95c5459ae2c6c084342eb8cf25 [file] [log] [blame]
/*
* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
compatible = "arm,tc";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &soc_uart0;
};
chosen {
bootargs = "console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute androidboot.boot_devices=1c050000.mmci ip=dhcp androidboot.selinux=permissive allow_mismatched_32bit_el0";
stdout-path = "serial0:115200n8";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};
/*
* The timings below are just to demonstrate working cpuidle.
* These values may be inaccurate.
*/
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2000>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
local-timer-stop;
entry-latency-us = <400>;
exit-latency-us = <1200>;
min-residency-us = <2500>;
};
};
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0>;
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <406>;
};
CPU1:cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x100>;
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <406>;
};
CPU2:cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x200>;
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <406>;
};
CPU3:cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x300>;
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <406>;
};
CPU4:cpu@400 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x400>;
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <912>;
};
CPU5:cpu@500 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x500>;
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <912>;
};
CPU6:cpu@600 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x600>;
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <912>;
};
CPU7:cpu@700 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x700>;
enable-method = "psci";
clocks = <&scmi_dvfs 2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
optee@0xfce00000 {
reg = <0x00000000 0xfce00000 0 0x00200000>;
no-map;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
sram: sram@6000000 {
compatible = "mmio-sram";
reg = <0x0 0x06000000 0x0 0x8000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x06000000 0x8000>;
cpu_scp_scmi_mem: scp-shmem@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x80>;
};
};
mbox_db_rx: mhu@45010000 {
compatible = "arm,mhuv2-rx","arm,primecell";
reg = <0x0 0x45010000 0x0 0x1000>;
clocks = <&soc_refclk100mhz>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupts = <0 317 4>;
interrupt-names = "mhu_rx";
mhu-protocol = "doorbell";
arm,mhuv2-protocols = <0 1>;
};
mbox_db_tx: mhu@45000000 {
compatible = "arm,mhuv2-tx","arm,primecell";
reg = <0x0 0x45000000 0x0 0x1000>;
clocks = <&soc_refclk100mhz>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupt-names = "mhu_tx";
mhu-protocol = "doorbell";
arm,mhuv2-protocols = <0 1>;
};
scmi {
compatible = "arm,scmi";
mbox-names = "tx", "rx";
mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
#address-cells = <1>;
#size-cells = <0>;
scmi_dvfs: protocol@13 {
reg = <0x13>;
#clock-cells = <1>;
};
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
gic: interrupt-controller@2c010000 {
compatible = "arm,gic-600", "arm,gic-v3";
#address-cells = <2>;
#interrupt-cells = <3>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x30000000 0 0x10000>, /* GICD */
<0x0 0x30080000 0 0x200000>; /* GICR */
interrupts = <0x1 0x9 0x4>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <0x1 13 0x8>,
<0x1 14 0x8>,
<0x1 11 0x8>,
<0x1 10 0x8>;
};
soc_refclk100mhz: refclk100mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
soc_refclk60mhz: refclk60mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
clock-output-names = "iofpga_clk";
};
soc_uartclk: uartclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "uartclk";
};
soc_uart0: uart@7ff80000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x7ff80000 0x0 0x1000>;
interrupts = <0x0 116 0x4>;
clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
status = "okay";
};
vencoder {
compatible = "drm,virtual-encoder";
port {
vencoder_in: endpoint {
remote-endpoint = <&dp_pl0_out0>;
};
};
display-timings {
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
vactive = <480>;
hfront-porch = <16>;
hback-porch = <48>;
hsync-len = <96>;
vfront-porch = <10>;
vback-porch = <33>;
vsync-len = <2>;
};
};
};
hdlcd: hdlcd@7ff60000 {
compatible = "arm,hdlcd";
reg = <0x0 0x7ff60000 0x0 0x1000>;
interrupts = <0x0 117 0x4>;
clocks = <&fake_hdlcd_clk>;
clock-names = "pxlclk";
status = "disabled";
port {
hdlcd_out: endpoint {
remote-endpoint = <&vencoder_in>;
};
};
};
fake_hdlcd_clk: fake-hdlcd-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25175000>;
clock-output-names = "pxlclk";
};
ethernet@18000000 {
compatible = "smsc,lan91c111";
reg = <0x0 0x18000000 0x0 0x10000>;
interrupts = <0 109 4>;
};
kmi@1c060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c060000 0x0 0x1000>;
interrupts = <0 197 4>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@1c070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c070000 0x0 0x1000>;
interrupts = <0 103 4>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
bp_clock24mhz: clock24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "bp:clock24mhz";
};
virtio_block@1c130000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c130000 0x0 0x200>;
interrupts = <0 204 4>;
};
sysreg: sysreg@1c010000 {
compatible = "arm,vexpress-sysreg";
reg = <0x0 0x001c010000 0x0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
};
fixed_3v3: v2m-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
mmci@1c050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x0 0x001c050000 0x0 0x1000>;
interrupts = <0 107 0x4>,
<0 108 0x4>;
cd-gpios = <&sysreg 0 0>;
wp-gpios = <&sysreg 1 0>;
bus-width = <8>;
max-frequency = <12000000>;
vmmc-supply = <&fixed_3v3>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "mclk", "apb_pclk";
};
dp0: display@2cc00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,mali-d71";
reg = <0 0x2cc00000 0 0x20000>;
interrupts = <0 69 4>;
interrupt-names = "DPU";
clocks = <&scmi_clk 0>;
clock-names = "aclk";
pl0: pipeline@0 {
reg = <0>;
clocks = <&scmi_clk 1>;
clock-names = "pxclk";
pl_id = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp_pl0_out0: endpoint {
remote-endpoint = <&vencoder_in>;
};
};
};
};
pl1: pipeline@1 {
reg = <1>;
clocks = <&scmi_clk 2>;
clock-names = "pxclk";
pl_id = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
};
};
};
};