plat/arm/common/arm_bl31_setup.c - filogic/atf - Gitiles

 /*
  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */

 #include <arch.h>
 #include <arch_helpers.h>
 #include <arm_def.h>
 #include <assert.h>
 #include <bl_common.h>
 #include <console.h>
 #include <debug.h>
 #include <mmio.h>
 #include <plat_arm.h>
 #include <platform.h>

 #define BL31_END (uintptr_t)(&__BL31_END__)

 /*
  * Placeholder variables for copying the arguments that have been passed to
  * BL31 from BL2.
  */
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;


 /* Weak definitions may be overridden in specific ARM standard platform */
 #pragma weak bl31_early_platform_setup2
 #pragma weak bl31_platform_setup
 #pragma weak bl31_plat_arch_setup
 #pragma weak bl31_plat_get_next_image_ep_info


 /*******************************************************************************
  * Return a pointer to the 'entry_point_info' structure of the next image for the
  * security state specified. BL33 corresponds to the non-secure image type
  * while BL32 corresponds to the secure image type. A NULL pointer is returned
  * if the image does not exist.
  ******************************************************************************/
 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
 {
 	entry_point_info_t *next_image_info;

 	assert(sec_state_is_valid(type));
 	next_image_info = (type == NON_SECURE)
 			? &bl33_image_ep_info : &bl32_image_ep_info;
 	/*
 	 * None of the images on the ARM development platforms can have 0x0
 	 * as the entrypoint
 	 */
 	if (next_image_info->pc)
 		return next_image_info;
 	else
 		return NULL;
 }

 /*******************************************************************************
  * Perform any BL31 early platform setup common to ARM standard platforms.
  * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
  * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
  * done before the MMU is initialized so that the memory layout can be used
  * while creating page tables. BL2 has flushed this information to memory, so
  * we are guaranteed to pick up good data.
  ******************************************************************************/
 #if LOAD_IMAGE_V2
 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
 				uintptr_t hw_config, void *plat_params_from_bl2)
 #else
 void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_config,
 				uintptr_t hw_config, void *plat_params_from_bl2)
 #endif
 {
 	/* Initialize the console to provide early debug support */
 	arm_console_boot_init();

 #if RESET_TO_BL31
 	/* There are no parameters from BL2 if BL31 is a reset vector */
 	assert(from_bl2 == NULL);
 	assert(plat_params_from_bl2 == NULL);

 #ifdef BL32_BASE
 	/* Populate entry point information for BL32 */
 	SET_PARAM_HEAD(&bl32_image_ep_info,
 				PARAM_EP,
 				VERSION_1,
 				0);
 	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
 	bl32_image_ep_info.pc = BL32_BASE;
 	bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
 #endif /* BL32_BASE */

 	/* Populate entry point information for BL33 */
 	SET_PARAM_HEAD(&bl33_image_ep_info,
 				PARAM_EP,
 				VERSION_1,
 				0);
 	/*
 	 * Tell BL31 where the non-trusted software image
 	 * is located and the entry state information
 	 */
 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();

 	bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);

 #else /* RESET_TO_BL31 */

 	/*
 	 * In debug builds, we pass a special value in 'plat_params_from_bl2'
 	 * to verify platform parameters from BL2 to BL31.
 	 * In release builds, it's not used.
 	 */
 	assert(((unsigned long long)plat_params_from_bl2) ==
 		ARM_BL31_PLAT_PARAM_VAL);

 # if LOAD_IMAGE_V2
 	/*
 	 * Check params passed from BL2 should not be NULL,
 	 */
 	bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
 	assert(params_from_bl2 != NULL);
 	assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
 	assert(params_from_bl2->h.version >= VERSION_2);

 	bl_params_node_t *bl_params = params_from_bl2->head;

 	/*
 	 * Copy BL33 and BL32 (if present), entry point information.
 	 * They are stored in Secure RAM, in BL2's address space.
 	 */
 	while (bl_params) {
 		if (bl_params->image_id == BL32_IMAGE_ID)
 			bl32_image_ep_info = *bl_params->ep_info;

 		if (bl_params->image_id == BL33_IMAGE_ID)
 			bl33_image_ep_info = *bl_params->ep_info;

 		bl_params = bl_params->next_params_info;
 	}

 	if (bl33_image_ep_info.pc == 0)
 		panic();

 # else /* LOAD_IMAGE_V2 */

 	/*
 	 * Check params passed from BL2 should not be NULL,
 	 */
 	assert(from_bl2 != NULL);
 	assert(from_bl2->h.type == PARAM_BL31);
 	assert(from_bl2->h.version >= VERSION_1);

 	/* Dynamic Config is not supported for LOAD_IMAGE_V1 */
 	assert(soc_fw_config == 0);
 	assert(hw_config == 0);

 	/*
 	 * Copy BL32 (if populated by BL2) and BL33 entry point information.
 	 * They are stored in Secure RAM, in BL2's address space.
 	 */
 	if (from_bl2->bl32_ep_info)
 		bl32_image_ep_info = *from_bl2->bl32_ep_info;
 	bl33_image_ep_info = *from_bl2->bl33_ep_info;

 # endif /* LOAD_IMAGE_V2 */
 #endif /* RESET_TO_BL31 */
 }

 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 		u_register_t arg2, u_register_t arg3)
 {
 	arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);

 	/*
 	 * Initialize Interconnect for this cluster during cold boot.
 	 * No need for locks as no other CPU is active.
 	 */
 	plat_arm_interconnect_init();

 	/*
 	 * Enable Interconnect coherency for the primary CPU's cluster.
 	 * Earlier bootloader stages might already do this (e.g. Trusted
 	 * Firmware's BL1 does it) but we can't assume so. There is no harm in
 	 * executing this code twice anyway.
 	 * Platform specific PSCI code will enable coherency for other
 	 * clusters.
 	 */
 	plat_arm_interconnect_enter_coherency();
 }

 /*******************************************************************************
  * Perform any BL31 platform setup common to ARM standard platforms
  ******************************************************************************/
 void arm_bl31_platform_setup(void)
 {
 	/* Initialize the GIC driver, cpu and distributor interfaces */
 	plat_arm_gic_driver_init();
 	plat_arm_gic_init();

 #if RESET_TO_BL31
 	/*
 	 * Do initial security configuration to allow DRAM/device access
 	 * (if earlier BL has not already done so).
 	 */
 	plat_arm_security_setup();

 #if defined(PLAT_ARM_MEM_PROT_ADDR)
 	arm_nor_psci_do_dyn_mem_protect();
 #endif /* PLAT_ARM_MEM_PROT_ADDR */

 #endif /* RESET_TO_BL31 */

 	/* Enable and initialize the System level generic timer */
 	mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
 			CNTCR_FCREQ(0) | CNTCR_EN);

 	/* Allow access to the System counter timer module */
 	arm_configure_sys_timer();

 	/* Initialize power controller before setting up topology */
 	plat_arm_pwrc_setup();
 }

 /*******************************************************************************
  * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM
  * standard platforms
  * Perform BL31 platform setup
  ******************************************************************************/
 void arm_bl31_plat_runtime_setup(void)
 {
 #if MULTI_CONSOLE_API
 	console_switch_state(CONSOLE_FLAG_RUNTIME);
 #else
 	console_uninit();
 #endif

 	/* Initialize the runtime console */
 	arm_console_runtime_init();
 }

 void bl31_platform_setup(void)
 {
 	arm_bl31_platform_setup();
 }

 void bl31_plat_runtime_setup(void)
 {
 	arm_bl31_plat_runtime_setup();
 }

 /*******************************************************************************
  * Perform the very early platform specific architectural setup shared between
  * ARM standard platforms. This only does basic initialization. Later
  * architectural setup (bl31_arch_setup()) does not do anything platform
  * specific.
  ******************************************************************************/
 void arm_bl31_plat_arch_setup(void)
 {
 	arm_setup_page_tables(BL31_BASE,
 			      BL31_END - BL31_BASE,
 			      BL_CODE_BASE,
 			      BL_CODE_END,
 			      BL_RO_DATA_BASE,
 			      BL_RO_DATA_END
 #if USE_COHERENT_MEM
 			      , BL_COHERENT_RAM_BASE,
 			      BL_COHERENT_RAM_END
 #endif
 			      );
 	enable_mmu_el3(0);
 }

 void bl31_plat_arch_setup(void)
 {
 	arm_bl31_plat_arch_setup();
 }
	/*
	* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
	*
	* SPDX-License-Identifier: BSD-3-Clause
	*/

	#include <arch.h>
	#include <arch_helpers.h>
	#include <arm_def.h>
	#include <assert.h>
	#include <bl_common.h>
	#include <console.h>
	#include <debug.h>
	#include <mmio.h>
	#include <plat_arm.h>
	#include <platform.h>

	#define BL31_END (uintptr_t)(&__BL31_END__)

	/*
	* Placeholder variables for copying the arguments that have been passed to
	* BL31 from BL2.
	*/
	static entry_point_info_t bl32_image_ep_info;
	static entry_point_info_t bl33_image_ep_info;


	/* Weak definitions may be overridden in specific ARM standard platform */
	#pragma weak bl31_early_platform_setup2
	#pragma weak bl31_platform_setup
	#pragma weak bl31_plat_arch_setup
	#pragma weak bl31_plat_get_next_image_ep_info


	/*******************************************************************************
	* Return a pointer to the 'entry_point_info' structure of the next image for the
	* security state specified. BL33 corresponds to the non-secure image type
	* while BL32 corresponds to the secure image type. A NULL pointer is returned
	* if the image does not exist.
	******************************************************************************/
	entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
	{
	entry_point_info_t *next_image_info;

	assert(sec_state_is_valid(type));
	next_image_info = (type == NON_SECURE)
	? &bl33_image_ep_info : &bl32_image_ep_info;
	/*
	* None of the images on the ARM development platforms can have 0x0
	* as the entrypoint
	*/
	if (next_image_info->pc)
	return next_image_info;
	else
	return NULL;
	}

	/*******************************************************************************
	* Perform any BL31 early platform setup common to ARM standard platforms.
	* Here is an opportunity to copy parameters passed by the calling EL (S-EL1
	* in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
	* done before the MMU is initialized so that the memory layout can be used
	* while creating page tables. BL2 has flushed this information to memory, so
	* we are guaranteed to pick up good data.
	******************************************************************************/
	#if LOAD_IMAGE_V2
	void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
	uintptr_t hw_config, void *plat_params_from_bl2)
	#else
	void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_config,
	uintptr_t hw_config, void *plat_params_from_bl2)
	#endif
	{
	/* Initialize the console to provide early debug support */
	arm_console_boot_init();

	#if RESET_TO_BL31
	/* There are no parameters from BL2 if BL31 is a reset vector */
	assert(from_bl2 == NULL);
	assert(plat_params_from_bl2 == NULL);

	#ifdef BL32_BASE
	/* Populate entry point information for BL32 */
	SET_PARAM_HEAD(&bl32_image_ep_info,
	PARAM_EP,
	VERSION_1,
	0);
	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
	bl32_image_ep_info.pc = BL32_BASE;
	bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
	#endif /* BL32_BASE */

	/* Populate entry point information for BL33 */
	SET_PARAM_HEAD(&bl33_image_ep_info,
	PARAM_EP,
	VERSION_1,
	0);
	/*
	* Tell BL31 where the non-trusted software image
	* is located and the entry state information
	*/
	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();

	bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);

	#else /* RESET_TO_BL31 */

	/*
	* In debug builds, we pass a special value in 'plat_params_from_bl2'
	* to verify platform parameters from BL2 to BL31.
	* In release builds, it's not used.
	*/
	assert(((unsigned long long)plat_params_from_bl2) ==
	ARM_BL31_PLAT_PARAM_VAL);

	# if LOAD_IMAGE_V2
	/*
	* Check params passed from BL2 should not be NULL,
	*/
	bl_params_t params_from_bl2 = (bl_params_t )from_bl2;
	assert(params_from_bl2 != NULL);
	assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
	assert(params_from_bl2->h.version >= VERSION_2);

	bl_params_node_t *bl_params = params_from_bl2->head;

	/*
	* Copy BL33 and BL32 (if present), entry point information.
	* They are stored in Secure RAM, in BL2's address space.
	*/
	while (bl_params) {
	if (bl_params->image_id == BL32_IMAGE_ID)
	bl32_image_ep_info = *bl_params->ep_info;

	if (bl_params->image_id == BL33_IMAGE_ID)
	bl33_image_ep_info = *bl_params->ep_info;

	bl_params = bl_params->next_params_info;
	}

	if (bl33_image_ep_info.pc == 0)
	panic();

	# else /* LOAD_IMAGE_V2 */

	/*
	* Check params passed from BL2 should not be NULL,
	*/
	assert(from_bl2 != NULL);
	assert(from_bl2->h.type == PARAM_BL31);
	assert(from_bl2->h.version >= VERSION_1);

	/* Dynamic Config is not supported for LOAD_IMAGE_V1 */
	assert(soc_fw_config == 0);
	assert(hw_config == 0);

	/*
	* Copy BL32 (if populated by BL2) and BL33 entry point information.
	* They are stored in Secure RAM, in BL2's address space.
	*/
	if (from_bl2->bl32_ep_info)
	bl32_image_ep_info = *from_bl2->bl32_ep_info;
	bl33_image_ep_info = *from_bl2->bl33_ep_info;

	# endif /* LOAD_IMAGE_V2 */
	#endif /* RESET_TO_BL31 */
	}

	void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
	u_register_t arg2, u_register_t arg3)
	{
	arm_bl31_early_platform_setup((void )arg0, arg1, arg2, (void )arg3);

	/*
	* Initialize Interconnect for this cluster during cold boot.
	* No need for locks as no other CPU is active.
	*/
	plat_arm_interconnect_init();

	/*
	* Enable Interconnect coherency for the primary CPU's cluster.
	* Earlier bootloader stages might already do this (e.g. Trusted
	* Firmware's BL1 does it) but we can't assume so. There is no harm in
	* executing this code twice anyway.
	* Platform specific PSCI code will enable coherency for other
	* clusters.
	*/
	plat_arm_interconnect_enter_coherency();
	}

	/*******************************************************************************
	* Perform any BL31 platform setup common to ARM standard platforms
	******************************************************************************/
	void arm_bl31_platform_setup(void)
	{
	/* Initialize the GIC driver, cpu and distributor interfaces */
	plat_arm_gic_driver_init();
	plat_arm_gic_init();

	#if RESET_TO_BL31
	/*
	* Do initial security configuration to allow DRAM/device access
	* (if earlier BL has not already done so).
	*/
	plat_arm_security_setup();

	#if defined(PLAT_ARM_MEM_PROT_ADDR)
	arm_nor_psci_do_dyn_mem_protect();
	#endif /* PLAT_ARM_MEM_PROT_ADDR */

	#endif /* RESET_TO_BL31 */

	/* Enable and initialize the System level generic timer */
	mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
	CNTCR_FCREQ(0) \| CNTCR_EN);

	/* Allow access to the System counter timer module */
	arm_configure_sys_timer();

	/* Initialize power controller before setting up topology */
	plat_arm_pwrc_setup();
	}

	/*******************************************************************************
	* Perform any BL31 platform runtime setup prior to BL31 exit common to ARM
	* standard platforms
	* Perform BL31 platform setup
	******************************************************************************/
	void arm_bl31_plat_runtime_setup(void)
	{
	#if MULTI_CONSOLE_API
	console_switch_state(CONSOLE_FLAG_RUNTIME);
	#else
	console_uninit();
	#endif

	/* Initialize the runtime console */
	arm_console_runtime_init();
	}

	void bl31_platform_setup(void)
	{
	arm_bl31_platform_setup();
	}

	void bl31_plat_runtime_setup(void)
	{
	arm_bl31_plat_runtime_setup();
	}

	/*******************************************************************************
	* Perform the very early platform specific architectural setup shared between
	* ARM standard platforms. This only does basic initialization. Later
	* architectural setup (bl31_arch_setup()) does not do anything platform
	* specific.
	******************************************************************************/
	void arm_bl31_plat_arch_setup(void)
	{
	arm_setup_page_tables(BL31_BASE,
	BL31_END - BL31_BASE,
	BL_CODE_BASE,
	BL_CODE_END,
	BL_RO_DATA_BASE,
	BL_RO_DATA_END
	#if USE_COHERENT_MEM
	, BL_COHERENT_RAM_BASE,
	BL_COHERENT_RAM_END
	#endif
	);
	enable_mmu_el3(0);
	}

	void bl31_plat_arch_setup(void)
	{
	arm_bl31_plat_arch_setup();
	}