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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 9e9fb4c010597f1d3d27889eedf2c2ad51236a73 / target / linux / mediatek / files-5.4 / arch / arm64 / boot / dts / mediatek / mt7981.dtsi
  1. 9e9fb4c [][Refactor mt7981 eth clk to real clk source from clk driver] by developer · Tue Nov 30 17:33:04 2021 +0800
  2. e3c7cd1 [][Change mt7981 eip97 and audio to enable clock by its own dts node] by developer · Tue Nov 30 14:49:26 2021 +0800
  3. a7de8be [][dts: mt7981: add efuse node for gphy calibration] by developer · Mon Nov 15 21:14:31 2021 +0800
  4. 33b0c63 [][Change spi source clk to 208M] by developer · Thu Nov 11 16:25:17 2021 +0800
  5. 3f7ec6d [][Fix system timer clock rate] by developer · Fri Nov 12 14:59:41 2021 +0800
  6. af7c350 [][Fix mt7981 snand clk to 52MHz] by developer · Wed Nov 10 20:49:31 2021 +0800
  7. 24455dd [][Add mt7981 dts/dtsi] by developer · Thu Oct 28 10:55:41 2021 +0800