blob: 6cecec91cf72582f8522ef4022613cf4c6e8bdc2 [file] [log] [blame]
developer565bacb2021-09-28 21:26:32 +08001/dts-v1/;
2#include "mt7986b.dtsi"
3#include "mt7986b-pinctrl.dtsi"
4#include "mt7986-spim-nand-partition.dtsi"
5/ {
6 model = "MediaTek MT7986b RFB";
7 compatible = "mediatek,mt7986b-spim-snand-rfb";
8 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16};
17
18&uart0 {
19 status = "okay";
20};
21
22/* Warning: pins shared with &snand */
23&uart1 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins>;
26 status = "disabled";
27};
28
29/* Warning: pins shared with &spi1 */
30&uart2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&uart2_pins>;
33 status = "disabled";
34};
35
36&i2c0 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&i2c_pins>;
39 status = "okay";
40};
41
42&watchdog {
43 status = "okay";
44};
45
46&eth {
47 status = "okay";
48
49 gmac0: mac@0 {
50 compatible = "mediatek,eth-mac";
51 reg = <0>;
52 phy-mode = "2500base-x";
53
54 fixed-link {
55 speed = <2500>;
56 full-duplex;
57 pause;
58 };
59 };
60
61 gmac1: mac@1 {
62 compatible = "mediatek,eth-mac";
63 reg = <1>;
64 phy-mode = "2500base-x";
65
66 fixed-link {
67 speed = <2500>;
68 full-duplex;
69 pause;
70 };
71 };
72
73 mdio: mdio-bus {
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 phy5: phy@5 {
78 compatible = "ethernet-phy-id67c9.de0a";
79 reg = <5>;
80 reset-gpios = <&pio 6 1>;
81 reset-deassert-us = <20000>;
82 phy-mode = "2500base-x";
83 };
84
85 phy6: phy@6 {
86 compatible = "ethernet-phy-id67c9.de0a";
87 reg = <6>;
88 phy-mode = "2500base-x";
89 };
90
91 switch@0 {
92 compatible = "mediatek,mt7531";
93 reg = <31>;
94 reset-gpios = <&pio 5 0>;
95
96 ports {
97 #address-cells = <1>;
98 #size-cells = <0>;
99
100 port@0 {
101 reg = <0>;
102 label = "lan0";
103 };
104
105 port@1 {
106 reg = <1>;
107 label = "lan1";
108 };
109
110 port@2 {
111 reg = <2>;
112 label = "lan2";
113 };
114
115 port@3 {
116 reg = <3>;
117 label = "lan3";
118 };
119
120 port@6 {
121 reg = <6>;
122 label = "cpu";
123 ethernet = <&gmac0>;
124 phy-mode = "2500base-x";
125
126 fixed-link {
127 speed = <2500>;
128 full-duplex;
129 pause;
130 };
131 };
132 };
133 };
134 };
135};
136
137&hnat {
138 mtketh-wan = "eth1";
139 mtketh-lan = "lan";
140 mtketh-max-gmac = <2>;
141 status = "okay";
142};
143
144&spi0 {
145 pinctrl-names = "default";
146 pinctrl-0 = <&spi_flash_pins>;
147 cs-gpios = <0>, <0>;
148 status = "okay";
149
150 spi_nor@0 {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 compatible = "jedec,spi-nor";
154 reg = <0>;
developerb9b1ffc2021-12-16 14:19:08 +0800155 spi-max-frequency = <52000000>;
developer565bacb2021-09-28 21:26:32 +0800156 spi-tx-buswidth = <4>;
157 spi-rx-buswidth = <4>;
158 };
159
160 spi_nand: spi_nand@1 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 compatible = "spi-nand";
164 reg = <1>;
developerb9b1ffc2021-12-16 14:19:08 +0800165 spi-max-frequency = <52000000>;
developer565bacb2021-09-28 21:26:32 +0800166 spi-tx-buswidth = <4>;
167 spi-rx-buswidth = <4>;
168 };
169};
170
171/* Warning: pins shared with &uart2 */
172&spi1 {
173 pinctrl-names = "default";
174 pinctrl-0 = <&spic_pins>;
175 status = "okay";
176};
177
178&wbsys {
179 mediatek,mtd-eeprom = <&factory 0x0000>;
180 status = "okay";
developere138bcd2021-12-06 09:20:47 +0800181 pinctrl-names = "default", "dbdc";
182 pinctrl-0 = <&wf_2g_5g_pins>;
183 pinctrl-1 = <&wf_dbdc_pins>;
developer565bacb2021-09-28 21:26:32 +0800184};
185
186&pio {
187 spi_flash_pins: spi-flash-pins-33-to-38 {
188 mux {
189 function = "flash";
190 groups = "spi0", "spi0_wp_hold";
191 };
192 conf-pu {
193 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
194 drive-strength = <MTK_DRIVE_8mA>;
195 mediatek,pull-up-adv = <0>; /* bias-disable */
196 };
197 conf-pd {
198 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
199 drive-strength = <MTK_DRIVE_8mA>;
200 mediatek,pull-down-adv = <0>; /* bias-disable */
201 };
202
203 };
developere138bcd2021-12-06 09:20:47 +0800204
205 wf_2g_5g_pins: wf_2g_5g-pins {
206 mux {
207 function = "wifi";
208 groups = "wf_2g", "wf_5g";
209 };
210 conf {
211 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
212 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
213 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
214 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
215 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
216 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
217 "WF1_TOP_CLK", "WF1_TOP_DATA";
218 drive-strength = <MTK_DRIVE_4mA>;
219 };
220 };
221
222 wf_dbdc_pins: wf_dbdc-pins {
223 mux {
224 function = "wifi";
225 groups = "wf_dbdc";
226 };
227 conf {
228 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
229 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
230 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
231 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
232 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
233 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
234 "WF1_TOP_CLK", "WF1_TOP_DATA";
235 drive-strength = <MTK_DRIVE_4mA>;
236 };
237 };
developer565bacb2021-09-28 21:26:32 +0800238};