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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 562703a0762ad78a11365cccdc4be4cb283bcd76 / . / autobuild_mac80211_release / mt7988_mt7996_mac80211 / target / linux / mediatek / patches-5.4 / 999-3021-mtk-wed-add-wed3-support.patch
blob: bccc43e9429cf6591532b255094cf33c08f2f6b8 [file] [log] [blame]
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1From 400f8349a31ffc48538aa7df64a88111de9a738b Mon Sep 17 00:00:00 2001
2From: Sujuan Chen <sujuan.chen@mediatek.com>
3Date: Thu, 13 Apr 2023 15:51:08 +0800
4Subject: [PATCH] mtk:wed:add wed3 support
5
6Signed-off-by: sujuan.chen <sujuan.chen@mediatek.com>
7---
8 arch/arm64/boot/dts/mediatek/mt7988.dtsi | 152 ++-
9 .../dts/mediatek/mt7988a-dsa-10g-spim-nor.dts | 16 +-
10 .../dts/mediatek/mt7988d-dsa-10g-spim-nor.dts | 16 +-
11 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 +-
12 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 +-
13 drivers/net/ethernet/mediatek/mtk_ppe.c | 17 +-
14 drivers/net/ethernet/mediatek/mtk_ppe.h | 2 +-
15 .../net/ethernet/mediatek/mtk_ppe_offload.c | 13 +-
16 drivers/net/ethernet/mediatek/mtk_wed.c | 1164 +++++++++++++----
17 drivers/net/ethernet/mediatek/mtk_wed.h | 25 +-
18 .../net/ethernet/mediatek/mtk_wed_debugfs.c | 584 ++++++++-
19 drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 13 +-
20 drivers/net/ethernet/mediatek/mtk_wed_mcu.h | 5 +-
21 drivers/net/ethernet/mediatek/mtk_wed_regs.h | 338 ++++-
22 include/linux/netdevice.h | 7 +
23 include/linux/soc/mediatek/mtk_wed.h | 81 +-
24 16 files changed, 1446 insertions(+), 333 deletions(-)
25 mode change 100755 => 100644 drivers/net/ethernet/mediatek/mtk_ppe.c
26
27diff --git a/arch/arm64/boot/dts/mediatek/mt7988.dtsi b/arch/arm64/boot/dts/mediatek/mt7988.dtsi
28index 364deef..f9a0120 100644
29--- a/arch/arm64/boot/dts/mediatek/mt7988.dtsi
30+++ b/arch/arm64/boot/dts/mediatek/mt7988.dtsi
31@@ -191,44 +191,49 @@
32 status = "disabled";
33 };
34
35- wed: wed@15010000 {
36- compatible = "mediatek,wed";
37- wed_num = <3>;
38- /* add this property for wed get the pci slot number. */
39- pci_slot_map = <0>, <1>, <2>;
40- reg = <0 0x15010000 0 0x2000>,
41- <0 0x15012000 0 0x2000>,
42- <0 0x15014000 0 0x2000>;
43+ wed0: wed@15010000 {
44+ compatible = "mediatek,mt7988-wed",
45+ "syscon";
46+ reg = <0 0x15010000 0 0x2000>;
47 interrupt-parent = <&gic>;
48- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
49- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
50- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
51- };
52-
53- wed2: wed2@15012000 {
54- compatible = "mediatek,wed2";
55- wed_num = <3>;
56- /* add this property for wed get the pci slot number. */
57- reg = <0 0x15010000 0 0x2000>,
58- <0 0x15012000 0 0x2000>,
59- <0 0x15014000 0 0x2000>;
60+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
61+ mediatek,wed_pcie = <&wed_pcie>;
62+ mediatek,ap2woccif = <&ap2woccif0>;
63+ mediatek,wocpu_ilm = <&wocpu0_ilm>;
64+ mediatek,wocpu_dlm = <&wocpu0_dlm>;
65+ mediatek,wocpu_boot = <&cpu0_boot>;
66+ mediatek,wocpu_emi = <&wocpu0_emi>;
67+ mediatek,wocpu_data = <&wocpu_data>;
68+ };
69+
70+ wed1: wed@15012000 {
71+ compatible = "mediatek,mt7988-wed",
72+ "syscon";
73+ reg = <0 0x15012000 0 0x2000>;
74 interrupt-parent = <&gic>;
75- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
76- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
77- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
78- };
79-
80- wed3: wed3@15014000 {
81- compatible = "mediatek,wed3";
82- wed_num = <3>;
83- /* add this property for wed get the pci slot number. */
84- reg = <0 0x15010000 0 0x2000>,
85- <0 0x15012000 0 0x2000>,
86- <0 0x15014000 0 0x2000>;
87+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
88+ mediatek,wed_pcie = <&wed_pcie>;
89+ mediatek,ap2woccif = <&ap2woccif1>;
90+ mediatek,wocpu_ilm = <&wocpu1_ilm>;
91+ mediatek,wocpu_dlm = <&wocpu1_dlm>;
92+ mediatek,wocpu_boot = <&cpu1_boot>;
93+ mediatek,wocpu_emi = <&wocpu1_emi>;
94+ mediatek,wocpu_data = <&wocpu_data>;
95+ };
96+
97+ wed2: wed@15014000 {
98+ compatible = "mediatek,mt7988-wed",
99+ "syscon";
100+ reg = <0 0x15014000 0 0x2000>;
101 interrupt-parent = <&gic>;
102- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
103- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
104- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
105+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
106+ mediatek,wed_pcie = <&wed_pcie>;
107+ mediatek,ap2woccif = <&ap2woccif2>;
108+ mediatek,wocpu_ilm = <&wocpu2_ilm>;
109+ mediatek,wocpu_dlm = <&wocpu2_dlm>;
110+ mediatek,wocpu_boot = <&cpu2_boot>;
111+ mediatek,wocpu_emi = <&wocpu2_emi>;
112+ mediatek,wocpu_data = <&wocpu_data>;
113 };
114
115 wdma: wdma@15104800 {
116@@ -238,15 +243,25 @@
117 <0 0x15105000 0 0x400>;
118 };
119
120- ap2woccif: ap2woccif@151A5000 {
121- compatible = "mediatek,ap2woccif";
122- reg = <0 0x151A5000 0 0x1000>,
123- <0 0x152A5000 0 0x1000>,
124- <0 0x153A5000 0 0x1000>;
125+ ap2woccif0: ap2woccif@151A5000 {
126+ compatible = "mediatek,ap2woccif", "syscon";
127+ reg = <0 0x151A5000 0 0x1000>;
128+ interrupt-parent = <&gic>;
129+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
130+ };
131+
132+ ap2woccif1: ap2woccif@152A5000 {
133+ compatible = "mediatek,ap2woccif", "syscon";
134+ reg = <0 0x152A5000 0 0x1000>;
135 interrupt-parent = <&gic>;
136- interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
137- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
138- <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
139+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
140+ };
141+
142+ ap2woccif2: ap2woccif@153A5000 {
143+ compatible = "mediatek,ap2woccif", "syscon";
144+ reg = <0 0x153A5000 0 0x1000>;
145+ interrupt-parent = <&gic>;
146+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
147 };
148
149 wocpu0_ilm: wocpu0_ilm@151E0000 {
150@@ -254,31 +269,53 @@
151 reg = <0 0x151E0000 0 0x8000>;
152 };
153
154- wocpu1_ilm: wocpu1_ilm@152E0000 {
155- compatible = "mediatek,wocpu1_ilm";
156+ wocpu1_ilm: wocpu_ilm@152E0000 {
157+ compatible = "mediatek,wocpu_ilm";
158 reg = <0 0x152E0000 0 0x8000>;
159 };
160
161- wocpu2_ilm: wocpu2_ilm@153E0000 {
162- compatible = "mediatek,wocpu2_ilm";
163- reg = <0 0x153E0000 0 0x8000>;
164+ wocpu2_ilm: wocpu_ilm@153E0000 {
165+ compatible = "mediatek,wocpu_ilm";
166+ reg = <0 0x153E0000 0 0x8000>;
167+ };
168+
169+ wocpu0_dlm: wocpu_dlm@151E8000 {
170+ compatible = "mediatek,wocpu_dlm";
171+ reg = <0 0x151E8000 0 0x2000>;
172+
173+ resets = <&ethsysrst 0>;
174+ reset-names = "wocpu_rst";
175+ };
176+
177+ wocpu1_dlm: wocpu_dlm@0x152E8000 {
178+ compatible = "mediatek,wocpu_dlm";
179+ reg = <0 0x152E8000 0 0x2000>;
180+
181+ resets = <&ethsysrst 0>;
182+ reset-names = "wocpu_rst";
183 };
184
185- wocpu_dlm: wocpu_dlm@151E8000 {
186+ wocpu2_dlm: wocpu_dlm@0x153E8000 {
187 compatible = "mediatek,wocpu_dlm";
188- reg = <0 0x151E8000 0 0x2000>,
189- <0 0x152E8000 0 0x2000>,
190- <0 0x153E8000 0 0x2000>;
191+ reg = <0 0x153E8000 0 0x2000>;
192
193 resets = <&ethsysrst 0>;
194 reset-names = "wocpu_rst";
195 };
196
197- cpu_boot: wocpu_boot@15194000 {
198- compatible = "mediatek,wocpu_boot";
199- reg = <0 0x15194000 0 0x1000>,
200- <0 0x15294000 0 0x1000>,
201- <0 0x15394000 0 0x1000>;
202+ cpu0_boot: wocpu_boot@15194000 {
203+ compatible = "mediatek,wocpu0_boot";
204+ reg = <0 0x15194000 0 0x1000>;
205+ };
206+
207+ cpu1_boot: wocpu_boot@15294000 {
208+ compatible = "mediatek,wocpu1_boot";
209+ reg = <0 0x15294000 0 0x1000>;
210+ };
211+
212+ cpu2_boot: wocpu_boot@15394000 {
213+ compatible = "mediatek,wocpu2_boot";
214+ reg = <0 0x15394000 0 0x1000>;
215 };
216
217 reserved-memory {
218@@ -827,6 +864,7 @@
219 <&topckgen CK_TOP_CB_SGM_325M>;
220 mediatek,ethsys = <&ethsys>;
221 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
222+ mediatek,wed = <&wed0>, <&wed1>, <&wed2>;
223 mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
224 mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
225 mediatek,xfi_pll = <&xfi_pll>;
226diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts b/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts
227index 7db5164..0a6db8b 100644
228--- a/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts
229+++ b/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts
230@@ -341,9 +341,23 @@
231 status = "okay";
232 };
233
234-&wed {
235+&wed0 {
236 dy_txbm_enable = "true";
237 dy_txbm_budge = <8>;
238 txbm_init_sz = <10>;
239 status = "okay";
240 };
241+
242+&wed1 {
243+ dy_txbm_enable = "true";
244+ dy_txbm_budge = <8>;
245+ txbm_init_sz = <10>;
246+ status = "okay";
247+};
248+
249+&wed2 {
250+ dy_txbm_enable = "true";
251+ dy_txbm_budge = <8>;
252+ txbm_init_sz = <10>;
253+ status = "okay";
254+};
255\ No newline at end of file
256diff --git a/arch/arm64/boot/dts/mediatek/mt7988d-dsa-10g-spim-nor.dts b/arch/arm64/boot/dts/mediatek/mt7988d-dsa-10g-spim-nor.dts
257index 67c6508..c407b33 100644
258--- a/arch/arm64/boot/dts/mediatek/mt7988d-dsa-10g-spim-nor.dts
259+++ b/arch/arm64/boot/dts/mediatek/mt7988d-dsa-10g-spim-nor.dts
260@@ -325,9 +325,23 @@
261 status = "okay";
262 };
263
264-&wed {
265+&wed0 {
266 dy_txbm_enable = "true";
267 dy_txbm_budge = <8>;
268 txbm_init_sz = <10>;
269 status = "okay";
270 };
271+
272+&wed1 {
273+ dy_txbm_enable = "true";
274+ dy_txbm_budge = <8>;
275+ txbm_init_sz = <10>;
276+ status = "okay";
277+};
278+
279+&wed2 {
280+ dy_txbm_enable = "true";
281+ dy_txbm_budge = <8>;
282+ txbm_init_sz = <10>;
283+ status = "okay";
284+};
285\ No newline at end of file
286diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
287index 388982c..d59c29f 100644
288--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
289+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
290@@ -4709,7 +4709,8 @@ static int mtk_probe(struct platform_device *pdev)
291 "mediatek,wed", i);
292 static const u32 wdma_regs[] = {
293 MTK_WDMA0_BASE,
294- MTK_WDMA1_BASE
295+ MTK_WDMA1_BASE,
296+ MTK_WDMA2_BASE
297 };
298 void __iomem *wdma;
299 u32 wdma_phy;
300diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
301index a9feaed..70e8377 100644
302--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
303+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
304@@ -605,9 +605,12 @@
305 #define RX_DMA_SPORT_MASK 0x7
306 #define RX_DMA_SPORT_MASK_V2 0xf
307
308-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
309+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
310 #define MTK_WDMA0_BASE 0x4800
311 #define MTK_WDMA1_BASE 0x4c00
312+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
313+#define MTK_WDMA2_BASE 0x5000
314+#endif
315 #else
316 #define MTK_WDMA0_BASE 0x2800
317 #define MTK_WDMA1_BASE 0x2c00
318diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c
319old mode 100755
320new mode 100644
321index bc13a9b..3910163
322--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
323+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
324@@ -9,6 +9,7 @@
325 #include <linux/if_ether.h>
326 #include <linux/if_vlan.h>
327 #include <net/dsa.h>
328+#include <net/route.h>
329 #include "mtk_eth_soc.h"
330 #include "mtk_ppe.h"
331 #include "mtk_ppe_regs.h"
332@@ -396,7 +397,7 @@ int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid)
333 }
334
335 int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,
336- int bss, int wcid)
337+ int bss, int wcid, bool amsdu_en)
338 {
339 struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
340 u32 *ib2 = mtk_foe_entry_ib2(entry);
341@@ -408,6 +409,9 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,
342
343 l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) |
344 FIELD_PREP(MTK_FOE_WINFO_BSS, bss);
345+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
346+ l2->winfo_pao = FIELD_PREP(MTK_FOE_WINFO_PAO_AMSDU_EN, amsdu_en);
347+#endif
348 #else
349 if (wdma_idx)
350 *ib2 |= MTK_FOE_IB2_WDMA_DEVIDX;
351@@ -443,6 +447,17 @@ int mtk_foe_entry_set_dscp(struct mtk_foe_entry *entry, int dscp)
352 *ib2 &= ~MTK_FOE_IB2_DSCP;
353 *ib2 |= FIELD_PREP(MTK_FOE_IB2_DSCP, dscp);
354
355+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
356+ struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
357+
358+ if (*ib2 & MTK_FOE_IB2_WDMA_WINFO &&
359+ l2->winfo_pao & MTK_FOE_WINFO_PAO_AMSDU_EN) {
360+ u8 tid = rt_tos2priority(dscp) & 0xf;
361+
362+ l2->winfo_pao |= FIELD_PREP(MTK_FOE_WINFO_PAO_TID, tid);
363+ }
364+#endif
365+
366 return 0;
367 }
368
369diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h
370index df10040..9e7d5aa 100644
371--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
372+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
373@@ -428,7 +428,7 @@ int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port);
374 int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid);
375 int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid);
376 int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,
377- int bss, int wcid);
378+ int bss, int wcid, bool amsdu_en);
379 int mtk_foe_entry_set_qid(struct mtk_foe_entry *entry, int qid);
380 int mtk_foe_entry_set_dscp(struct mtk_foe_entry *entry, int dscp);
381 int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
382diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
383index 9bc0857..86fc9a1 100644
384--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
385+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
386@@ -112,6 +112,7 @@ mtk_flow_get_wdma_info(struct net_device *dev, const u8 *addr, struct mtk_wdma_i
387 info->queue = path.mtk_wdma.queue;
388 info->bss = path.mtk_wdma.bss;
389 info->wcid = path.mtk_wdma.wcid;
390+ info->amsdu_en = path.mtk_wdma.amsdu_en;
391
392 return 0;
393 }
394@@ -193,13 +194,15 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe,
395
396 if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) {
397 mtk_foe_entry_set_wdma(foe, info.wdma_idx, info.queue, info.bss,
398- info.wcid);
399+ info.wcid, info.amsdu_en);
400 pse_port = PSE_PPE0_PORT;
401 #if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
402 if (info.wdma_idx == 0)
403 pse_port = PSE_WDMA0_PORT;
404 else if (info.wdma_idx == 1)
405 pse_port = PSE_WDMA1_PORT;
406+ else if (info.wdma_idx == 2)
407+ pse_port = PSE_WDMA2_PORT;
408 else
409 return -EOPNOTSUPP;
410 #endif
411@@ -458,8 +461,8 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f)
412 if (err)
413 return err;
414
415- if (wed_index >= 0 && (err = mtk_wed_flow_add(wed_index)) < 0)
416- return err;
417+ /*if (wed_index >= 0 && (err = mtk_wed_flow_add(wed_index)) < 0)
418+ return err;*/
419
420 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
421 if (!entry)
422@@ -499,8 +502,8 @@ clear:
423 mtk_foe_entry_clear(eth->ppe[i], entry);
424 free:
425 kfree(entry);
426- if (wed_index >= 0)
427- mtk_wed_flow_remove(wed_index);
428+ /*if (wed_index >= 0)
429+ mtk_wed_flow_remove(wed_index);*/
430 return err;
431 }
432
433diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c
434index 37a86c3..e3809db 100644
435--- a/drivers/net/ethernet/mediatek/mtk_wed.c
436+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
437@@ -28,7 +28,7 @@ struct wo_cmd_ring {
438 u32 cnt;
439 u32 unit;
440 };
441-static struct mtk_wed_hw *hw_list[2];
442+static struct mtk_wed_hw *hw_list[3];
443 static DEFINE_MUTEX(hw_lock);
444
445 static void
446@@ -73,6 +73,26 @@ mtk_wdma_read_reset(struct mtk_wed_device *dev)
447 return wdma_r32(dev, MTK_WDMA_GLO_CFG);
448 }
449
450+static u32
451+mtk_wed_check_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
452+{
453+ if (wed_r32(dev, reg) & mask)
454+ return true;
455+
456+ return false;
457+}
458+
459+static int
460+mtk_wed_poll_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
461+{
462+ int sleep = 1000;
463+ int timeout = 100 * sleep;
464+ u32 val;
465+
466+ return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
467+ timeout, false, dev, reg, mask);
468+}
469+
470 static int
471 mtk_wdma_rx_reset(struct mtk_wed_device *dev)
472 {
473@@ -235,6 +255,8 @@ mtk_wed_assign(struct mtk_wed_device *dev)
474 continue;
475
476 hw->wed_dev = dev;
477+ hw->pci_base = MTK_WED_PCIE_BASE;
478+
479 return hw;
480 }
481
482@@ -242,23 +264,84 @@ mtk_wed_assign(struct mtk_wed_device *dev)
483 }
484
485 static int
486-mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
487+mtk_wed_pao_buffer_alloc(struct mtk_wed_device *dev)
488+{
489+ struct mtk_wed_pao *pao;
490+ int i, j;
491+
492+ pao = kzalloc(sizeof(struct mtk_wed_pao), GFP_KERNEL);
493+ if (!pao)
494+ return -ENOMEM;
495+
496+ dev->hw->wed_pao = pao;
497+
498+ for (i = 0; i < 32; i++) {
499+ /* each segment is 64K*/
500+ pao->hif_txd[i] = (char *)__get_free_pages(GFP_ATOMIC |
501+ GFP_DMA32 |
502+ __GFP_ZERO, 4);
503+ if (!pao->hif_txd[i])
504+ goto err;
505+
506+ pao->hif_txd_phys[i] = dma_map_single(dev->hw->dev,
507+ pao->hif_txd[i],
508+ 16 * PAGE_SIZE,
509+ DMA_TO_DEVICE);
510+ if (unlikely(dma_mapping_error(dev->hw->dev,
511+ pao->hif_txd_phys[i])))
512+ goto err;
513+ }
514+
515+ return 0;
516+
517+err:
518+ for (j = 0; j < i; j++)
519+ dma_unmap_single(dev->hw->dev, pao->hif_txd_phys[j],
520+ 16 * PAGE_SIZE, DMA_TO_DEVICE);
521+
522+ return -ENOMEM;
523+}
524+
525+static int
526+mtk_wed_pao_free_buffer(struct mtk_wed_device *dev)
527+{
528+ struct mtk_wed_pao *pao = dev->hw->wed_pao;
529+ int i;
530+
531+ for (i = 0; i < 32; i++) {
532+ dma_unmap_single(dev->hw->dev, pao->hif_txd_phys[i],
533+ 16 * PAGE_SIZE, DMA_TO_DEVICE);
534+ free_pages((unsigned long)pao->hif_txd[i], 4);
535+ }
536+
537+ return 0;
538+}
539+
540+static int
541+mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
542 {
543 struct mtk_wdma_desc *desc;
544+ void *desc_ptr;
545 dma_addr_t desc_phys;
546- void **page_list;
547+ struct dma_page_info *page_list;
548 u32 last_seg = MTK_WDMA_DESC_CTRL_LAST_SEG1;
549 int token = dev->wlan.token_start;
550- int ring_size, n_pages, page_idx;
551- int i;
552-
553+ int ring_size, pkt_nums, n_pages, page_idx;
554+ int i, ret = 0;
555
556 if (dev->ver == MTK_WED_V1) {
557 ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
558- } else {
559+ pkt_nums = ring_size;
560+ dev->tx_buf_ring.desc_size = sizeof(struct mtk_wdma_desc);
561+ } else if (dev->hw->version == 2) {
562 ring_size = MTK_WED_VLD_GROUP_SIZE * MTK_WED_PER_GROUP_PKT +
563 MTK_WED_WDMA_RING_SIZE * 2;
564 last_seg = MTK_WDMA_DESC_CTRL_LAST_SEG0;
565+ dev->tx_buf_ring.desc_size = sizeof(struct mtk_wdma_desc);
566+ } else if (dev->hw->version == 3) {
567+ ring_size = MTK_WED_TX_BM_DMA_SIZE;
568+ pkt_nums = MTK_WED_TX_BM_PKT_CNT;
569+ dev->tx_buf_ring.desc_size = sizeof(struct mtk_rxbm_desc);
570 }
571
572 n_pages = ring_size / MTK_WED_BUF_PER_PAGE;
573@@ -267,18 +350,20 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
574 if (!page_list)
575 return -ENOMEM;
576
577- dev->buf_ring.size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
578- dev->buf_ring.pages = page_list;
579+ dev->tx_buf_ring.size = ring_size;
580+ dev->tx_buf_ring.pages = page_list;
581+ dev->tx_buf_ring.pkt_nums = pkt_nums;
582
583- desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),
584- &desc_phys, GFP_KERNEL);
585- if (!desc)
586+ desc_ptr = dma_alloc_coherent(dev->hw->dev,
587+ ring_size * dev->tx_buf_ring.desc_size,
588+ &desc_phys, GFP_KERNEL);
589+ if (!desc_ptr)
590 return -ENOMEM;
591
592- dev->buf_ring.desc = desc;
593- dev->buf_ring.desc_phys = desc_phys;
594+ dev->tx_buf_ring.desc = desc_ptr;
595+ dev->tx_buf_ring.desc_phys = desc_phys;
596
597- for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
598+ for (i = 0, page_idx = 0; i < pkt_nums; i += MTK_WED_BUF_PER_PAGE) {
599 dma_addr_t page_phys, buf_phys;
600 struct page *page;
601 void *buf;
602@@ -295,7 +380,10 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
603 return -ENOMEM;
604 }
605
606- page_list[page_idx++] = page;
607+ page_list[page_idx].addr = page;
608+ page_list[page_idx].addr_phys = page_phys;
609+ page_idx++;
610+
611 dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,
612 DMA_BIDIRECTIONAL);
613
614@@ -303,19 +391,23 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
615 buf_phys = page_phys;
616
617 for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {
618- u32 txd_size;
619-
620- txd_size = dev->wlan.init_buf(buf, buf_phys, token++);
621-
622+ desc = desc_ptr;
623 desc->buf0 = buf_phys;
624- desc->buf1 = buf_phys + txd_size;
625- desc->ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0,
626- txd_size) |
627- FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
628- MTK_WED_BUF_SIZE - txd_size) |
629- last_seg;
630- desc->info = 0;
631- desc++;
632+ if (dev->hw->version < 3) {
633+ u32 txd_size;
634+
635+ txd_size = dev->wlan.init_buf(buf, buf_phys, token++);
636+ desc->buf1 = buf_phys + txd_size;
637+ desc->ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0,
638+ txd_size) |
639+ FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
640+ MTK_WED_BUF_SIZE - txd_size) |
641+ last_seg;
642+ desc->info = 0;
643+ } else {
644+ desc->ctrl = token << 16;
645+ }
646+ desc_ptr += dev->tx_buf_ring.desc_size;
647
648 buf += MTK_WED_BUF_SIZE;
649 buf_phys += MTK_WED_BUF_SIZE;
650@@ -325,15 +417,18 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
651 DMA_BIDIRECTIONAL);
652 }
653
654- return 0;
655+ if (dev->hw->version == 3)
656+ ret = mtk_wed_pao_buffer_alloc(dev);
657+
658+ return ret;
659 }
660
661 static void
662-mtk_wed_free_buffer(struct mtk_wed_device *dev)
663+mtk_wed_free_tx_buffer(struct mtk_wed_device *dev)
664 {
665- struct mtk_wdma_desc *desc = dev->buf_ring.desc;
666- void **page_list = dev->buf_ring.pages;
667- int ring_size, page_idx;
668+ struct mtk_rxbm_desc *desc = dev->tx_buf_ring.desc;
669+ struct dma_page_info *page_list = dev->tx_buf_ring.pages;
670+ int ring_size, page_idx, pkt_nums;
671 int i;
672
673 if (!page_list)
674@@ -342,33 +437,33 @@ mtk_wed_free_buffer(struct mtk_wed_device *dev)
675 if (!desc)
676 goto free_pagelist;
677
678- if (dev->ver == MTK_WED_V1) {
679- ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
680- } else {
681- ring_size = MTK_WED_VLD_GROUP_SIZE * MTK_WED_PER_GROUP_PKT +
682- MTK_WED_WDMA_RING_SIZE * 2;
683+ pkt_nums = ring_size = dev->tx_buf_ring.size;
684+ if (dev->hw->version == 3) {
685+ mtk_wed_pao_free_buffer(dev);
686+ pkt_nums = dev->tx_buf_ring.pkt_nums;
687 }
688
689- for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
690- void *page = page_list[page_idx++];
691+ for (i = 0, page_idx = 0; i < pkt_nums; i += MTK_WED_BUF_PER_PAGE) {
692+ void *page = page_list[page_idx].addr;
693
694 if (!page)
695 break;
696
697- dma_unmap_page(dev->hw->dev, desc[i].buf0,
698+ dma_unmap_page(dev->hw->dev, page_list[page_idx].addr_phys,
699 PAGE_SIZE, DMA_BIDIRECTIONAL);
700 __free_page(page);
701+ page_idx++;
702 }
703
704- dma_free_coherent(dev->hw->dev, ring_size * sizeof(*desc),
705- desc, dev->buf_ring.desc_phys);
706+ dma_free_coherent(dev->hw->dev, ring_size * dev->tx_buf_ring.desc_size,
707+ dev->tx_buf_ring.desc, dev->tx_buf_ring.desc_phys);
708
709 free_pagelist:
710 kfree(page_list);
711 }
712
713 static int
714-mtk_wed_rx_bm_alloc(struct mtk_wed_device *dev)
715+mtk_wed_rx_buffer_alloc(struct mtk_wed_device *dev)
716 {
717 struct mtk_rxbm_desc *desc;
718 dma_addr_t desc_phys;
719@@ -389,7 +484,7 @@ mtk_wed_rx_bm_alloc(struct mtk_wed_device *dev)
720 }
721
722 static void
723-mtk_wed_free_rx_bm(struct mtk_wed_device *dev)
724+mtk_wed_free_rx_buffer(struct mtk_wed_device *dev)
725 {
726 struct mtk_rxbm_desc *desc = dev->rx_buf_ring.desc;
727 int ring_size = dev->rx_buf_ring.size;
728@@ -403,6 +498,113 @@ mtk_wed_free_rx_bm(struct mtk_wed_device *dev)
729 desc, dev->rx_buf_ring.desc_phys);
730 }
731
732+/* TODO */
733+static int
734+mtk_wed_rx_page_buffer_alloc(struct mtk_wed_device *dev)
735+{
736+ int ring_size = dev->wlan.rx_nbuf, buf_num = MTK_WED_RX_PG_BM_CNT;
737+ struct mtk_rxbm_desc *desc;
738+ dma_addr_t desc_phys;
739+ struct dma_page_info *page_list;
740+ int n_pages, page_idx;
741+ int i;
742+
743+ n_pages = buf_num / MTK_WED_RX_PAGE_BUF_PER_PAGE;
744+
745+ page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);
746+ if (!page_list)
747+ return -ENOMEM;
748+
749+ dev->rx_page_buf_ring.size = ring_size & ~(MTK_WED_BUF_PER_PAGE - 1);
750+ dev->rx_page_buf_ring.pages = page_list;
751+ dev->rx_page_buf_ring.pkt_nums = buf_num;
752+
753+ desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),
754+ &desc_phys, GFP_KERNEL);
755+ if (!desc)
756+ return -ENOMEM;
757+
758+ dev->rx_page_buf_ring.desc = desc;
759+ dev->rx_page_buf_ring.desc_phys = desc_phys;
760+
761+ for (i = 0, page_idx = 0; i < buf_num; i += MTK_WED_RX_PAGE_BUF_PER_PAGE) {
762+ dma_addr_t page_phys, buf_phys;
763+ struct page *page;
764+ void *buf;
765+ int s;
766+
767+ page = __dev_alloc_pages(GFP_KERNEL, 0);
768+ if (!page)
769+ return -ENOMEM;
770+
771+ page_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE,
772+ DMA_BIDIRECTIONAL);
773+ if (dma_mapping_error(dev->hw->dev, page_phys)) {
774+ __free_page(page);
775+ return -ENOMEM;
776+ }
777+
778+ page_list[page_idx].addr= page;
779+ page_list[page_idx].addr_phys= page_phys;
780+ page_idx++;
781+
782+ dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,
783+ DMA_BIDIRECTIONAL);
784+
785+ buf = page_to_virt(page);
786+ buf_phys = page_phys;
787+
788+ for (s = 0; s < MTK_WED_RX_PAGE_BUF_PER_PAGE; s++) {
789+
790+ desc->buf0 = cpu_to_le32(buf_phys);
791+ desc++;
792+
793+ buf += MTK_WED_PAGE_BUF_SIZE;
794+ buf_phys += MTK_WED_PAGE_BUF_SIZE;
795+ }
796+
797+ dma_sync_single_for_device(dev->hw->dev, page_phys, PAGE_SIZE,
798+ DMA_BIDIRECTIONAL);
799+ }
800+
801+ return 0;
802+}
803+
804+static void
805+mtk_wed_rx_page_free_buffer(struct mtk_wed_device *dev)
806+{
807+ struct mtk_rxbm_desc *desc = dev->rx_page_buf_ring.desc;
808+ struct dma_page_info *page_list = dev->rx_page_buf_ring.pages;
809+ int ring_size, page_idx;
810+ int i;
811+
812+ if (!page_list)
813+ return;
814+
815+ if (!desc)
816+ goto free_pagelist;
817+
818+ ring_size = dev->rx_page_buf_ring.pkt_nums;
819+
820+ for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_RX_PAGE_BUF_PER_PAGE) {
821+ void *page = page_list[page_idx].addr;
822+
823+ if (!page)
824+ break;
825+
826+ dma_unmap_page(dev->hw->dev, page_list[page_idx].addr_phys,
827+ PAGE_SIZE, DMA_BIDIRECTIONAL);
828+ __free_page(page);
829+ page_idx++;
830+ }
831+
developera60ce2b2023-06-16 13:07:18 +0800[diff] [blame]832+ dma_free_coherent(dev->hw->dev, dev->rx_page_buf_ring.size * sizeof(*desc),
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]833+ desc, dev->rx_page_buf_ring.desc_phys);
834+
835+free_pagelist:
836+ kfree(page_list);
837+}
838+
839 static void
840 mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, int scale)
841 {
842@@ -416,19 +618,25 @@ mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, int sca
843 static void
844 mtk_wed_free_tx_rings(struct mtk_wed_device *dev)
845 {
846- int i;
847+ int i, scale = dev->hw->version > 1 ? 2 : 1;
848
849 for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++)
850- mtk_wed_free_ring(dev, &dev->tx_ring[i], 1);
851+ if (!(dev->rx_ring[i].flags & MTK_WED_RING_CONFIGURED))
852+ mtk_wed_free_ring(dev, &dev->tx_ring[i], 1);
853+
854 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
855- mtk_wed_free_ring(dev, &dev->tx_wdma[i], dev->ver);
856+ if ((dev->rx_ring[i].flags & MTK_WED_RING_CONFIGURED))
857+ mtk_wed_free_ring(dev, &dev->tx_wdma[i], scale);
858 }
859
860 static void
861 mtk_wed_free_rx_rings(struct mtk_wed_device *dev)
862 {
863- mtk_wed_free_rx_bm(dev);
864+ mtk_wed_free_rx_buffer(dev);
865 mtk_wed_free_ring(dev, &dev->rro.rro_ring, 1);
866+
867+ if (dev->wlan.hwrro)
868+ mtk_wed_rx_page_free_buffer(dev);
869 }
870
871 static void
872@@ -437,7 +645,7 @@ mtk_wed_set_int(struct mtk_wed_device *dev, u32 irq_mask)
873 u32 wdma_mask;
874
875 wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));
876- if (dev->ver > MTK_WED_V1)
877+ if (mtk_wed_get_rx_capa(dev))
878 wdma_mask |= FIELD_PREP(MTK_WDMA_INT_MASK_TX_DONE,
879 GENMASK(1, 0));
880 /* wed control cr set */
881@@ -447,7 +655,7 @@ mtk_wed_set_int(struct mtk_wed_device *dev, u32 irq_mask)
882 MTK_WED_CTRL_WED_TX_BM_EN |
883 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
884
885- if (dev->ver == MTK_WED_V1) {
886+ if (dev->hw->version == 1) {
887 wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
888 MTK_WED_PCIE_INT_TRIGGER_STATUS);
889
890@@ -458,6 +666,8 @@ mtk_wed_set_int(struct mtk_wed_device *dev, u32 irq_mask)
891 wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
892 MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
893 } else {
894+ if (dev->hw->version == 3)
895+ wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_TKID_ALI_EN);
896
897 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
898 MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
899@@ -475,18 +685,20 @@ mtk_wed_set_int(struct mtk_wed_device *dev, u32 irq_mask)
900 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
901 dev->wlan.txfree_tbit));
902
903- wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
904- MTK_WED_WPDMA_INT_CTRL_RX0_EN |
905- MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
906- MTK_WED_WPDMA_INT_CTRL_RX1_EN |
907- MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
908- FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
909- dev->wlan.rx_tbit[0]) |
910- FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
911- dev->wlan.rx_tbit[1]));
912+ if (mtk_wed_get_rx_capa(dev))
913+ wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
914+ MTK_WED_WPDMA_INT_CTRL_RX0_EN |
915+ MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
916+ MTK_WED_WPDMA_INT_CTRL_RX1_EN |
917+ MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
918+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
919+ dev->wlan.rx_tbit[0]) |
920+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
921+ dev->wlan.rx_tbit[1]));
922 }
923+
924 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);
925- if (dev->ver == MTK_WED_V1) {
926+ if (dev->hw->version == 1) {
927 wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
928 } else {
929 wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
930@@ -506,6 +718,21 @@ mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en)
931 {
932 u32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
933
934+ switch (dev->hw->version) {
935+ case 1:
936+ mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
937+ break;
938+ case 2 :
939+ mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH2 |
940+ MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH2 |
941+ MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
942+ MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR;
943+ break;
944+ case 3:
945+ mask = MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT;
946+ break;
947+ }
948+
949 if (!dev->hw->num_flows)
950 mask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
951
952@@ -514,31 +741,86 @@ mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en)
953 }
954
955 static void
956-mtk_wed_set_512_support(struct mtk_wed_device *dev, bool en)
957+mtk_wed_pao_init(struct mtk_wed_device *dev)
958 {
959- if (en) {
960- wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
961- wed_w32(dev, MTK_WED_TXP_DW1,
962- FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0103));
963- } else {
964- wed_w32(dev, MTK_WED_TXP_DW1,
965- FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0100));
966- wed_clr(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
967+ struct mtk_wed_pao *pao = dev->hw->wed_pao;
968+ int i;
969+
970+ for (i = 0; i < 32; i++)
971+ wed_w32(dev, MTK_WED_PAO_HIFTXD_BASE_L(i),
972+ pao->hif_txd_phys[i]);
973+
974+ /* init all sta parameter */
975+ wed_w32(dev, MTK_WED_PAO_STA_INFO_INIT, MTK_WED_PAO_STA_RMVL |
976+ MTK_WED_PAO_STA_WTBL_HDRT_MODE |
977+ FIELD_PREP(MTK_WED_PAO_STA_MAX_AMSDU_LEN,
978+ dev->wlan.max_amsdu_len >> 8) |
979+ FIELD_PREP(MTK_WED_PAO_STA_MAX_AMSDU_NUM,
980+ dev->wlan.max_amsdu_nums));
981+
982+ wed_w32(dev, MTK_WED_PAO_STA_INFO, MTK_WED_PAO_STA_INFO_DO_INIT);
983+
984+ if (mtk_wed_poll_busy(dev, MTK_WED_PAO_STA_INFO,
985+ MTK_WED_PAO_STA_INFO_DO_INIT)) {
986+ dev_err(dev->hw->dev, "mtk_wed%d: pao init failed!\n",
987+ dev->hw->index);
988+ return;
989 }
990+
991+ /* init pao txd src */
992+ wed_set(dev, MTK_WED_PAO_HIFTXD_CFG,
993+ FIELD_PREP(MTK_WED_PAO_HIFTXD_SRC, dev->hw->index));
994+
995+ /* init qmem */
996+ wed_set(dev, MTK_WED_PAO_PSE, MTK_WED_PAO_PSE_RESET);
997+ if (mtk_wed_poll_busy(dev, MTK_WED_PAO_MON_QMEM_STS1, BIT(29))) {
998+ pr_info("%s: init pao qmem fail\n", __func__);
999+ return;
1000+ }
1001+
1002+ /* eagle E1 PCIE1 tx ring 22 flow control issue */
1003+ if (dev->wlan.chip_id == 0x7991) {
1004+ wed_clr(dev, MTK_WED_PAO_AMSDU_FIFO,
1005+ MTK_WED_PAO_AMSDU_IS_PRIOR0_RING);
1006+ }
1007+
1008+ wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_PAO_EN);
1009+
1010+ return;
1011 }
1012
1013-static void
1014-mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev, int idx)
1015+static int
1016+mtk_wed_hwrro_init(struct mtk_wed_device *dev)
1017 {
1018-#define MTK_WFMDA_RX_DMA_EN BIT(2)
1019+ if (!mtk_wed_get_rx_capa(dev))
1020+ return 0;
1021+
1022+ wed_set(dev, MTK_WED_RRO_PG_BM_RX_DMAM,
1023+ FIELD_PREP(MTK_WED_RRO_PG_BM_RX_SDL0, 128));
1024+
1025+ wed_w32(dev, MTK_WED_RRO_PG_BM_BASE,
1026+ dev->rx_page_buf_ring.desc_phys);
1027+
1028+ wed_w32(dev, MTK_WED_RRO_PG_BM_INIT_PTR,
1029+ MTK_WED_RRO_PG_BM_INIT_SW_TAIL_IDX |
1030+ FIELD_PREP(MTK_WED_RRO_PG_BM_SW_TAIL_IDX,
1031+ MTK_WED_RX_PG_BM_CNT));
1032+
1033+ /* enable rx_page_bm to fetch dmad */
1034+ wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_PG_BM_EN);
1035+
1036+ return 0;
1037+}
1038
1039+static int
1040+mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev,
1041+ struct mtk_wed_ring *ring)
1042+{
1043 int timeout = 3;
1044- u32 cur_idx, regs;
1045+ u32 cur_idx;
1046
1047 do {
1048- regs = MTK_WED_WPDMA_RING_RX_DATA(idx) +
1049- MTK_WED_RING_OFS_CPU_IDX;
1050- cur_idx = wed_r32(dev, regs);
1051+ cur_idx = readl(ring->wpdma + MTK_WED_RING_OFS_CPU_IDX);
1052 if (cur_idx == MTK_WED_RX_RING_SIZE - 1)
1053 break;
1054
1055@@ -546,70 +828,133 @@ mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev, int idx)
1056 timeout--;
1057 } while (timeout > 0);
1058
1059- if (timeout) {
1060- unsigned int val;
1061+ return timeout;
1062+}
1063
1064- val = wifi_r32(dev, dev->wlan.wpdma_rx_glo -
1065- dev->wlan.phy_base);
1066- val |= MTK_WFMDA_RX_DMA_EN;
1067
1068- wifi_w32(dev, dev->wlan.wpdma_rx_glo -
1069- dev->wlan.phy_base, val);
1070+static void
1071+mtk_wed_set_512_support(struct mtk_wed_device *dev, bool en)
1072+{
1073+ if (en) {
1074+ wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
1075+ wed_w32(dev, MTK_WED_TXP_DW1,
1076+ FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0103));
1077 } else {
1078- dev_err(dev->hw->dev, "mtk_wed%d: rx(%d) dma enable failed!\n",
1079- dev->hw->index, idx);
1080+ wed_w32(dev, MTK_WED_TXP_DW1,
1081+ FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0100));
1082+ wed_clr(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
1083 }
1084 }
1085
1086 static void
1087 mtk_wed_dma_enable(struct mtk_wed_device *dev)
1088 {
1089- wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
1090- MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
1091+#define MTK_WFMDA_RX_DMA_EN BIT(2)
1092+
1093+ if (dev->hw->version == 1)
1094+ wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
1095+ MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
1096
1097 wed_set(dev, MTK_WED_GLO_CFG,
1098 MTK_WED_GLO_CFG_TX_DMA_EN |
1099 MTK_WED_GLO_CFG_RX_DMA_EN);
1100+
1101+ wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG,
1102+ FIELD_PREP(MTK_WED_WDMA_RX_PREF_BURST_SIZE, 0x10) |
1103+ FIELD_PREP(MTK_WED_WDMA_RX_PREF_LOW_THRES, 0x8));
1104+ wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
1105+ MTK_WED_WDMA_RX_PREF_DDONE2_EN);
1106+
1107+ wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG, MTK_WED_WDMA_RX_PREF_EN);
1108+
1109 wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
1110 MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
1111- MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
1112+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN |
1113+ MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR);
1114 wed_set(dev, MTK_WED_WDMA_GLO_CFG,
1115 MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
1116
1117 wdma_set(dev, MTK_WDMA_GLO_CFG,
1118- MTK_WDMA_GLO_CFG_TX_DMA_EN |
1119+ MTK_WDMA_GLO_CFG_TX_DMA_EN /*|
1120 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
1121- MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
1122+ MTK_WDMA_GLO_CFG_RX_INFO2_PRERES*/);
1123
1124- if (dev->ver == MTK_WED_V1) {
1125+ if (dev->hw->version == 1) {
1126 wdma_set(dev, MTK_WDMA_GLO_CFG,
1127 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
1128 } else {
1129 int idx = 0;
1130
1131- wed_set(dev, MTK_WED_WPDMA_CTRL,
1132- MTK_WED_WPDMA_CTRL_SDL1_FIXED);
1133-
1134- wed_set(dev, MTK_WED_WDMA_GLO_CFG,
1135- MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
1136- MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
1137+ if (mtk_wed_get_rx_capa(dev))
1138+ wed_set(dev, MTK_WED_WDMA_GLO_CFG,
1139+ MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
1140+ MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
1141
1142 wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
1143 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
1144 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
1145
1146+ if (dev->hw->version == 3) {
1147+ wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
1148+ MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST);
1149+ wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
1150+ MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK |
1151+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK |
1152+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4);
1153+
1154+ wdma_set(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
1155+ //wdma_w32(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN);
1156+ if (mtk_wed_get_rx_capa(dev)) {
1157+ wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
1158+ MTK_WED_WPDMA_RX_D_PREF_EN |
1159+ FIELD_PREP(MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE, 0x10) |
1160+ FIELD_PREP(MTK_WED_WPDMA_RX_D_PREF_LOW_THRES, 0x8));
1161+
1162+ wed_set(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_RX_D_DRV_EN);
1163+
1164+ wdma_set(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN);
1165+
1166+ wdma_set(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
1167+ }
1168+ }
1169+
1170 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
1171 MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
1172 MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
1173
1174+ if (!mtk_wed_get_rx_capa(dev))
1175+ return;
1176+
1177+ wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RXD_READ_LEN);
1178 wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
1179 MTK_WED_WPDMA_RX_D_RX_DRV_EN |
1180 FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
1181 FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
1182 0x2));
1183
1184- for (idx = 0; idx < dev->hw->ring_num; idx++)
1185- mtk_wed_check_wfdma_rx_fill(dev, idx);
1186+ for (idx = 0; idx < dev->hw->ring_num; idx++) {
1187+ struct mtk_wed_ring *ring = &dev->rx_ring[idx];
1188+
1189+ if(!(ring->flags & MTK_WED_RING_CONFIGURED))
1190+ continue;
1191+
1192+ if(mtk_wed_check_wfdma_rx_fill(dev, ring)) {
1193+ unsigned int val;
1194+
1195+ val = wifi_r32(dev, dev->wlan.wpdma_rx_glo -
1196+ dev->wlan.phy_base);
1197+ val |= MTK_WFMDA_RX_DMA_EN;
1198+
1199+ wifi_w32(dev, dev->wlan.wpdma_rx_glo -
1200+ dev->wlan.phy_base, val);
1201+
1202+ dev_err(dev->hw->dev, "mtk_wed%d: rx(%d) dma enable successful!\n",
1203+ dev->hw->index, idx);
1204+ } else {
1205+ dev_err(dev->hw->dev, "mtk_wed%d: rx(%d) dma enable failed!\n",
1206+ dev->hw->index, idx);
1207+ }
1208+ }
1209 }
1210 }
1211
1212@@ -644,15 +989,20 @@ mtk_wed_dma_disable(struct mtk_wed_device *dev)
1213 MTK_WED_WPDMA_RX_D_RX_DRV_EN);
1214 wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
1215 MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
1216- }
1217
1218- mtk_wed_set_512_support(dev, false);
1219+ if (dev->hw->version == 3 && mtk_wed_get_rx_capa(dev)) {
1220+ wdma_clr(dev, MTK_WDMA_PREF_TX_CFG,
1221+ MTK_WDMA_PREF_TX_CFG_PREF_EN);
1222+ wdma_clr(dev, MTK_WDMA_PREF_RX_CFG,
1223+ MTK_WDMA_PREF_RX_CFG_PREF_EN);
1224+ }
1225+ }
1226 }
1227
1228 static void
1229 mtk_wed_stop(struct mtk_wed_device *dev)
1230 {
1231- if (dev->ver > MTK_WED_V1) {
1232+ if (mtk_wed_get_rx_capa(dev)) {
1233 wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
1234 wed_w32(dev, MTK_WED_EXT_INT_MASK2, 0);
1235 }
1236@@ -677,13 +1027,21 @@ mtk_wed_deinit(struct mtk_wed_device *dev)
1237 MTK_WED_CTRL_WED_TX_BM_EN |
1238 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
1239
1240- if (dev->hw->ver == 1)
1241+ if (dev->hw->version == 1)
1242 return;
1243
1244 wed_clr(dev, MTK_WED_CTRL,
1245 MTK_WED_CTRL_RX_ROUTE_QM_EN |
1246 MTK_WED_CTRL_WED_RX_BM_EN |
1247 MTK_WED_CTRL_RX_RRO_QM_EN);
1248+
1249+ if (dev->hw->version == 3) {
1250+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_PAO_EN);
1251+ wed_clr(dev, MTK_WED_RESET, MTK_WED_RESET_TX_PAO);
1252+ wed_clr(dev, MTK_WED_PCIE_INT_CTRL,
1253+ MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
1254+ MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER);
1255+ }
1256 }
1257
1258 static void
1259@@ -702,9 +1060,9 @@ mtk_wed_detach(struct mtk_wed_device *dev)
1260
1261 mtk_wdma_tx_reset(dev);
1262
1263- mtk_wed_free_buffer(dev);
1264+ mtk_wed_free_tx_buffer(dev);
1265 mtk_wed_free_tx_rings(dev);
1266- if (dev->ver > MTK_WED_V1) {
1267+ if (mtk_wed_get_rx_capa(dev)) {
1268 mtk_wed_wo_reset(dev);
1269 mtk_wed_free_rx_rings(dev);
1270 mtk_wed_wo_exit(hw);
1271@@ -728,73 +1086,97 @@ mtk_wed_detach(struct mtk_wed_device *dev)
1272 mutex_unlock(&hw_lock);
1273 }
1274
1275+#define IRQ_MASK_APMCU 0x1000301c
1276 static void
1277 mtk_wed_bus_init(struct mtk_wed_device *dev)
1278 {
1279-#define PCIE_BASE_ADDR0 0x11280000
1280+ switch (dev->wlan.bus_type) {
1281+ case MTK_WED_BUS_PCIE: {
1282+ struct device_node *np = dev->hw->eth->dev->of_node;
1283+ struct regmap *regs;
1284+ unsigned long addr;
1285+ u32 value;
1286
1287- if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
1288- struct device_node *node;
1289- void __iomem * base_addr;
1290- u32 value = 0;
1291+ if (dev->hw->version == 2) {
1292+ regs = syscon_regmap_lookup_by_phandle(np,
1293+ "mediatek,wed-pcie");
1294+ if (IS_ERR(regs))
1295+ break;
1296
1297- node = of_parse_phandle(dev->hw->node, "mediatek,wed_pcie", 0);
1298- if (!node) {
1299- pr_err("%s: no wed_pcie node\n", __func__);
1300- return;
1301+ regmap_update_bits(regs, 0, BIT(0), BIT(0));
1302 }
1303
1304- base_addr = of_iomap(node, 0);
1305-
1306- value = readl(base_addr);
1307- value |= BIT(0);
1308- writel(value, base_addr);
1309+ if (dev->wlan.msi) {
1310+ wed_w32(dev, MTK_WED_PCIE_CFG_INTM, dev->hw->pci_base| 0xc08);
1311+ wed_w32(dev, MTK_WED_PCIE_CFG_BASE, dev->hw->pci_base | 0xc04);
1312+ wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(8));
1313+ } else {
1314+ wed_w32(dev, MTK_WED_PCIE_CFG_INTM, dev->hw->pci_base | 0x180);
1315+ wed_w32(dev, MTK_WED_PCIE_CFG_BASE, dev->hw->pci_base | 0x184);
1316+ wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
1317+ }
1318
1319- wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
1320- FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
1321+ if (dev->hw->version < 3 || dev->hw->index) {
1322+ wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
1323+ FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
1324+ } else {
1325+ /* set mask apmcu */
1326+ addr = (unsigned long)ioremap(IRQ_MASK_APMCU, 4);
1327+ value = readl((void *)addr);
1328+ value |= 0x7;
1329+ writel(value, (void *)addr);
1330+ iounmap((void *)addr);
1331+ }
1332
1333 /* pcie interrupt control: pola/source selection */
1334 wed_set(dev, MTK_WED_PCIE_INT_CTRL,
1335 MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
1336- FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1));
1337- wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
1338+ MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER |
1339+ FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, dev->hw->index));
1340
1341- value = wed_r32(dev, MTK_WED_PCIE_CFG_INTM);
1342- value = wed_r32(dev, MTK_WED_PCIE_CFG_BASE);
1343- wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180);
1344- wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184);
1345-
1346- value = wed_r32(dev, MTK_WED_PCIE_CFG_INTM);
1347- value = wed_r32(dev, MTK_WED_PCIE_CFG_BASE);
1348-
1349- wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
1350- wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER);
1351-
1352- /* pola setting */
1353- value = wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
1354- wed_set(dev, MTK_WED_PCIE_INT_CTRL,
1355- MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA);
1356- } else if (dev->wlan.bus_type == MTK_WED_BUS_AXI) {
1357+ break;
1358+ }
1359+ case MTK_WED_BUS_AXI:
1360 wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
1361 MTK_WED_WPDMA_INT_CTRL_SIG_SRC |
1362 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_SRC_SEL, 0));
1363+ break;
1364+ default:
1365+ break;
1366 }
1367+
1368 return;
1369 }
1370
1371 static void
1372 mtk_wed_set_wpdma(struct mtk_wed_device *dev)
1373 {
1374- if (dev->ver > MTK_WED_V1) {
1375+ if (dev->hw->version == 1) {
1376+ wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
1377+ } else {
1378+ mtk_wed_bus_init(dev);
1379+
1380 wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
1381 wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
1382- wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
1383+ wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
1384 wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
1385
1386- wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
1387- wed_w32(dev, MTK_WED_WPDMA_RX_RING, dev->wlan.wpdma_rx);
1388- } else {
1389- wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
1390+ if (mtk_wed_get_rx_capa(dev)) {
1391+ int i;
1392+
1393+ wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
1394+ wed_w32(dev, MTK_WED_WPDMA_RX_RING0, dev->wlan.wpdma_rx);
1395+ wed_w32(dev, MTK_WED_WPDMA_RX_RING1, dev->wlan.wpdma_rx + 0x10);
1396+
1397+ if (dev->wlan.hwrro) {
1398+ wed_w32(dev, MTK_WED_RRO_RX_D_CFG(0), dev->wlan.wpdma_rx_rro[0]);
1399+ wed_w32(dev, MTK_WED_RRO_RX_D_CFG(1), dev->wlan.wpdma_rx_rro[1]);
1400+ for (i = 0; i < MTK_WED_RX_PAGE_QUEUES; i++) {
1401+ wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING_CFG(i),
1402+ dev->wlan.wpdma_rx_pg + i * 0x10);
1403+ }
1404+ }
1405+ }
1406 }
1407 }
1408
1409@@ -806,21 +1188,25 @@ mtk_wed_hw_init_early(struct mtk_wed_device *dev)
1410 mtk_wed_deinit(dev);
1411 mtk_wed_reset(dev, MTK_WED_RESET_WED);
1412
1413- if (dev->ver > MTK_WED_V1)
1414- mtk_wed_bus_init(dev);
1415-
1416 mtk_wed_set_wpdma(dev);
1417
1418- mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE |
1419- MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
1420- MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
1421- set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) |
1422- MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |
1423- MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
1424+ if (dev->hw->version == 3) {
1425+ mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE;
1426+ set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2);
1427+ } else {
1428+ mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE |
1429+ MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
1430+ MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
1431+ set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) |
1432+ MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |
1433+ MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
1434+ }
1435+
1436 wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
1437
1438- if (dev->ver == MTK_WED_V1) {
1439+ if (dev->hw->version == 1) {
1440 u32 offset;
1441+
1442 offset = dev->hw->index ? 0x04000400 : 0;
1443 wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);
1444 wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset);
1445@@ -907,11 +1293,16 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_device *dev)
1446 } while (1);
1447
1448 /* configure RX_ROUTE_QM */
1449- wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
1450- wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_TXDMAD_FPORT);
1451- wed_set(dev, MTK_WED_RTQM_GLO_CFG,
1452- FIELD_PREP(MTK_WED_RTQM_TXDMAD_FPORT, 0x3 + dev->hw->index));
1453- wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
1454+ if (dev->hw->version == 2) {
1455+ wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
1456+ wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_TXDMAD_FPORT);
1457+ wed_set(dev, MTK_WED_RTQM_GLO_CFG,
1458+ FIELD_PREP(MTK_WED_RTQM_TXDMAD_FPORT, 0x3 + dev->hw->index));
1459+ wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
1460+ } else {
1461+ wed_set(dev, MTK_WED_RTQM_ENQ_CFG0,
1462+ FIELD_PREP(MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT, 0x3 + dev->hw->index));
1463+ }
1464
1465 /* enable RX_ROUTE_QM */
1466 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
1467@@ -920,23 +1311,45 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_device *dev)
1468 static void
1469 mtk_wed_tx_hw_init(struct mtk_wed_device *dev)
1470 {
1471- int size = dev->buf_ring.size;
1472+ int size = dev->wlan.nbuf;
1473 int rev_size = MTK_WED_TX_RING_SIZE / 2;
1474- int thr = 1;
1475+ int thr_lo = 1, thr_hi = 1;
1476
1477- if (dev->ver > MTK_WED_V1) {
1478+ if (dev->hw->version == 1) {
1479+ wed_w32(dev, MTK_WED_TX_BM_CTRL,
1480+ MTK_WED_TX_BM_CTRL_PAUSE |
1481+ FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, size / 128) |
1482+ FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, rev_size / 128));
1483+ } else {
1484 size = MTK_WED_WDMA_RING_SIZE * ARRAY_SIZE(dev->tx_wdma) +
1485- dev->buf_ring.size;
1486+ dev->tx_buf_ring.size;
1487 rev_size = size;
1488- thr = 0;
1489+ thr_lo = 0;
1490+ thr_hi = MTK_WED_TX_BM_DYN_THR_HI;
1491+
1492+ wed_w32(dev, MTK_WED_TX_TKID_CTRL,
1493+ MTK_WED_TX_TKID_CTRL_PAUSE |
1494+ FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM,
1495+ size / 128) |
1496+ FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
1497+ size / 128));
1498+
1499+ /* return SKBID + SDP back to bm */
1500+ if (dev->ver == 3) {
1501+ wed_set(dev, MTK_WED_TX_TKID_CTRL,
1502+ MTK_WED_TX_TKID_CTRL_FREE_FORMAT);
1503+ size = dev->wlan.nbuf;
1504+ rev_size = size;
1505+ } else {
1506+ wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
1507+ FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
1508+ MTK_WED_TX_TKID_DYN_THR_HI);
1509+ }
1510 }
1511
1512- wed_w32(dev, MTK_WED_TX_BM_CTRL,
1513- MTK_WED_TX_BM_CTRL_PAUSE |
1514- FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, size / 128) |
1515- FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, rev_size / 128));
1516+ mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
1517
1518- wed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys);
1519+ wed_w32(dev, MTK_WED_TX_BM_BASE, dev->tx_buf_ring.desc_phys);
1520
1521 wed_w32(dev, MTK_WED_TX_BM_TKID,
1522 FIELD_PREP(MTK_WED_TX_BM_TKID_START,
1523@@ -946,25 +1359,44 @@ mtk_wed_tx_hw_init(struct mtk_wed_device *dev)
1524
1525 wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
1526
1527- wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
1528- FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, thr) |
1529- MTK_WED_TX_BM_DYN_THR_HI);
1530+ if (dev->hw->version < 3)
1531+ wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
1532+ FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, thr_lo) |
1533+ FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, thr_hi));
1534+ else {
1535+ /* change to new bm */
1536+ wed_w32(dev, MTK_WED_TX_BM_INIT_PTR, dev->tx_buf_ring.pkt_nums |
1537+ MTK_WED_TX_BM_INIT_SW_TAIL_IDX);
1538+ wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_LEGACY_EN);
1539+ }
1540
1541- if (dev->ver > MTK_WED_V1) {
1542+ if (dev->hw->version != 1) {
1543 wed_w32(dev, MTK_WED_TX_TKID_CTRL,
1544 MTK_WED_TX_TKID_CTRL_PAUSE |
1545 FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM,
1546- dev->buf_ring.size / 128) |
1547+ size / 128) |
1548 FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
1549- dev->buf_ring.size / 128));
1550- wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
1551- FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
1552- MTK_WED_TX_TKID_DYN_THR_HI);
1553+ size / 128));
1554+
1555+ /* return SKBID + SDP back to bm */
1556+ if (dev->ver == 3)
1557+ wed_set(dev, MTK_WED_TX_TKID_CTRL,
1558+ MTK_WED_TX_TKID_CTRL_FREE_FORMAT);
1559+ else
1560+ wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
1561+ FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
1562+ MTK_WED_TX_TKID_DYN_THR_HI);
1563 }
1564- mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
1565+ wed_w32(dev, MTK_WED_TX_BM_TKID,
1566+ FIELD_PREP(MTK_WED_TX_BM_TKID_START,
1567+ dev->wlan.token_start) |
1568+ FIELD_PREP(MTK_WED_TX_BM_TKID_END,
1569+ dev->wlan.token_start + dev->wlan.nbuf - 1));
1570
1571+ wed_w32(dev, MTK_WED_TX_BM_INIT_PTR, dev->tx_buf_ring.pkt_nums |
1572+ MTK_WED_TX_BM_INIT_SW_TAIL_IDX);
1573 wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
1574- if (dev->ver > MTK_WED_V1)
1575+ if (dev->hw->version != 1)
1576 wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
1577 }
1578
1579@@ -977,7 +1409,26 @@ mtk_wed_rx_hw_init(struct mtk_wed_device *dev)
1580
1581 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
1582
1583+ /* reset prefetch index of ring */
1584+ wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX,
1585+ MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
1586+ wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX,
1587+ MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
1588+
1589+ wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX,
1590+ MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
1591+ wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX,
1592+ MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
1593+
1594+ /* reset prefetch FIFO of ring */
1595+ wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG,
1596+ MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR |
1597+ MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR);
1598+ wed_w32(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG, 0);
1599+
1600 mtk_wed_rx_bm_hw_init(dev);
1601+ if (dev->wlan.hwrro)
1602+ mtk_wed_hwrro_init(dev);
1603 mtk_wed_rro_hw_init(dev);
1604 mtk_wed_route_qm_hw_init(dev);
1605 }
1606@@ -991,7 +1442,7 @@ mtk_wed_hw_init(struct mtk_wed_device *dev)
1607 dev->init_done = true;
1608 mtk_wed_set_ext_int(dev, false);
1609 mtk_wed_tx_hw_init(dev);
1610- if (dev->ver > MTK_WED_V1)
1611+ if (mtk_wed_get_rx_capa(dev))
1612 mtk_wed_rx_hw_init(dev);
1613 }
1614
1615@@ -1015,26 +1466,6 @@ mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size, int scale, bool tx)
1616 }
1617 }
1618
1619-static u32
1620-mtk_wed_check_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
1621-{
1622- if (wed_r32(dev, reg) & mask)
1623- return true;
1624-
1625- return false;
1626-}
1627-
1628-static int
1629-mtk_wed_poll_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
1630-{
1631- int sleep = 1000;
1632- int timeout = 100 * sleep;
1633- u32 val;
1634-
1635- return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
1636- timeout, false, dev, reg, mask);
1637-}
1638-
1639 static void
1640 mtk_wed_rx_reset(struct mtk_wed_device *dev)
1641 {
1642@@ -1133,7 +1564,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *dev)
1643 mtk_wed_ring_reset(desc, MTK_WED_RX_RING_SIZE, 1, false);
1644 }
1645
1646- mtk_wed_free_rx_bm(dev);
1647+ mtk_wed_free_rx_buffer(dev);
1648 }
1649
1650
1651@@ -1271,12 +1702,15 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev,
1652 int idx, int size, bool reset)
1653 {
1654 struct mtk_wed_ring *wdma = &dev->tx_wdma[idx];
1655+ int scale = dev->hw->version > 1 ? 2 : 1;
1656
1657 if(!reset)
1658 if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
1659- dev->ver, true))
1660+ scale, true))
1661 return -ENOMEM;
1662
1663+ wdma->flags |= MTK_WED_RING_CONFIGURED;
1664+
1665 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
1666 wdma->desc_phys);
1667 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,
1668@@ -1296,12 +1730,31 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev,
1669 int idx, int size, bool reset)
1670 {
1671 struct mtk_wed_ring *wdma = &dev->rx_wdma[idx];
1672+ int scale = dev->hw->version > 1 ? 2 : 1;
1673
1674 if (!reset)
1675 if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
1676- dev->ver, true))
1677+ scale, true))
1678 return -ENOMEM;
1679
1680+ if (dev->hw->version == 3) {
1681+ struct mtk_wdma_desc *desc = wdma->desc;
1682+ int i;
1683+
1684+ for (i = 0; i < MTK_WED_WDMA_RING_SIZE; i++) {
1685+ desc->buf0 = 0;
1686+ desc->ctrl = MTK_WDMA_DESC_CTRL_DMA_DONE;
1687+ desc->buf1 = 0;
1688+ desc->info = MTK_WDMA_TXD0_DESC_INFO_DMA_DONE;
1689+ desc++;
1690+ desc->buf0 = 0;
1691+ desc->ctrl = MTK_WDMA_DESC_CTRL_DMA_DONE;
1692+ desc->buf1 = 0;
1693+ desc->info = MTK_WDMA_TXD1_DESC_INFO_DMA_DONE;
1694+ desc++;
1695+ }
1696+ }
1697+
1698 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
1699 wdma->desc_phys);
1700 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
1701@@ -1312,7 +1765,7 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev,
1702 MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_DMA_IDX, 0);
1703 if (reset)
1704 mtk_wed_ring_reset(wdma->desc, MTK_WED_WDMA_RING_SIZE,
1705- dev->ver, true);
1706+ scale, true);
1707 if (idx == 0) {
1708 wed_w32(dev, MTK_WED_WDMA_RING_TX
1709 + MTK_WED_RING_OFS_BASE, wdma->desc_phys);
1710@@ -1395,7 +1848,7 @@ mtk_wed_send_msg(struct mtk_wed_device *dev, int cmd_id, void *data, int len)
1711 {
1712 struct mtk_wed_wo *wo = dev->hw->wed_wo;
1713
1714- if (dev->ver == MTK_WED_V1)
1715+ if (!mtk_wed_get_rx_capa(dev))
1716 return 0;
1717
1718 return mtk_wed_mcu_send_msg(wo, MODULE_ID_WO, cmd_id, data, len, true);
1719@@ -1420,13 +1873,87 @@ mtk_wed_ppe_check(struct mtk_wed_device *dev, struct sk_buff *skb,
1720 }
1721 }
1722
1723+static void
1724+mtk_wed_start_hwrro(struct mtk_wed_device *dev, u32 irq_mask)
1725+{
1726+ int idx, ret;
1727+
1728+ wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
1729+ wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
1730+
1731+ if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hwrro)
1732+ return;
1733+
1734+ wed_set(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_MSDU_PG_DRV_CLR);
1735+ wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG, MTK_WED_RRO_MSDU_PG_DRV_CLR);
1736+
1737+ wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RRO_RX,
1738+ MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN |
1739+ MTK_WED_WPDMA_INT_CTRL_RRO_RX0_CLR |
1740+ MTK_WED_WPDMA_INT_CTRL_RRO_RX1_EN |
1741+ MTK_WED_WPDMA_INT_CTRL_RRO_RX1_CLR |
1742+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_RX0_DONE_TRIG,
1743+ dev->wlan.rro_rx_tbit[0]) |
1744+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_RX1_DONE_TRIG,
1745+ dev->wlan.rro_rx_tbit[1]));
1746+
1747+ wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG,
1748+ MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN |
1749+ MTK_WED_WPDMA_INT_CTRL_RRO_PG0_CLR |
1750+ MTK_WED_WPDMA_INT_CTRL_RRO_PG1_EN |
1751+ MTK_WED_WPDMA_INT_CTRL_RRO_PG1_CLR |
1752+ MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN |
1753+ MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR |
1754+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_PG0_DONE_TRIG,
1755+ dev->wlan.rx_pg_tbit[0]) |
1756+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_PG1_DONE_TRIG,
1757+ dev->wlan.rx_pg_tbit[1])|
1758+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG,
1759+ dev->wlan.rx_pg_tbit[2]));
1760+
1761+ /*
1762+ * RRO_MSDU_PG_RING2_CFG1_FLD_DRV_EN should be enabled after
1763+ * WM FWDL completed, otherwise RRO_MSDU_PG ring may broken
1764+ */
1765+ wed_set(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG, MTK_WED_RRO_MSDU_PG_DRV_EN);
1766+
1767+ for (idx = 0; idx < MTK_WED_RX_QUEUES; idx++) {
1768+ struct mtk_wed_ring *ring = &dev->rx_rro_ring[idx];
1769+
1770+ if(!(ring->flags & MTK_WED_RING_CONFIGURED))
1771+ continue;
1772+
1773+ ret = mtk_wed_check_wfdma_rx_fill(dev, ring);
1774+ if (!ret)
1775+ dev_err(dev->hw->dev, "mtk_wed%d: rx_rro_ring(%d) init failed!\n",
1776+ dev->hw->index, idx);
1777+ }
1778+
1779+ for (idx = 0; idx < MTK_WED_RX_PAGE_QUEUES; idx++){
1780+ struct mtk_wed_ring *ring = &dev->rx_page_ring[idx];
1781+ if(!(ring->flags & MTK_WED_RING_CONFIGURED))
1782+ continue;
1783+
1784+ ret = mtk_wed_check_wfdma_rx_fill(dev, ring);
1785+ if (!ret)
1786+ dev_err(dev->hw->dev, "mtk_wed%d: rx_page_ring(%d) init failed!\n",
1787+ dev->hw->index, idx);
1788+ }
1789+}
1790+
1791 static void
1792 mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
1793 {
1794 int i, ret;
1795
1796- if (dev->ver > MTK_WED_V1)
1797- ret = mtk_wed_rx_bm_alloc(dev);
1798+ if (mtk_wed_get_rx_capa(dev)) {
1799+ ret = mtk_wed_rx_buffer_alloc(dev);
1800+ if (ret)
1801+ return;
1802+
1803+ if (dev->wlan.hwrro)
1804+ mtk_wed_rx_page_buffer_alloc(dev);
1805+ }
1806
1807 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
1808 if (!dev->tx_wdma[i].desc)
1809@@ -1437,7 +1964,7 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
1810 mtk_wed_set_int(dev, irq_mask);
1811 mtk_wed_set_ext_int(dev, true);
1812
1813- if (dev->ver == MTK_WED_V1) {
1814+ if (dev->hw->version == 1) {
1815 u32 val;
1816
1817 val = dev->wlan.wpdma_phys |
1818@@ -1448,33 +1975,52 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
1819 val |= BIT(1);
1820 val |= BIT(0);
1821 regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
1822- } else {
1823+ } else if (mtk_wed_get_rx_capa(dev)) {
1824 /* driver set mid ready and only once */
1825 wed_w32(dev, MTK_WED_EXT_INT_MASK1,
1826 MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
1827 wed_w32(dev, MTK_WED_EXT_INT_MASK2,
1828 MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
1829+ if (dev->hw->version == 3)
1830+ wed_w32(dev, MTK_WED_EXT_INT_MASK3,
1831+ MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
1832
1833 wed_r32(dev, MTK_WED_EXT_INT_MASK1);
1834 wed_r32(dev, MTK_WED_EXT_INT_MASK2);
1835+ if (dev->hw->version == 3)
1836+ wed_r32(dev, MTK_WED_EXT_INT_MASK3);
1837
1838 ret = mtk_wed_rro_cfg(dev);
1839 if (ret)
1840 return;
1841 }
1842- mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
1843+
1844+ if (dev->hw->version == 2)
1845+ mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
1846+ else if (dev->hw->version == 3)
1847+ mtk_wed_pao_init(dev);
1848
1849 mtk_wed_dma_enable(dev);
1850 dev->running = true;
1851 }
1852
1853+static int
1854+mtk_wed_get_pci_base(struct mtk_wed_device *dev)
1855+{
1856+ if (dev->hw->index == 0)
1857+ return MTK_WED_PCIE_BASE0;
1858+ else if (dev->hw->index == 1)
1859+ return MTK_WED_PCIE_BASE1;
1860+ else
1861+ return MTK_WED_PCIE_BASE2;
1862+}
1863+
1864 static int
1865 mtk_wed_attach(struct mtk_wed_device *dev)
1866 __releases(RCU)
1867 {
1868 struct mtk_wed_hw *hw;
1869 struct device *device;
1870- u16 ver;
1871 int ret = 0;
1872
1873 RCU_LOCKDEP_WARN(!rcu_read_lock_held(),
1874@@ -1494,34 +2040,30 @@ mtk_wed_attach(struct mtk_wed_device *dev)
1875 goto out;
1876 }
1877
1878- device = dev->wlan.bus_type == MTK_WED_BUS_PCIE
1879- ? &dev->wlan.pci_dev->dev
1880- : &dev->wlan.platform_dev->dev;
1881+ device = dev->wlan.bus_type == MTK_WED_BUS_PCIE ?
1882+ &dev->wlan.pci_dev->dev
1883+ : &dev->wlan.platform_dev->dev;
1884 dev_info(device, "attaching wed device %d version %d\n",
1885- hw->index, hw->ver);
1886+ hw->index, hw->version);
1887
1888 dev->hw = hw;
1889 dev->dev = hw->dev;
1890 dev->irq = hw->irq;
1891 dev->wdma_idx = hw->index;
1892+ dev->ver = hw->version;
1893+
1894+ if (dev->hw->version == 3)
1895+ dev->hw->pci_base = mtk_wed_get_pci_base(dev);
1896
1897 if (hw->eth->dma_dev == hw->eth->dev &&
1898 of_dma_is_coherent(hw->eth->dev->of_node))
1899 mtk_eth_set_dma_device(hw->eth, hw->dev);
1900
1901- dev->ver = FIELD_GET(MTK_WED_REV_ID_MAJOR,
1902- wed_r32(dev, MTK_WED_REV_ID));
1903- if (dev->ver > MTK_WED_V1)
1904- ver = FIELD_GET(MTK_WED_REV_ID_MINOR,
1905- wed_r32(dev, MTK_WED_REV_ID));
1906-
1907- dev->rev_id = ((dev->ver << 28) | ver << 16);
1908-
1909- ret = mtk_wed_buffer_alloc(dev);
1910+ ret = mtk_wed_tx_buffer_alloc(dev);
1911 if (ret)
1912 goto error;
1913
1914- if (dev->ver > MTK_WED_V1) {
1915+ if (mtk_wed_get_rx_capa(dev)) {
1916 ret = mtk_wed_rro_alloc(dev);
1917 if (ret)
1918 goto error;
1919@@ -1533,15 +2075,20 @@ mtk_wed_attach(struct mtk_wed_device *dev)
1920 init_completion(&dev->wlan_reset_done);
1921 atomic_set(&dev->fe_reset, 0);
1922
1923- if (dev->ver == MTK_WED_V1)
1924+ if (dev->hw->version != 1)
1925+ dev->rev_id = wed_r32(dev, MTK_WED_REV_ID);
1926+ else
1927 regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
1928 BIT(hw->index), 0);
1929- else
1930+
1931+ if (mtk_wed_get_rx_capa(dev))
1932 ret = mtk_wed_wo_init(hw);
1933
1934 error:
1935- if (ret)
1936+ if (ret) {
1937+ pr_info("%s: detach wed\n", __func__);
1938 mtk_wed_detach(dev);
1939+ }
1940 out:
1941 mutex_unlock(&hw_lock);
1942
1943@@ -1576,8 +2123,26 @@ mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx,
1944 if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE, reset))
1945 return -ENOMEM;
1946
1947+ if (dev->hw->version == 3 && idx == 1) {
1948+ /* reset prefetch index */
1949+ wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG,
1950+ MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR |
1951+ MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR);
1952+
1953+ wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
1954+ MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR |
1955+ MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR);
1956+
1957+ /* reset prefetch FIFO */
1958+ wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG,
1959+ MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR |
1960+ MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR);
1961+ wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG, 0);
1962+ }
1963+
1964 ring->reg_base = MTK_WED_RING_TX(idx);
1965 ring->wpdma = regs;
1966+ ring->flags |= MTK_WED_RING_CONFIGURED;
1967
1968 /* WED -> WPDMA */
1969 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
1970@@ -1599,7 +2164,7 @@ mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
1971 struct mtk_wed_ring *ring = &dev->txfree_ring;
1972 int i, idx = 1;
1973
1974- if(dev->ver > MTK_WED_V1)
1975+ if(dev->hw->version > 1)
1976 idx = 0;
1977
1978 /*
1979@@ -1652,6 +2217,129 @@ mtk_wed_rx_ring_setup(struct mtk_wed_device *dev,
1980 return 0;
1981 }
1982
1983+static int
1984+mtk_wed_rro_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
1985+{
1986+ struct mtk_wed_ring *ring = &dev->rx_rro_ring[idx];
1987+
1988+ ring->wpdma = regs;
1989+
1990+ wed_w32(dev, MTK_WED_RRO_RX_D_RX(idx) + MTK_WED_RING_OFS_BASE,
1991+ readl(regs));
1992+ wed_w32(dev, MTK_WED_RRO_RX_D_RX(idx) + MTK_WED_RING_OFS_COUNT,
1993+ readl(regs + MTK_WED_RING_OFS_COUNT));
1994+
1995+ ring->flags |= MTK_WED_RING_CONFIGURED;
1996+
1997+ return 0;
1998+}
1999+
2000+static int
2001+mtk_wed_msdu_pg_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
2002+{
2003+ struct mtk_wed_ring *ring = &dev->rx_page_ring[idx];
2004+
2005+ ring->wpdma = regs;
2006+
2007+ wed_w32(dev, MTK_WED_RRO_MSDU_PG_CTRL0(idx) + MTK_WED_RING_OFS_BASE,
2008+ readl(regs));
2009+ wed_w32(dev, MTK_WED_RRO_MSDU_PG_CTRL0(idx) + MTK_WED_RING_OFS_COUNT,
2010+ readl(regs + MTK_WED_RING_OFS_COUNT));
2011+
2012+ ring->flags |= MTK_WED_RING_CONFIGURED;
2013+
2014+ return 0;
2015+}
2016+
2017+static int
2018+mtk_wed_ind_rx_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
2019+{
2020+ struct mtk_wed_ring *ring = &dev->ind_cmd_ring;
2021+ u32 val = readl(regs + MTK_WED_RING_OFS_COUNT);
2022+ int i = 0, cnt = 0;
2023+
2024+ ring->wpdma = regs;
2025+
2026+ if (readl(regs) & 0xf)
2027+ pr_info("%s(): address is not 16-byte alignment\n", __func__);
2028+
2029+ wed_w32(dev, MTK_WED_IND_CMD_RX_CTRL1 + MTK_WED_RING_OFS_BASE,
2030+ readl(regs) & 0xfffffff0);
2031+
2032+ wed_w32(dev, MTK_WED_IND_CMD_RX_CTRL1 + MTK_WED_RING_OFS_COUNT,
2033+ readl(regs + MTK_WED_RING_OFS_COUNT));
2034+
2035+ /* ack sn cr */
2036+ wed_w32(dev, MTK_WED_RRO_CFG0, dev->wlan.phy_base +
2037+ dev->wlan.ind_cmd.ack_sn_addr);
2038+ wed_w32(dev, MTK_WED_RRO_CFG1,
2039+ FIELD_PREP(MTK_WED_RRO_CFG1_MAX_WIN_SZ,
2040+ dev->wlan.ind_cmd.win_size) |
2041+ FIELD_PREP(MTK_WED_RRO_CFG1_PARTICL_SE_ID,
2042+ dev->wlan.ind_cmd.particular_sid));
2043+
2044+ /* particular session addr element */
2045+ wed_w32(dev, MTK_WED_ADDR_ELEM_CFG0, dev->wlan.ind_cmd.particular_se_phys);
2046+
2047+ for (i = 0; i < dev->wlan.ind_cmd.se_group_nums; i++) {
2048+ wed_w32(dev, MTK_WED_RADDR_ELEM_TBL_WDATA,
2049+ dev->wlan.ind_cmd.addr_elem_phys[i] >> 4);
2050+ wed_w32(dev, MTK_WED_ADDR_ELEM_TBL_CFG,
2051+ MTK_WED_ADDR_ELEM_TBL_WR | (i & 0x7f));
2052+
2053+ val = wed_r32(dev, MTK_WED_ADDR_ELEM_TBL_CFG);
2054+ while (!(val & MTK_WED_ADDR_ELEM_TBL_WR_RDY) &&
2055+ cnt < 100) {
2056+ val = wed_r32(dev, MTK_WED_ADDR_ELEM_TBL_CFG);
2057+ cnt++;
2058+ }
2059+ if (cnt >= 100) {
2060+ dev_err(dev->hw->dev, "mtk_wed%d: write ba session base failed!\n",
2061+ dev->hw->index);
2062+ }
2063+ /*if (mtk_wed_poll_busy(dev, MTK_WED_ADDR_ELEM_TBL_CFG,
2064+ MTK_WED_ADDR_ELEM_TBL_WR_RDY)) {
2065+ dev_err(dev->hw->dev, "mtk_wed%d: write ba session base failed!\n",
2066+ dev->hw->index);
2067+ return -1;
2068+ }*/
2069+ }
2070+
2071+ /* pn check init */
2072+ for (i = 0; i < dev->wlan.ind_cmd.particular_sid; i++) {
2073+ wed_w32(dev, MTK_WED_PN_CHECK_WDATA_M,
2074+ MTK_WED_PN_CHECK_IS_FIRST);
2075+
2076+ wed_w32(dev, MTK_WED_PN_CHECK_CFG, MTK_WED_PN_CHECK_WR |
2077+ FIELD_PREP(MTK_WED_PN_CHECK_SE_ID, i));
2078+
2079+ cnt = 0;
2080+ val = wed_r32(dev, MTK_WED_PN_CHECK_CFG);
2081+ while (!(val & MTK_WED_PN_CHECK_WR_RDY) &&
2082+ cnt < 100) {
2083+ val = wed_r32(dev, MTK_WED_PN_CHECK_CFG);
2084+ cnt++;
2085+ }
2086+ if (cnt >= 100) {
2087+ dev_err(dev->hw->dev, "mtk_wed%d: session(%d) init failed!\n",
2088+ dev->hw->index, i);
2089+ }
2090+ /*if (mtk_wed_poll_busy(dev, MTK_WED_PN_CHECK_CFG,
2091+ MTK_WED_PN_CHECK_WR_RDY)) {
2092+ dev_err(dev->hw->dev, "mtk_wed%d: session(%d) init failed!\n",
2093+ dev->hw->index, i);
2094+ //return -1;
2095+ }*/
2096+ }
2097+
2098+ wed_w32(dev, MTK_WED_RX_IND_CMD_CNT0, MTK_WED_RX_IND_CMD_DBG_CNT_EN);
2099+
2100+ wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_IND_CMD_EN);
2101+
2102+ return 0;
2103+}
2104+
2105+
2106 static u32
2107 mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
2108 {
2109@@ -1660,6 +2348,8 @@ mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
2110 val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
2111 wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
2112 val &= MTK_WED_EXT_INT_STATUS_ERROR_MASK;
2113+ if (dev->hw->version == 3)
2114+ val &= MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT;
2115 WARN_RATELIMIT(val, "mtk_wed%d: error status=%08x\n",
2116 dev->hw->index, val);
2117
2118@@ -1752,6 +2442,9 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
2119 .tx_ring_setup = mtk_wed_tx_ring_setup,
2120 .txfree_ring_setup = mtk_wed_txfree_ring_setup,
2121 .rx_ring_setup = mtk_wed_rx_ring_setup,
2122+ .rro_rx_ring_setup = mtk_wed_rro_rx_ring_setup,
2123+ .msdu_pg_rx_ring_setup = mtk_wed_msdu_pg_rx_ring_setup,
2124+ .ind_rx_ring_setup = mtk_wed_ind_rx_ring_setup,
2125 .msg_update = mtk_wed_send_msg,
2126 .start = mtk_wed_start,
2127 .stop = mtk_wed_stop,
2128@@ -1763,6 +2456,7 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
2129 .detach = mtk_wed_detach,
2130 .setup_tc = mtk_wed_eth_setup_tc,
2131 .ppe_check = mtk_wed_ppe_check,
2132+ .start_hwrro = mtk_wed_start_hwrro,
2133 };
2134 struct device_node *eth_np = eth->dev->of_node;
2135 struct platform_device *pdev;
2136@@ -1802,9 +2496,10 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
2137 hw->wdma_phy = wdma_phy;
2138 hw->index = index;
2139 hw->irq = irq;
2140- hw->ver = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
2141+ hw->version = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) ?
2142+ 3 : MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
2143
2144- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
2145+ if (hw->version == 1) {
2146 hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
2147 "mediatek,pcie-mirror");
2148 hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
2149@@ -1819,7 +2514,6 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
2150 regmap_write(hw->mirror, 0, 0);
2151 regmap_write(hw->mirror, 4, 0);
2152 }
2153- hw->ver = MTK_WED_V1;
2154 }
2155
2156 mtk_wed_hw_add_debugfs(hw);
2157diff --git a/drivers/net/ethernet/mediatek/mtk_wed.h b/drivers/net/ethernet/mediatek/mtk_wed.h
2158index 490873c..fcf7bd0 100644
2159--- a/drivers/net/ethernet/mediatek/mtk_wed.h
2160+++ b/drivers/net/ethernet/mediatek/mtk_wed.h
2161@@ -10,10 +10,13 @@
2162 #include <linux/netdevice.h>
2163 #define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000)
2164
2165-#define MTK_WED_PKT_SIZE 1900
2166+#define MTK_WED_PKT_SIZE 1920//1900
2167 #define MTK_WED_BUF_SIZE 2048
2168+#define MTK_WED_PAGE_BUF_SIZE 128
2169 #define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048)
2170+#define MTK_WED_RX_PAGE_BUF_PER_PAGE (PAGE_SIZE / 128)
2171 #define MTK_WED_RX_RING_SIZE 1536
2172+#define MTK_WED_RX_PG_BM_CNT 8192
2173
2174 #define MTK_WED_TX_RING_SIZE 2048
2175 #define MTK_WED_WDMA_RING_SIZE 512
2176@@ -27,6 +30,9 @@
2177 #define MTK_WED_RRO_QUE_CNT 8192
2178 #define MTK_WED_MIOD_ENTRY_CNT 128
2179
2180+#define MTK_WED_TX_BM_DMA_SIZE 65536
2181+#define MTK_WED_TX_BM_PKT_CNT 32768
2182+
2183 #define MODULE_ID_WO 1
2184
2185 struct mtk_eth;
2186@@ -43,6 +49,8 @@ struct mtk_wed_hw {
2187 struct dentry *debugfs_dir;
2188 struct mtk_wed_device *wed_dev;
2189 struct mtk_wed_wo *wed_wo;
2190+ struct mtk_wed_pao *wed_pao;
2191+ u32 pci_base;
2192 u32 debugfs_reg;
2193 u32 num_flows;
2194 u32 wdma_phy;
2195@@ -50,7 +58,8 @@ struct mtk_wed_hw {
2196 int ring_num;
2197 int irq;
2198 int index;
2199- u32 ver;
2200+ int token_id;
2201+ u32 version;
2202 };
2203
2204 struct mtk_wdma_info {
2205@@ -58,6 +67,18 @@ struct mtk_wdma_info {
2206 u8 queue;
2207 u16 wcid;
2208 u8 bss;
2209+ u32 usr_info;
2210+ u8 tid;
2211+ u8 is_fixedrate;
2212+ u8 is_prior;
2213+ u8 is_sp;
2214+ u8 hf;
2215+ u8 amsdu_en;
2216+};
2217+
2218+struct mtk_wed_pao {
2219+ char *hif_txd[32];
2220+ dma_addr_t hif_txd_phys[32];
2221 };
2222
2223 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
2224diff --git a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
2225index 4a9e684..51e3d7c 100644
2226--- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
2227+++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
2228@@ -11,9 +11,11 @@ struct reg_dump {
2229 u16 offset;
2230 u8 type;
2231 u8 base;
2232+ u32 mask;
2233 };
2234
2235 enum {
2236+ DUMP_TYPE_END,
2237 DUMP_TYPE_STRING,
2238 DUMP_TYPE_WED,
2239 DUMP_TYPE_WDMA,
2240@@ -23,8 +25,11 @@ enum {
2241 DUMP_TYPE_WED_RRO,
2242 };
2243
2244+#define DUMP_END() { .type = DUMP_TYPE_END }
2245 #define DUMP_STR(_str) { _str, 0, DUMP_TYPE_STRING }
2246 #define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ }
2247+#define DUMP_REG_MASK(_reg, _mask) { #_mask, MTK_##_reg, DUMP_TYPE_WED, 0, MTK_##_mask }
2248+
2249 #define DUMP_RING(_prefix, _base, ...) \
2250 { _prefix " BASE", _base, __VA_ARGS__ }, \
2251 { _prefix " CNT", _base + 0x4, __VA_ARGS__ }, \
2252@@ -32,6 +37,7 @@ enum {
2253 { _prefix " DIDX", _base + 0xc, __VA_ARGS__ }
2254
2255 #define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED)
2256+#define DUMP_WED_MASK(_reg, _mask) DUMP_REG_MASK(_reg, _mask)
2257 #define DUMP_WED_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WED)
2258
2259 #define DUMP_WDMA(_reg) DUMP_REG(_reg, DUMP_TYPE_WDMA)
2260@@ -52,36 +58,49 @@ print_reg_val(struct seq_file *s, const char *name, u32 val)
2261
2262 static void
2263 dump_wed_regs(struct seq_file *s, struct mtk_wed_device *dev,
2264- const struct reg_dump *regs, int n_regs)
2265+ const struct reg_dump **regs)
2266 {
2267- const struct reg_dump *cur;
2268+ const struct reg_dump **cur_o = regs, *cur;
2269+ bool newline = false;
2270 u32 val;
2271
2272- for (cur = regs; cur < &regs[n_regs]; cur++) {
2273- switch (cur->type) {
2274- case DUMP_TYPE_STRING:
2275- seq_printf(s, "%s======== %s:\n",
2276- cur > regs ? "\n" : "",
2277- cur->name);
2278- continue;
2279- case DUMP_TYPE_WED:
2280- case DUMP_TYPE_WED_RRO:
2281- val = wed_r32(dev, cur->offset);
2282- break;
2283- case DUMP_TYPE_WDMA:
2284- val = wdma_r32(dev, cur->offset);
2285- break;
2286- case DUMP_TYPE_WPDMA_TX:
2287- val = wpdma_tx_r32(dev, cur->base, cur->offset);
2288- break;
2289- case DUMP_TYPE_WPDMA_TXFREE:
2290- val = wpdma_txfree_r32(dev, cur->offset);
2291- break;
2292- case DUMP_TYPE_WPDMA_RX:
2293- val = wpdma_rx_r32(dev, cur->base, cur->offset);
2294- break;
2295+ while (*cur_o) {
2296+ cur = *cur_o;
2297+
2298+ while (cur->type != DUMP_TYPE_END) {
2299+ switch (cur->type) {
2300+ case DUMP_TYPE_STRING:
2301+ seq_printf(s, "%s======== %s:\n",
2302+ newline ? "\n" : "",
2303+ cur->name);
2304+ newline = true;
2305+ cur++;
2306+ continue;
2307+ case DUMP_TYPE_WED:
2308+ case DUMP_TYPE_WED_RRO:
2309+ val = wed_r32(dev, cur->offset);
2310+ break;
2311+ case DUMP_TYPE_WDMA:
2312+ val = wdma_r32(dev, cur->offset);
2313+ break;
2314+ case DUMP_TYPE_WPDMA_TX:
2315+ val = wpdma_tx_r32(dev, cur->base, cur->offset);
2316+ break;
2317+ case DUMP_TYPE_WPDMA_TXFREE:
2318+ val = wpdma_txfree_r32(dev, cur->offset);
2319+ break;
2320+ case DUMP_TYPE_WPDMA_RX:
2321+ val = wpdma_rx_r32(dev, cur->base, cur->offset);
2322+ break;
2323+ }
2324+
2325+ if (cur->mask)
2326+ val = (cur->mask & val) >> (ffs(cur->mask) - 1);
2327+
2328+ print_reg_val(s, cur->name, val);
2329+ cur++;
2330 }
2331- print_reg_val(s, cur->name, val);
2332+ cur_o++;
2333 }
2334 }
2335
2336@@ -89,7 +108,7 @@ dump_wed_regs(struct seq_file *s, struct mtk_wed_device *dev,
2337 static int
2338 wed_txinfo_show(struct seq_file *s, void *data)
2339 {
2340- static const struct reg_dump regs[] = {
2341+ static const struct reg_dump regs_common[] = {
2342 DUMP_STR("WED TX"),
2343 DUMP_WED(WED_TX_MIB(0)),
2344 DUMP_WED_RING(WED_RING_TX(0)),
2345@@ -128,16 +147,32 @@ wed_txinfo_show(struct seq_file *s, void *data)
2346 DUMP_WDMA_RING(WDMA_RING_RX(0)),
2347 DUMP_WDMA_RING(WDMA_RING_RX(1)),
2348
2349- DUMP_STR("TX FREE"),
2350+ DUMP_STR("WED TX FREE"),
2351 DUMP_WED(WED_RX_MIB(0)),
2352+ DUMP_WED_RING(WED_RING_RX(0)),
2353+ DUMP_WED(WED_WPDMA_RX_COHERENT_MIB(0)),
2354+
2355+ DUMP_WED(WED_RX_MIB(1)),
2356+ DUMP_WED_RING(WED_RING_RX(1)),
2357+ DUMP_WED(WED_WPDMA_RX_COHERENT_MIB(1)),
2358+ DUMP_STR("WED_WPDMA TX FREE"),
2359+ DUMP_WED_RING(WED_WPDMA_RING_RX(0)),
2360+ DUMP_WED_RING(WED_WPDMA_RING_RX(1)),
2361+ DUMP_END(),
2362+ };
2363+
2364+ static const struct reg_dump *regs[] = {
2365+ &regs_common[0],
2366+ NULL,
2367 };
2368+
2369 struct mtk_wed_hw *hw = s->private;
2370 struct mtk_wed_device *dev = hw->wed_dev;
2371
2372 if (!dev)
2373 return 0;
2374
2375- dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
2376+ dump_wed_regs(s, dev, regs);
2377
2378 return 0;
2379 }
2380@@ -146,7 +181,7 @@ DEFINE_SHOW_ATTRIBUTE(wed_txinfo);
2381 static int
2382 wed_rxinfo_show(struct seq_file *s, void *data)
2383 {
2384- static const struct reg_dump regs[] = {
2385+ static const struct reg_dump regs_common[] = {
2386 DUMP_STR("WPDMA RX"),
2387 DUMP_WPDMA_RX_RING(0),
2388 DUMP_WPDMA_RX_RING(1),
2389@@ -164,7 +199,7 @@ wed_rxinfo_show(struct seq_file *s, void *data)
2390 DUMP_WED_RING(WED_RING_RX_DATA(0)),
2391 DUMP_WED_RING(WED_RING_RX_DATA(1)),
2392
2393- DUMP_STR("WED RRO"),
2394+ DUMP_STR("WED WO RRO"),
2395 DUMP_WED_RRO_RING(WED_RROQM_MIOD_CTRL0),
2396 DUMP_WED(WED_RROQM_MID_MIB),
2397 DUMP_WED(WED_RROQM_MOD_MIB),
2398@@ -175,16 +210,6 @@ wed_rxinfo_show(struct seq_file *s, void *data)
2399 DUMP_WED(WED_RROQM_FDBK_ANC_MIB),
2400 DUMP_WED(WED_RROQM_FDBK_ANC2H_MIB),
2401
2402- DUMP_STR("WED Route QM"),
2403- DUMP_WED(WED_RTQM_R2H_MIB(0)),
2404- DUMP_WED(WED_RTQM_R2Q_MIB(0)),
2405- DUMP_WED(WED_RTQM_Q2H_MIB(0)),
2406- DUMP_WED(WED_RTQM_R2H_MIB(1)),
2407- DUMP_WED(WED_RTQM_R2Q_MIB(1)),
2408- DUMP_WED(WED_RTQM_Q2H_MIB(1)),
2409- DUMP_WED(WED_RTQM_Q2N_MIB),
2410- DUMP_WED(WED_RTQM_Q2B_MIB),
2411- DUMP_WED(WED_RTQM_PFDBK_MIB),
2412
2413 DUMP_STR("WED WDMA TX"),
2414 DUMP_WED(WED_WDMA_TX_MIB),
2415@@ -205,15 +230,99 @@ wed_rxinfo_show(struct seq_file *s, void *data)
2416 DUMP_WED(WED_RX_BM_INTF2),
2417 DUMP_WED(WED_RX_BM_INTF),
2418 DUMP_WED(WED_RX_BM_ERR_STS),
2419+ DUMP_END()
2420+ };
2421+
2422+ static const struct reg_dump regs_v2[] = {
2423+ DUMP_STR("WED Route QM"),
2424+ DUMP_WED(WED_RTQM_R2H_MIB(0)),
2425+ DUMP_WED(WED_RTQM_R2Q_MIB(0)),
2426+ DUMP_WED(WED_RTQM_Q2H_MIB(0)),
2427+ DUMP_WED(WED_RTQM_R2H_MIB(1)),
2428+ DUMP_WED(WED_RTQM_R2Q_MIB(1)),
2429+ DUMP_WED(WED_RTQM_Q2H_MIB(1)),
2430+ DUMP_WED(WED_RTQM_Q2N_MIB),
2431+ DUMP_WED(WED_RTQM_Q2B_MIB),
2432+ DUMP_WED(WED_RTQM_PFDBK_MIB),
2433+
2434+ DUMP_END()
2435+ };
2436+
2437+ static const struct reg_dump regs_v3[] = {
2438+ DUMP_STR("WED RX RRO DATA"),
2439+ DUMP_WED_RING(WED_RRO_RX_D_RX(0)),
2440+ DUMP_WED_RING(WED_RRO_RX_D_RX(1)),
2441+
2442+ DUMP_STR("WED RX MSDU PAGE"),
2443+ DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(0)),
2444+ DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(1)),
2445+ DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(2)),
2446+
2447+ DUMP_STR("WED RX IND CMD"),
2448+ DUMP_WED(WED_IND_CMD_RX_CTRL1),
2449+ DUMP_WED_MASK(WED_IND_CMD_RX_CTRL2, WED_IND_CMD_MAX_CNT),
2450+ DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0, WED_IND_CMD_PROC_IDX),
2451+ DUMP_WED_MASK(RRO_IND_CMD_SIGNATURE, RRO_IND_CMD_DMA_IDX),
2452+ DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0, WED_IND_CMD_MAGIC_CNT),
2453+ DUMP_WED_MASK(RRO_IND_CMD_SIGNATURE, RRO_IND_CMD_MAGIC_CNT),
2454+ DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0,
2455+ WED_IND_CMD_PREFETCH_FREE_CNT),
2456+ DUMP_WED_MASK(WED_RRO_CFG1, WED_RRO_CFG1_PARTICL_SE_ID),
2457+
2458+ DUMP_STR("WED ADDR ELEM"),
2459+ DUMP_WED(WED_ADDR_ELEM_CFG0),
2460+ DUMP_WED_MASK(WED_ADDR_ELEM_CFG1,
2461+ WED_ADDR_ELEM_PREFETCH_FREE_CNT),
2462+
2463+ DUMP_STR("WED Route QM"),
2464+ DUMP_WED(WED_RTQM_ENQ_I2Q_DMAD_CNT),
2465+ DUMP_WED(WED_RTQM_ENQ_I2N_DMAD_CNT),
2466+ DUMP_WED(WED_RTQM_ENQ_I2Q_PKT_CNT),
2467+ DUMP_WED(WED_RTQM_ENQ_I2N_PKT_CNT),
2468+ DUMP_WED(WED_RTQM_ENQ_USED_ENTRY_CNT),
2469+ DUMP_WED(WED_RTQM_ENQ_ERR_CNT),
2470+
2471+ DUMP_WED(WED_RTQM_DEQ_DMAD_CNT),
2472+ DUMP_WED(WED_RTQM_DEQ_Q2I_DMAD_CNT),
2473+ DUMP_WED(WED_RTQM_DEQ_PKT_CNT),
2474+ DUMP_WED(WED_RTQM_DEQ_Q2I_PKT_CNT),
2475+ DUMP_WED(WED_RTQM_DEQ_USED_PFDBK_CNT),
2476+ DUMP_WED(WED_RTQM_DEQ_ERR_CNT),
2477+
2478+ DUMP_END()
2479+ };
2480+
2481+ static const struct reg_dump *regs_new_v2[] = {
2482+ &regs_common[0],
2483+ &regs_v2[0],
2484+ NULL,
2485+ };
2486+
2487+ static const struct reg_dump *regs_new_v3[] = {
2488+ &regs_common[0],
2489+ &regs_v3[0],
2490+ NULL,
2491 };
2492
2493 struct mtk_wed_hw *hw = s->private;
2494 struct mtk_wed_device *dev = hw->wed_dev;
2495+ const struct reg_dump **regs;
2496
2497 if (!dev)
2498 return 0;
2499
2500- dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
2501+ switch(dev->hw->version) {
2502+ case 2:
2503+ regs = regs_new_v2;
2504+ break;
2505+ case 3:
2506+ regs = regs_new_v3;
2507+ break;
2508+ default:
2509+ return 0;
2510+ }
2511+
2512+ dump_wed_regs(s, dev, regs);
2513
2514 return 0;
2515 }
2516@@ -248,6 +357,383 @@ mtk_wed_reg_get(void *data, u64 *val)
2517 DEFINE_DEBUGFS_ATTRIBUTE(fops_regval, mtk_wed_reg_get, mtk_wed_reg_set,
2518 "0x%08llx\n");
2519
2520+static int
2521+wed_token_txd_show(struct seq_file *s, void *data)
2522+{
2523+ struct mtk_wed_hw *hw = s->private;
2524+ struct mtk_wed_device *dev = hw->wed_dev;
2525+ struct dma_page_info *page_list = dev->tx_buf_ring.pages;
2526+ int token = dev->wlan.token_start;
2527+ u32 val = hw->token_id, size = 1;
2528+ int page_idx = (val - token) / 2;
2529+ int i;
2530+
2531+ if (val < token) {
2532+ size = val;
2533+ page_idx = 0;
2534+ }
2535+
2536+ for (i = 0; i < size; i += MTK_WED_BUF_PER_PAGE) {
2537+ void *page = page_list[page_idx++].addr;
2538+ void *buf;
2539+ int j;
2540+
2541+ if (!page)
2542+ break;
2543+
2544+ buf = page_to_virt(page);
2545+
2546+ for (j = 0; j < MTK_WED_BUF_PER_PAGE; j++) {
2547+ printk("[TXD]:token id = %d\n", token + 2 * (page_idx - 1) + j);
2548+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)buf, 128, false);
2549+ seq_printf(s, "\n");
2550+
2551+ buf += MTK_WED_BUF_SIZE;
2552+ }
2553+ }
2554+
2555+ return 0;
2556+}
2557+
2558+DEFINE_SHOW_ATTRIBUTE(wed_token_txd);
2559+
2560+static int
2561+wed_pao_show(struct seq_file *s, void *data)
2562+{
2563+ static const struct reg_dump regs_common[] = {
2564+ DUMP_STR("PAO AMDSU INFO"),
2565+ DUMP_WED(WED_PAO_MON_AMSDU_FIFO_DMAD),
2566+
2567+ DUMP_STR("PAO AMDSU ENG0 INFO"),
2568+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(0)),
2569+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(0)),
2570+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(0)),
2571+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(0)),
2572+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(0)),
2573+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(0),
2574+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2575+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(0),
2576+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2577+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(0),
2578+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2579+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(0),
2580+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2581+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(0),
2582+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2583+
2584+ DUMP_STR("PAO AMDSU ENG1 INFO"),
2585+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(1)),
2586+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(1)),
2587+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(1)),
2588+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(1)),
2589+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(1)),
2590+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(1),
2591+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2592+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(1),
2593+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2594+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(1),
2595+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2596+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(2),
2597+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2598+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(2),
2599+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2600+
2601+ DUMP_STR("PAO AMDSU ENG2 INFO"),
2602+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(2)),
2603+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(2)),
2604+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(2)),
2605+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(2)),
2606+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(2)),
2607+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(2),
2608+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2609+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(2),
2610+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2611+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(2),
2612+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2613+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(2),
2614+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2615+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(2),
2616+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2617+
2618+ DUMP_STR("PAO AMDSU ENG3 INFO"),
2619+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(3)),
2620+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(3)),
2621+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(3)),
2622+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(3)),
2623+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(3)),
2624+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(3),
2625+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2626+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(3),
2627+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2628+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(3),
2629+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2630+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(3),
2631+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2632+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(3),
2633+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2634+
2635+ DUMP_STR("PAO AMDSU ENG4 INFO"),
2636+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(4)),
2637+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(4)),
2638+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(4)),
2639+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(4)),
2640+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(4)),
2641+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(4),
2642+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2643+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(4),
2644+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2645+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(4),
2646+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2647+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(4),
2648+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2649+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(4),
2650+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2651+
2652+ DUMP_STR("PAO AMDSU ENG5 INFO"),
2653+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(5)),
2654+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(5)),
2655+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(5)),
2656+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(5)),
2657+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(5)),
2658+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(5),
2659+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2660+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(5),
2661+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2662+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(5),
2663+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2664+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(5),
2665+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2666+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(5),
2667+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2668+
2669+ DUMP_STR("PAO AMDSU ENG6 INFO"),
2670+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(6)),
2671+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(6)),
2672+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(6)),
2673+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(6)),
2674+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(6)),
2675+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(6),
2676+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2677+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(6),
2678+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2679+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(6),
2680+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2681+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(6),
2682+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2683+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(6),
2684+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2685+
2686+ DUMP_STR("PAO AMDSU ENG7 INFO"),
2687+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(7)),
2688+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(7)),
2689+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(7)),
2690+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(7)),
2691+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(7)),
2692+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(7),
2693+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2694+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(7),
2695+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2696+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(7),
2697+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2698+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(7),
2699+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2700+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(4),
2701+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2702+
2703+ DUMP_STR("PAO AMDSU ENG8 INFO"),
2704+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(8)),
2705+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(8)),
2706+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(8)),
2707+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(8)),
2708+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(8)),
2709+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(8),
2710+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2711+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(8),
2712+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2713+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(8),
2714+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2715+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(8),
2716+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2717+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(8),
2718+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2719+
2720+ DUMP_STR("PAO QMEM INFO"),
2721+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(0), WED_PAO_QMEM_FQ_CNT),
2722+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(0), WED_PAO_QMEM_SP_QCNT),
2723+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(1), WED_PAO_QMEM_TID0_QCNT),
2724+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(1), WED_PAO_QMEM_TID1_QCNT),
2725+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(2), WED_PAO_QMEM_TID2_QCNT),
2726+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(2), WED_PAO_QMEM_TID3_QCNT),
2727+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(3), WED_PAO_QMEM_TID4_QCNT),
2728+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(3), WED_PAO_QMEM_TID5_QCNT),
2729+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(4), WED_PAO_QMEM_TID6_QCNT),
2730+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(4), WED_PAO_QMEM_TID7_QCNT),
2731+
2732+
2733+ DUMP_STR("PAO QMEM HEAD INFO"),
2734+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(0), WED_PAO_QMEM_FQ_HEAD),
2735+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(0), WED_PAO_QMEM_SP_QHEAD),
2736+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(1), WED_PAO_QMEM_TID0_QHEAD),
2737+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(1), WED_PAO_QMEM_TID1_QHEAD),
2738+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(2), WED_PAO_QMEM_TID2_QHEAD),
2739+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(2), WED_PAO_QMEM_TID3_QHEAD),
2740+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(3), WED_PAO_QMEM_TID4_QHEAD),
2741+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(3), WED_PAO_QMEM_TID5_QHEAD),
2742+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(4), WED_PAO_QMEM_TID6_QHEAD),
2743+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(4), WED_PAO_QMEM_TID7_QHEAD),
2744+
2745+ DUMP_STR("PAO QMEM TAIL INFO"),
2746+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(5), WED_PAO_QMEM_FQ_TAIL),
2747+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(5), WED_PAO_QMEM_SP_QTAIL),
2748+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(6), WED_PAO_QMEM_TID0_QTAIL),
2749+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(6), WED_PAO_QMEM_TID1_QTAIL),
2750+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(7), WED_PAO_QMEM_TID2_QTAIL),
2751+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(7), WED_PAO_QMEM_TID3_QTAIL),
2752+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(8), WED_PAO_QMEM_TID4_QTAIL),
2753+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(8), WED_PAO_QMEM_TID5_QTAIL),
2754+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(9), WED_PAO_QMEM_TID6_QTAIL),
2755+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(9), WED_PAO_QMEM_TID7_QTAIL),
2756+
2757+ DUMP_STR("PAO HIFTXD MSDU INFO"),
2758+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(1)),
2759+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(2)),
2760+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(3)),
2761+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(4)),
2762+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(5)),
2763+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(6)),
2764+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(7)),
2765+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(8)),
2766+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(9)),
2767+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(10)),
2768+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(11)),
2769+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(12)),
2770+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(13)),
2771+ DUMP_END()
2772+ };
2773+
2774+ static const struct reg_dump *regs[] = {
2775+ &regs_common[0],
2776+ NULL,
2777+ };
2778+ struct mtk_wed_hw *hw = s->private;
2779+ struct mtk_wed_device *dev = hw->wed_dev;
2780+
2781+ if (!dev)
2782+ return 0;
2783+
2784+ dump_wed_regs(s, dev, regs);
2785+
2786+ return 0;
2787+}
2788+DEFINE_SHOW_ATTRIBUTE(wed_pao);
2789+
2790+static int
2791+wed_rtqm_show(struct seq_file *s, void *data)
2792+{
2793+ static const struct reg_dump regs_common[] = {
2794+ DUMP_STR("WED Route QM IGRS0(N2H + Recycle)"),
2795+ DUMP_WED(WED_RTQM_IGRS0_I2HW_DMAD_CNT),
2796+ DUMP_WED(WED_RTQM_IGRS0_I2H_DMAD_CNT(0)),
2797+ DUMP_WED(WED_RTQM_IGRS0_I2H_DMAD_CNT(1)),
2798+ DUMP_WED(WED_RTQM_IGRS0_I2HW_PKT_CNT),
2799+ DUMP_WED(WED_RTQM_IGRS0_I2H_PKT_CNT(0)),
2800+ DUMP_WED(WED_RTQM_IGRS0_I2H_PKT_CNT(0)),
2801+ DUMP_WED(WED_RTQM_IGRS0_FDROP_CNT),
2802+
2803+
2804+ DUMP_STR("WED Route QM IGRS1(Legacy)"),
2805+ DUMP_WED(WED_RTQM_IGRS1_I2HW_DMAD_CNT),
2806+ DUMP_WED(WED_RTQM_IGRS1_I2H_DMAD_CNT(0)),
2807+ DUMP_WED(WED_RTQM_IGRS1_I2H_DMAD_CNT(1)),
2808+ DUMP_WED(WED_RTQM_IGRS1_I2HW_PKT_CNT),
2809+ DUMP_WED(WED_RTQM_IGRS1_I2H_PKT_CNT(0)),
2810+ DUMP_WED(WED_RTQM_IGRS1_I2H_PKT_CNT(1)),
2811+ DUMP_WED(WED_RTQM_IGRS1_FDROP_CNT),
2812+
2813+ DUMP_STR("WED Route QM IGRS2(RRO3.0)"),
2814+ DUMP_WED(WED_RTQM_IGRS2_I2HW_DMAD_CNT),
2815+ DUMP_WED(WED_RTQM_IGRS2_I2H_DMAD_CNT(0)),
2816+ DUMP_WED(WED_RTQM_IGRS2_I2H_DMAD_CNT(1)),
2817+ DUMP_WED(WED_RTQM_IGRS2_I2HW_PKT_CNT),
2818+ DUMP_WED(WED_RTQM_IGRS2_I2H_PKT_CNT(0)),
2819+ DUMP_WED(WED_RTQM_IGRS2_I2H_PKT_CNT(1)),
2820+ DUMP_WED(WED_RTQM_IGRS2_FDROP_CNT),
2821+
2822+ DUMP_STR("WED Route QM IGRS3(DEBUG)"),
2823+ DUMP_WED(WED_RTQM_IGRS2_I2HW_DMAD_CNT),
2824+ DUMP_WED(WED_RTQM_IGRS3_I2H_DMAD_CNT(0)),
2825+ DUMP_WED(WED_RTQM_IGRS3_I2H_DMAD_CNT(1)),
2826+ DUMP_WED(WED_RTQM_IGRS3_I2HW_PKT_CNT),
2827+ DUMP_WED(WED_RTQM_IGRS3_I2H_PKT_CNT(0)),
2828+ DUMP_WED(WED_RTQM_IGRS3_I2H_PKT_CNT(1)),
2829+ DUMP_WED(WED_RTQM_IGRS3_FDROP_CNT),
2830+
2831+ DUMP_END()
2832+ };
2833+
2834+ static const struct reg_dump *regs[] = {
2835+ &regs_common[0],
2836+ NULL,
2837+ };
2838+ struct mtk_wed_hw *hw = s->private;
2839+ struct mtk_wed_device *dev = hw->wed_dev;
2840+
2841+ if (!dev)
2842+ return 0;
2843+
2844+ dump_wed_regs(s, dev, regs);
2845+
2846+ return 0;
2847+}
2848+DEFINE_SHOW_ATTRIBUTE(wed_rtqm);
2849+
2850+
2851+static int
2852+wed_rro_show(struct seq_file *s, void *data)
2853+{
2854+ static const struct reg_dump regs_common[] = {
2855+ DUMP_STR("RRO/IND CMD CNT"),
2856+ DUMP_WED(WED_RX_IND_CMD_CNT(1)),
2857+ DUMP_WED(WED_RX_IND_CMD_CNT(2)),
2858+ DUMP_WED(WED_RX_IND_CMD_CNT(3)),
2859+ DUMP_WED(WED_RX_IND_CMD_CNT(4)),
2860+ DUMP_WED(WED_RX_IND_CMD_CNT(5)),
2861+ DUMP_WED(WED_RX_IND_CMD_CNT(6)),
2862+ DUMP_WED(WED_RX_IND_CMD_CNT(7)),
2863+ DUMP_WED(WED_RX_IND_CMD_CNT(8)),
2864+ DUMP_WED_MASK(WED_RX_IND_CMD_CNT(9),
2865+ WED_IND_CMD_MAGIC_CNT_FAIL_CNT),
2866+
2867+ DUMP_WED(WED_RX_ADDR_ELEM_CNT(0)),
2868+ DUMP_WED_MASK(WED_RX_ADDR_ELEM_CNT(1),
2869+ WED_ADDR_ELEM_SIG_FAIL_CNT),
2870+ DUMP_WED(WED_RX_MSDU_PG_CNT(1)),
2871+ DUMP_WED(WED_RX_MSDU_PG_CNT(2)),
2872+ DUMP_WED(WED_RX_MSDU_PG_CNT(3)),
2873+ DUMP_WED(WED_RX_MSDU_PG_CNT(4)),
2874+ DUMP_WED(WED_RX_MSDU_PG_CNT(5)),
2875+ DUMP_WED_MASK(WED_RX_PN_CHK_CNT,
2876+ WED_PN_CHK_FAIL_CNT),
2877+
2878+ DUMP_END()
2879+ };
2880+
2881+ static const struct reg_dump *regs[] = {
2882+ &regs_common[0],
2883+ NULL,
2884+ };
2885+ struct mtk_wed_hw *hw = s->private;
2886+ struct mtk_wed_device *dev = hw->wed_dev;
2887+
2888+ if (!dev)
2889+ return 0;
2890+
2891+ dump_wed_regs(s, dev, regs);
2892+
2893+ return 0;
2894+}
2895+DEFINE_SHOW_ATTRIBUTE(wed_rro);
2896+
2897 void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)
2898 {
2899 struct dentry *dir;
2900@@ -261,8 +747,18 @@ void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)
2901 debugfs_create_u32("regidx", 0600, dir, &hw->debugfs_reg);
2902 debugfs_create_file_unsafe("regval", 0600, dir, hw, &fops_regval);
2903 debugfs_create_file_unsafe("txinfo", 0400, dir, hw, &wed_txinfo_fops);
2904- debugfs_create_file_unsafe("rxinfo", 0400, dir, hw, &wed_rxinfo_fops);
2905- if (hw->ver != MTK_WED_V1) {
2906+ debugfs_create_u32("token_id", 0600, dir, &hw->token_id);
2907+ debugfs_create_file_unsafe("token_txd", 0600, dir, hw, &wed_token_txd_fops);
2908+
2909+ if (hw->version == 3)
2910+ debugfs_create_file_unsafe("pao", 0400, dir, hw, &wed_pao_fops);
2911+
2912+ if (hw->version != 1) {
2913+ debugfs_create_file_unsafe("rxinfo", 0400, dir, hw, &wed_rxinfo_fops);
2914+ if (hw->version == 3) {
2915+ debugfs_create_file_unsafe("rtqm", 0400, dir, hw, &wed_rtqm_fops);
2916+ debugfs_create_file_unsafe("rro", 0400, dir, hw, &wed_rro_fops);
2917+ }
2918 wed_wo_mcu_debugfs(hw, dir);
2919 }
2920 }
2921diff --git a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
2922index 96e30a3..055594d 100644
2923--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
2924+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
2925@@ -242,7 +242,7 @@ mtk_wed_load_firmware(struct mtk_wed_wo *wo)
2926 u32 ofs = 0;
2927 u32 boot_cr, val;
2928
2929- mcu = wo->hw->index ? MT7986_FIRMWARE_WO_2 : MT7986_FIRMWARE_WO_1;
2930+ mcu = wo->hw->index ? MTK_FIRMWARE_WO_1 : MTK_FIRMWARE_WO_0;
2931
2932 ret = request_firmware(&fw, mcu, wo->hw->dev);
2933 if (ret)
2934@@ -289,8 +289,12 @@ mtk_wed_load_firmware(struct mtk_wed_wo *wo)
2935 }
2936
2937 /* write the start address */
2938- boot_cr = wo->hw->index ?
2939- WOX_MCU_CFG_LS_WA_BOOT_ADDR_ADDR : WOX_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
2940+ if (wo->hw->version == 3)
2941+ boot_cr = WOX_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
2942+ else
2943+ boot_cr = wo->hw->index ?
2944+ WOX_MCU_CFG_LS_WA_BOOT_ADDR_ADDR : WOX_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
2945+
2946 wo_w32(wo, boot_cr, (wo->region[WO_REGION_EMI].addr_pa >> 16));
2947
2948 /* wo firmware reset */
2949@@ -298,8 +302,7 @@ mtk_wed_load_firmware(struct mtk_wed_wo *wo)
2950
2951 val = wo_r32(wo, WOX_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR);
2952
2953- val |= wo->hw->index ? WOX_MCU_CFG_LS_WF_MCU_CFG_WM_WA_WA_CPU_RSTB_MASK :
2954- WOX_MCU_CFG_LS_WF_MCU_CFG_WM_WA_WM_CPU_RSTB_MASK;
2955+ val |= WOX_MCU_CFG_LS_WF_MCU_CFG_WM_WA_WM_CPU_RSTB_MASK;
2956
2957 wo_w32(wo, WOX_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
2958
2959diff --git a/drivers/net/ethernet/mediatek/mtk_wed_mcu.h b/drivers/net/ethernet/mediatek/mtk_wed_mcu.h
2960index 19e1199..c07bdb6 100644
2961--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.h
2962+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.h
2963@@ -16,8 +16,9 @@
2964 #define WARP_OK_STATUS (0)
2965 #define WARP_ALREADY_DONE_STATUS (1)
2966
2967-#define MT7986_FIRMWARE_WO_1 "mediatek/mt7986_wo_0.bin"
2968-#define MT7986_FIRMWARE_WO_2 "mediatek/mt7986_wo_1.bin"
2969+#define MTK_FIRMWARE_WO_0 "mediatek/mtk_wo_0.bin"
2970+#define MTK_FIRMWARE_WO_1 "mediatek/mtk_wo_1.bin"
2971+#define MTK_FIRMWARE_WO_2 "mediatek/mtk_wo_2.bin"
2972
2973 #define WOCPU_EMI_DEV_NODE "mediatek,wocpu_emi"
2974 #define WOCPU_ILM_DEV_NODE "mediatek,wocpu_ilm"
2975diff --git a/drivers/net/ethernet/mediatek/mtk_wed_regs.h b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
2976index 403a36b..4e619ff 100644
2977--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
2978+++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
2979@@ -20,6 +20,9 @@
2980 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
2981 #define MTK_WED_RX_BM_TOKEN GENMASK(31, 16)
2982
2983+#define MTK_WDMA_TXD0_DESC_INFO_DMA_DONE BIT(29)
2984+#define MTK_WDMA_TXD1_DESC_INFO_DMA_DONE BIT(31)
2985+
2986 struct mtk_wdma_desc {
2987 __le32 buf0;
2988 __le32 ctrl;
2989@@ -51,6 +54,7 @@ struct mtk_wdma_desc {
2990 #define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)
2991 #define MTK_WED_RESET_RX_RRO_QM BIT(20)
2992 #define MTK_WED_RESET_RX_ROUTE_QM BIT(21)
2993+#define MTK_WED_RESET_TX_PAO BIT(22)
2994 #define MTK_WED_RESET_WED BIT(31)
2995
2996 #define MTK_WED_CTRL 0x00c
2997@@ -58,6 +62,9 @@ struct mtk_wdma_desc {
2998 #define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY BIT(1)
2999 #define MTK_WED_CTRL_WDMA_INT_AGENT_EN BIT(2)
3000 #define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY BIT(3)
3001+#define MTK_WED_CTRL_WED_RX_IND_CMD_EN BIT(5)
3002+#define MTK_WED_CTRL_WED_RX_PG_BM_EN BIT(6)
3003+#define MTK_WED_CTRL_WED_RX_PG_BM_BUSU BIT(7)
3004 #define MTK_WED_CTRL_WED_TX_BM_EN BIT(8)
3005 #define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9)
3006 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10)
3007@@ -68,9 +75,14 @@ struct mtk_wdma_desc {
3008 #define MTK_WED_CTRL_RX_RRO_QM_BUSY BIT(15)
3009 #define MTK_WED_CTRL_RX_ROUTE_QM_EN BIT(16)
3010 #define MTK_WED_CTRL_RX_ROUTE_QM_BUSY BIT(17)
3011+#define MTK_WED_CTRL_TX_TKID_ALI_EN BIT(20)
3012+#define MTK_WED_CTRL_TX_TKID_ALI_BUSY BIT(21)
3013+#define MTK_WED_CTRL_TX_PAO_EN BIT(22)
3014+#define MTK_WED_CTRL_TX_PAO_BUSY BIT(23)
3015 #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24)
3016 #define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25)
3017 #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28)
3018+#define MTK_WED_CTRL_FLD_MIB_RD_CLR BIT(28)
3019
3020 #define MTK_WED_EXT_INT_STATUS 0x020
3021 #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0)
3022@@ -78,12 +90,10 @@ struct mtk_wdma_desc {
3023 #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4)
3024 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8)
3025 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9)
3026-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
3027-#define MTK_WED_EXT_INT_STATUS_TX_TKID_LO_TH BIT(10)
3028-#define MTK_WED_EXT_INT_STATUS_TX_TKID_HI_TH BIT(11)
3029-#endif
3030-#define MTK_WED_EXT_INT_STATUS_RX_FREE_AT_EMPTY BIT(12)
3031-#define MTK_WED_EXT_INT_STATUS_RX_FBUF_DMAD_ER BIT(13)
3032+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH2 BIT(10)
3033+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH2 BIT(11)
3034+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(12)
3035+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(13)
3036 #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16)
3037 #define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR BIT(17)
3038 #define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT BIT(18)
3039@@ -100,17 +110,15 @@ struct mtk_wdma_desc {
3040 #define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \
3041 MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \
3042 MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \
3043- MTK_WED_EXT_INT_STATUS_RX_FREE_AT_EMPTY | \
3044- MTK_WED_EXT_INT_STATUS_RX_FBUF_DMAD_ER | \
3045 MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \
3046 MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \
3047 MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \
3048- MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR | \
3049- MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR)
3050+ MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR)
3051
3052 #define MTK_WED_EXT_INT_MASK 0x028
3053 #define MTK_WED_EXT_INT_MASK1 0x02c
3054 #define MTK_WED_EXT_INT_MASK2 0x030
3055+#define MTK_WED_EXT_INT_MASK3 0x034
3056
3057 #define MTK_WED_STATUS 0x060
3058 #define MTK_WED_STATUS_TX GENMASK(15, 8)
3059@@ -118,9 +126,14 @@ struct mtk_wdma_desc {
3060 #define MTK_WED_TX_BM_CTRL 0x080
3061 #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0)
3062 #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16)
3063+#define MTK_WED_TX_BM_CTRL_LEGACY_EN BIT(26)
3064+#define MTK_WED_TX_TKID_CTRL_FREE_FORMAT BIT(27)
3065 #define MTK_WED_TX_BM_CTRL_PAUSE BIT(28)
3066
3067 #define MTK_WED_TX_BM_BASE 0x084
3068+#define MTK_WED_TX_BM_INIT_PTR 0x088
3069+#define MTK_WED_TX_BM_SW_TAIL_IDX GENMASK(16, 0)
3070+#define MTK_WED_TX_BM_INIT_SW_TAIL_IDX BIT(16)
3071
3072 #define MTK_WED_TX_BM_BUF_LEN 0x08c
3073
3074@@ -134,22 +147,24 @@ struct mtk_wdma_desc {
3075 #if defined(CONFIG_MEDIATEK_NETSYS_V2)
3076 #define MTK_WED_TX_BM_DYN_THR_LO GENMASK(8, 0)
3077 #define MTK_WED_TX_BM_DYN_THR_HI GENMASK(24, 16)
3078-
3079-#define MTK_WED_TX_BM_TKID 0x0c8
3080-#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)
3081-#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
3082 #else
3083 #define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0)
3084 #define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16)
3085+#endif
3086
3087-#define MTK_WED_TX_BM_TKID 0x088
3088+#define MTK_WED_TX_BM_TKID 0x0c8
3089 #define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)
3090 #define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
3091-#endif
3092
3093 #define MTK_WED_TX_TKID_CTRL 0x0c0
3094+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
3095+#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(7, 0)
3096+#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(23, 16)
3097+#else
3098 #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(6, 0)
3099 #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16)
3100+#endif
3101+
3102 #define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28)
3103
3104 #define MTK_WED_TX_TKID_DYN_THR 0x0e0
3105@@ -220,12 +235,15 @@ struct mtk_wdma_desc {
3106 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5)
3107 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6)
3108 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7)
3109-#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(18, 16)
3110+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(15, 12)
3111+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4 BIT(18)
3112 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19)
3113-#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UEVENT_PKT_FMT_CHK BIT(20)
3114+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK BIT(20)
3115 #define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21)
3116 #define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24)
3117+#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST BIT(25)
3118 #define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28)
3119+#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK BIT(30)
3120
3121 /* CONFIG_MEDIATEK_NETSYS_V1 */
3122 #define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4)
3123@@ -288,9 +306,11 @@ struct mtk_wdma_desc {
3124 #define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16)
3125
3126 #define MTK_WED_PCIE_INT_CTRL 0x57c
3127-#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20)
3128-#define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16)
3129 #define MTK_WED_PCIE_INT_CTRL_POLL_EN GENMASK(13, 12)
3130+#define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16)
3131+#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20)
3132+#define MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER BIT(21)
3133+
3134 #define MTK_WED_WPDMA_CFG_BASE 0x580
3135 #define MTK_WED_WPDMA_CFG_INT_MASK 0x584
3136 #define MTK_WED_WPDMA_CFG_TX 0x588
3137@@ -319,20 +339,50 @@ struct mtk_wdma_desc {
3138 #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX GENMASK(25, 24)
3139
3140 #define MTK_WED_WPDMA_RX_GLO_CFG 0x76c
3141-#define MTK_WED_WPDMA_RX_RING 0x770
3142+#if defined(CONFIG_MEDIATEK_NETSYS_V2)
3143+#define MTK_WED_WPDMA_RX_RING0 0x770
3144+#else
3145+#define MTK_WED_WPDMA_RX_RING0 0x7d0
3146+#endif
3147+#define MTK_WED_WPDMA_RX_RING1 0x7d8
3148
3149 #define MTK_WED_WPDMA_RX_D_MIB(_n) (0x774 + (_n) * 4)
3150 #define MTK_WED_WPDMA_RX_D_PROCESSED_MIB(_n) (0x784 + (_n) * 4)
3151 #define MTK_WED_WPDMA_RX_D_COHERENT_MIB 0x78c
3152
3153+#define MTK_WED_WPDMA_RX_D_PREF_CFG 0x7b4
3154+#define MTK_WED_WPDMA_RX_D_PREF_EN BIT(0)
3155+#define MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE GENMASK(12, 8)
3156+#define MTK_WED_WPDMA_RX_D_PREF_LOW_THRES GENMASK(21, 16)
3157+
3158+#define MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX 0x7b8
3159+#define MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR BIT(15)
3160+
3161+#define MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX 0x7bc
3162+
3163+#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG 0x7c0
3164+#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR BIT(0)
3165+#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR BIT(16)
3166+
3167 #define MTK_WED_WDMA_RING_TX 0x800
3168
3169 #define MTK_WED_WDMA_TX_MIB 0x810
3170
3171-
3172 #define MTK_WED_WDMA_RING_RX(_n) (0x900 + (_n) * 0x10)
3173 #define MTK_WED_WDMA_RX_THRES(_n) (0x940 + (_n) * 0x4)
3174
3175+#define MTK_WED_WDMA_RX_PREF_CFG 0x950
3176+#define MTK_WED_WDMA_RX_PREF_EN BIT(0)
3177+#define MTK_WED_WDMA_RX_PREF_BURST_SIZE GENMASK(12, 8)
3178+#define MTK_WED_WDMA_RX_PREF_LOW_THRES GENMASK(21, 16)
3179+#define MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR BIT(24)
3180+#define MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR BIT(25)
3181+#define MTK_WED_WDMA_RX_PREF_DDONE2_EN BIT(26)
3182+
3183+#define MTK_WED_WDMA_RX_PREF_FIFO_CFG 0x95C
3184+#define MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR BIT(0)
3185+#define MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR BIT(16)
3186+
3187 #define MTK_WED_WDMA_GLO_CFG 0xa04
3188 #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0)
3189 #define MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK BIT(1)
3190@@ -365,6 +415,7 @@ struct mtk_wdma_desc {
3191 #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16)
3192
3193 #define MTK_WED_WDMA_INT_CTRL 0xa2c
3194+#define MTK_WED_WDMA_INT_POLL_PRD GENMASK(7, 0)
3195 #define MTK_WED_WDMA_INT_POLL_SRC_SEL GENMASK(17, 16)
3196
3197 #define MTK_WED_WDMA_CFG_BASE 0xaa0
3198@@ -426,6 +477,18 @@ struct mtk_wdma_desc {
3199 #define MTK_WDMA_INT_GRP1 0x250
3200 #define MTK_WDMA_INT_GRP2 0x254
3201
3202+#define MTK_WDMA_PREF_TX_CFG 0x2d0
3203+#define MTK_WDMA_PREF_TX_CFG_PREF_EN BIT(0)
3204+
3205+#define MTK_WDMA_PREF_RX_CFG 0x2dc
3206+#define MTK_WDMA_PREF_RX_CFG_PREF_EN BIT(0)
3207+
3208+#define MTK_WDMA_WRBK_TX_CFG 0x300
3209+#define MTK_WDMA_WRBK_TX_CFG_WRBK_EN BIT(30)
3210+
3211+#define MTK_WDMA_WRBK_RX_CFG 0x344
3212+#define MTK_WDMA_WRBK_RX_CFG_WRBK_EN BIT(30)
3213+
3214 #define MTK_PCIE_MIRROR_MAP(n) ((n) ? 0x4 : 0x0)
3215 #define MTK_PCIE_MIRROR_MAP_EN BIT(0)
3216 #define MTK_PCIE_MIRROR_MAP_WED_ID BIT(1)
3217@@ -439,6 +502,31 @@ struct mtk_wdma_desc {
3218 #define MTK_WED_RTQM_Q_DBG_BYPASS BIT(5)
3219 #define MTK_WED_RTQM_TXDMAD_FPORT GENMASK(23, 20)
3220
3221+#define MTK_WED_RTQM_IGRS0_I2HW_DMAD_CNT 0xb1c
3222+#define MTK_WED_RTQM_IGRS0_I2H_DMAD_CNT(_n) (0xb20 + (_n) * 0x4)
3223+#define MTK_WED_RTQM_IGRS0_I2HW_PKT_CNT 0xb28
3224+#define MTK_WED_RTQM_IGRS0_I2H_PKT_CNT(_n) (0xb2c + (_n) * 0x4)
3225+#define MTK_WED_RTQM_IGRS0_FDROP_CNT 0xb34
3226+
3227+
3228+#define MTK_WED_RTQM_IGRS1_I2HW_DMAD_CNT 0xb44
3229+#define MTK_WED_RTQM_IGRS1_I2H_DMAD_CNT(_n) (0xb48 + (_n) * 0x4)
3230+#define MTK_WED_RTQM_IGRS1_I2HW_PKT_CNT 0xb50
3231+#define MTK_WED_RTQM_IGRS1_I2H_PKT_CNT(_n) (0xb54+ (_n) * 0x4)
3232+#define MTK_WED_RTQM_IGRS1_FDROP_CNT 0xb5c
3233+
3234+#define MTK_WED_RTQM_IGRS2_I2HW_DMAD_CNT 0xb6c
3235+#define MTK_WED_RTQM_IGRS2_I2H_DMAD_CNT(_n) (0xb70 + (_n) * 0x4)
3236+#define MTK_WED_RTQM_IGRS2_I2HW_PKT_CNT 0xb78
3237+#define MTK_WED_RTQM_IGRS2_I2H_PKT_CNT(_n) (0xb7c+ (_n) * 0x4)
3238+#define MTK_WED_RTQM_IGRS2_FDROP_CNT 0xb84
3239+
3240+#define MTK_WED_RTQM_IGRS3_I2HW_DMAD_CNT 0xb94
3241+#define MTK_WED_RTQM_IGRS3_I2H_DMAD_CNT(_n) (0xb98 + (_n) * 0x4)
3242+#define MTK_WED_RTQM_IGRS3_I2HW_PKT_CNT 0xba0
3243+#define MTK_WED_RTQM_IGRS3_I2H_PKT_CNT(_n) (0xba4+ (_n) * 0x4)
3244+#define MTK_WED_RTQM_IGRS3_FDROP_CNT 0xbac
3245+
3246 #define MTK_WED_RTQM_R2H_MIB(_n) (0xb70 + (_n) * 0x4)
3247 #define MTK_WED_RTQM_R2Q_MIB(_n) (0xb78 + (_n) * 0x4)
3248 #define MTK_WED_RTQM_Q2N_MIB 0xb80
3249@@ -447,6 +535,24 @@ struct mtk_wdma_desc {
3250 #define MTK_WED_RTQM_Q2B_MIB 0xb8c
3251 #define MTK_WED_RTQM_PFDBK_MIB 0xb90
3252
3253+#define MTK_WED_RTQM_ENQ_CFG0 0xbb8
3254+#define MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT GENMASK(15, 12)
3255+
3256+#define MTK_WED_RTQM_FDROP_MIB 0xb84
3257+#define MTK_WED_RTQM_ENQ_I2Q_DMAD_CNT 0xbbc
3258+#define MTK_WED_RTQM_ENQ_I2N_DMAD_CNT 0xbc0
3259+#define MTK_WED_RTQM_ENQ_I2Q_PKT_CNT 0xbc4
3260+#define MTK_WED_RTQM_ENQ_I2N_PKT_CNT 0xbc8
3261+#define MTK_WED_RTQM_ENQ_USED_ENTRY_CNT 0xbcc
3262+#define MTK_WED_RTQM_ENQ_ERR_CNT 0xbd0
3263+
3264+#define MTK_WED_RTQM_DEQ_DMAD_CNT 0xbd8
3265+#define MTK_WED_RTQM_DEQ_Q2I_DMAD_CNT 0xbdc
3266+#define MTK_WED_RTQM_DEQ_PKT_CNT 0xbe0
3267+#define MTK_WED_RTQM_DEQ_Q2I_PKT_CNT 0xbe4
3268+#define MTK_WED_RTQM_DEQ_USED_PFDBK_CNT 0xbe8
3269+#define MTK_WED_RTQM_DEQ_ERR_CNT 0xbec
3270+
3271 #define MTK_WED_RROQM_GLO_CFG 0xc04
3272 #define MTK_WED_RROQM_RST_IDX 0xc08
3273 #define MTK_WED_RROQM_RST_IDX_MIOD BIT(0)
3274@@ -487,8 +593,8 @@ struct mtk_wdma_desc {
3275 #define MTK_WED_RX_BM_BASE 0xd84
3276 #define MTK_WED_RX_BM_INIT_PTR 0xd88
3277 #define MTK_WED_RX_BM_PTR 0xd8c
3278-#define MTK_WED_RX_BM_PTR_HEAD GENMASK(32, 16)
3279 #define MTK_WED_RX_BM_PTR_TAIL GENMASK(15, 0)
3280+#define MTK_WED_RX_BM_PTR_HEAD GENMASK(32, 16)
3281
3282 #define MTK_WED_RX_BM_BLEN 0xd90
3283 #define MTK_WED_RX_BM_STS 0xd94
3284@@ -496,7 +602,193 @@ struct mtk_wdma_desc {
3285 #define MTK_WED_RX_BM_INTF 0xd9c
3286 #define MTK_WED_RX_BM_ERR_STS 0xda8
3287
3288+#define MTK_RRO_IND_CMD_SIGNATURE 0xe00
3289+#define MTK_RRO_IND_CMD_DMA_IDX GENMASK(11, 0)
3290+#define MTK_RRO_IND_CMD_MAGIC_CNT GENMASK(30, 28)
3291+
3292+#define MTK_WED_IND_CMD_RX_CTRL0 0xe04
3293+#define MTK_WED_IND_CMD_PROC_IDX GENMASK(11, 0)
3294+#define MTK_WED_IND_CMD_PREFETCH_FREE_CNT GENMASK(19, 16)
3295+#define MTK_WED_IND_CMD_MAGIC_CNT GENMASK(30, 28)
3296+
3297+#define MTK_WED_IND_CMD_RX_CTRL1 0xe08
3298+#define MTK_WED_IND_CMD_RX_CTRL2 0xe0c
3299+#define MTK_WED_IND_CMD_MAX_CNT GENMASK(11, 0)
3300+#define MTK_WED_IND_CMD_BASE_M GENMASK(19, 16)
3301+
3302+#define MTK_WED_RRO_CFG0 0xe10
3303+#define MTK_WED_RRO_CFG1 0xe14
3304+#define MTK_WED_RRO_CFG1_MAX_WIN_SZ GENMASK(31, 29)
3305+#define MTK_WED_RRO_CFG1_ACK_SN_BASE_M GENMASK(19, 16)
3306+#define MTK_WED_RRO_CFG1_PARTICL_SE_ID GENMASK(11, 0)
3307+
3308+#define MTK_WED_ADDR_ELEM_CFG0 0xe18
3309+#define MTK_WED_ADDR_ELEM_CFG1 0xe1c
3310+#define MTK_WED_ADDR_ELEM_PREFETCH_FREE_CNT GENMASK(19, 16)
3311+
3312+#define MTK_WED_ADDR_ELEM_TBL_CFG 0xe20
3313+#define MTK_WED_ADDR_ELEM_TBL_OFFSET GENMASK(6, 0)
3314+#define MTK_WED_ADDR_ELEM_TBL_RD_RDY BIT(28)
3315+#define MTK_WED_ADDR_ELEM_TBL_WR_RDY BIT(29)
3316+#define MTK_WED_ADDR_ELEM_TBL_RD BIT(30)
3317+#define MTK_WED_ADDR_ELEM_TBL_WR BIT(31)
3318+
3319+#define MTK_WED_RADDR_ELEM_TBL_WDATA 0xe24
3320+#define MTK_WED_RADDR_ELEM_TBL_RDATA 0xe28
3321+
3322+#define MTK_WED_PN_CHECK_CFG 0xe30
3323+#define MTK_WED_PN_CHECK_SE_ID GENMASK(11, 0)
3324+#define MTK_WED_PN_CHECK_RD_RDY BIT(28)
3325+#define MTK_WED_PN_CHECK_WR_RDY BIT(29)
3326+#define MTK_WED_PN_CHECK_RD BIT(30)
3327+#define MTK_WED_PN_CHECK_WR BIT(31)
3328+
3329+#define MTK_WED_PN_CHECK_WDATA_M 0xe38
3330+#define MTK_WED_PN_CHECK_IS_FIRST BIT(17)
3331+
3332+#define MTK_WED_RRO_MSDU_PG_RING_CFG(_n) (0xe44 + (_n) * 0x8)
3333+
3334+#define MTK_WED_RRO_MSDU_PG_RING2_CFG 0xe58
3335+#define MTK_WED_RRO_MSDU_PG_DRV_CLR BIT(26)
3336+#define MTK_WED_RRO_MSDU_PG_DRV_EN BIT(31)
3337+
3338+#define MTK_WED_RRO_MSDU_PG_CTRL0(_n) (0xe5c + (_n) * 0xc)
3339+#define MTK_WED_RRO_MSDU_PG_CTRL1(_n) (0xe60 + (_n) * 0xc)
3340+#define MTK_WED_RRO_MSDU_PG_CTRL2(_n) (0xe64 + (_n) * 0xc)
3341+
3342+#define MTK_WED_RRO_RX_D_RX(_n) (0xe80 + (_n) * 0x10)
3343+
3344+#define MTK_WED_RRO_RX_MAGIC_CNT BIT(13)
3345+
3346+#define MTK_WED_RRO_RX_D_CFG(_n) (0xea0 + (_n) * 0x4)
3347+#define MTK_WED_RRO_RX_D_DRV_CLR BIT(26)
3348+#define MTK_WED_RRO_RX_D_DRV_EN BIT(31)
3349+
3350+#define MTK_WED_RRO_PG_BM_RX_DMAM 0xeb0
3351+#define MTK_WED_RRO_PG_BM_RX_SDL0 GENMASK(13, 0)
3352+
3353+#define MTK_WED_RRO_PG_BM_BASE 0xeb4
3354+#define MTK_WED_RRO_PG_BM_INIT_PTR 0xeb8
3355+#define MTK_WED_RRO_PG_BM_SW_TAIL_IDX GENMASK(15, 0)
3356+#define MTK_WED_RRO_PG_BM_INIT_SW_TAIL_IDX BIT(16)
3357+
3358+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX 0xeec
3359+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN BIT(0)
3360+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_CLR BIT(1)
3361+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_DONE_TRIG GENMASK(6, 2)
3362+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_EN BIT(8)
3363+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_CLR BIT(9)
3364+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_DONE_TRIG GENMASK(14, 10)
3365+
3366+#define MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG 0xef4
3367+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN BIT(0)
3368+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_CLR BIT(1)
3369+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_DONE_TRIG GENMASK(6, 2)
3370+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_EN BIT(8)
3371+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_CLR BIT(9)
3372+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_DONE_TRIG GENMASK(14, 10)
3373+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN BIT(16)
3374+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR BIT(17)
3375+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG GENMASK(22, 18)
3376+
3377+#define MTK_WED_RX_IND_CMD_CNT0 0xf20
3378+#define MTK_WED_RX_IND_CMD_DBG_CNT_EN BIT(31)
3379+
3380+#define MTK_WED_RX_IND_CMD_CNT(_n) (0xf20 + (_n) * 0x4)
3381+#define MTK_WED_IND_CMD_MAGIC_CNT_FAIL_CNT GENMASK(15, 0)
3382+
3383+#define MTK_WED_RX_ADDR_ELEM_CNT(_n) (0xf48 + (_n) * 0x4)
3384+#define MTK_WED_ADDR_ELEM_SIG_FAIL_CNT GENMASK(15, 0)
3385+#define MTK_WED_ADDR_ELEM_FIRST_SIG_FAIL_CNT GENMASK(31, 16)
3386+#define MTK_WED_ADDR_ELEM_ACKSN_CNT GENMASK(27, 0)
3387+
3388+#define MTK_WED_RX_MSDU_PG_CNT(_n) (0xf5c + (_n) * 0x4)
3389+
3390+#define MTK_WED_RX_PN_CHK_CNT 0xf70
3391+#define MTK_WED_PN_CHK_FAIL_CNT GENMASK(15, 0)
3392+
3393 #define MTK_WED_WOCPU_VIEW_MIOD_BASE 0x8000
3394 #define MTK_WED_PCIE_INT_MASK 0x0
3395
3396+#define MTK_WED_PAO_AMSDU_FIFO 0x1800
3397+#define MTK_WED_PAO_AMSDU_IS_PRIOR0_RING BIT(10)
3398+
3399+#define MTK_WED_PAO_STA_INFO 0x01810
3400+#define MTK_WED_PAO_STA_INFO_DO_INIT BIT(0)
3401+#define MTK_WED_PAO_STA_INFO_SET_INIT BIT(1)
3402+
3403+#define MTK_WED_PAO_STA_INFO_INIT 0x01814
3404+#define MTK_WED_PAO_STA_WTBL_HDRT_MODE BIT(0)
3405+#define MTK_WED_PAO_STA_RMVL BIT(1)
3406+#define MTK_WED_PAO_STA_MAX_AMSDU_LEN GENMASK(7, 2)
3407+#define MTK_WED_PAO_STA_MAX_AMSDU_NUM GENMASK(11, 8)
3408+
3409+#define MTK_WED_PAO_HIFTXD_BASE_L(_n) (0x1980 + (_n) * 0x4)
3410+
3411+#define MTK_WED_PAO_PSE 0x1910
3412+#define MTK_WED_PAO_PSE_RESET BIT(16)
3413+
3414+#define MTK_WED_PAO_HIFTXD_CFG 0x1968
3415+#define MTK_WED_PAO_HIFTXD_SRC GENMASK(16, 15)
3416+
3417+#define MTK_WED_PAO_MON_AMSDU_FIFO_DMAD 0x1a34
3418+
3419+#define MTK_WED_PAO_MON_AMSDU_ENG_DMAD(_n) (0x1a80 + (_n) * 0x50)
3420+#define MTK_WED_PAO_MON_AMSDU_ENG_QFPL(_n) (0x1a84 + (_n) * 0x50)
3421+#define MTK_WED_PAO_MON_AMSDU_ENG_QENI(_n) (0x1a88 + (_n) * 0x50)
3422+#define MTK_WED_PAO_MON_AMSDU_ENG_QENO(_n) (0x1a8c + (_n) * 0x50)
3423+#define MTK_WED_PAO_MON_AMSDU_ENG_MERG(_n) (0x1a90 + (_n) * 0x50)
3424+
3425+#define MTK_WED_PAO_MON_AMSDU_ENG_CNT8(_n) (0x1a94 + (_n) * 0x50)
3426+#define MTK_WED_PAO_AMSDU_ENG_MAX_QGPP_CNT GENMASK(10, 0)
3427+#define MTK_WED_PAO_AMSDU_ENG_MAX_PL_CNT GENMASK(27, 16)
3428+
3429+#define MTK_WED_PAO_MON_AMSDU_ENG_CNT9(_n) (0x1a98 + (_n) * 0x50)
3430+#define MTK_WED_PAO_AMSDU_ENG_CUR_ENTRY GENMASK(10, 0)
3431+#define MTK_WED_PAO_AMSDU_ENG_MAX_BUF_MERGED GENMASK(20, 16)
3432+#define MTK_WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED GENMASK(28, 24)
3433+
3434+#define MTK_WED_PAO_MON_QMEM_STS1 0x1e04
3435+
3436+#define MTK_WED_PAO_MON_QMEM_CNT(_n) (0x1e0c + (_n) * 0x4)
3437+#define MTK_WED_PAO_QMEM_FQ_CNT GENMASK(27, 16)
3438+#define MTK_WED_PAO_QMEM_SP_QCNT GENMASK(11, 0)
3439+#define MTK_WED_PAO_QMEM_TID0_QCNT GENMASK(27, 16)
3440+#define MTK_WED_PAO_QMEM_TID1_QCNT GENMASK(11, 0)
3441+#define MTK_WED_PAO_QMEM_TID2_QCNT GENMASK(27, 16)
3442+#define MTK_WED_PAO_QMEM_TID3_QCNT GENMASK(11, 0)
3443+#define MTK_WED_PAO_QMEM_TID4_QCNT GENMASK(27, 16)
3444+#define MTK_WED_PAO_QMEM_TID5_QCNT GENMASK(11, 0)
3445+#define MTK_WED_PAO_QMEM_TID6_QCNT GENMASK(27, 16)
3446+#define MTK_WED_PAO_QMEM_TID7_QCNT GENMASK(11, 0)
3447+
3448+#define MTK_WED_PAO_MON_QMEM_PTR(_n) (0x1e20 + (_n) * 0x4)
3449+#define MTK_WED_PAO_QMEM_FQ_HEAD GENMASK(27, 16)
3450+#define MTK_WED_PAO_QMEM_SP_QHEAD GENMASK(11, 0)
3451+#define MTK_WED_PAO_QMEM_TID0_QHEAD GENMASK(27, 16)
3452+#define MTK_WED_PAO_QMEM_TID1_QHEAD GENMASK(11, 0)
3453+#define MTK_WED_PAO_QMEM_TID2_QHEAD GENMASK(27, 16)
3454+#define MTK_WED_PAO_QMEM_TID3_QHEAD GENMASK(11, 0)
3455+#define MTK_WED_PAO_QMEM_TID4_QHEAD GENMASK(27, 16)
3456+#define MTK_WED_PAO_QMEM_TID5_QHEAD GENMASK(11, 0)
3457+#define MTK_WED_PAO_QMEM_TID6_QHEAD GENMASK(27, 16)
3458+#define MTK_WED_PAO_QMEM_TID7_QHEAD GENMASK(11, 0)
3459+#define MTK_WED_PAO_QMEM_FQ_TAIL GENMASK(27, 16)
3460+#define MTK_WED_PAO_QMEM_SP_QTAIL GENMASK(11, 0)
3461+#define MTK_WED_PAO_QMEM_TID0_QTAIL GENMASK(27, 16)
3462+#define MTK_WED_PAO_QMEM_TID1_QTAIL GENMASK(11, 0)
3463+#define MTK_WED_PAO_QMEM_TID2_QTAIL GENMASK(27, 16)
3464+#define MTK_WED_PAO_QMEM_TID3_QTAIL GENMASK(11, 0)
3465+#define MTK_WED_PAO_QMEM_TID4_QTAIL GENMASK(27, 16)
3466+#define MTK_WED_PAO_QMEM_TID5_QTAIL GENMASK(11, 0)
3467+#define MTK_WED_PAO_QMEM_TID6_QTAIL GENMASK(27, 16)
3468+#define MTK_WED_PAO_QMEM_TID7_QTAIL GENMASK(11, 0)
3469+
3470+#define MTK_WED_PAO_MON_HIFTXD_FETCH_MSDU(_n) (0x1ec4 + (_n) * 0x4)
3471+
3472+#define MTK_WED_PCIE_BASE 0x11280000
3473+
3474+#define MTK_WED_PCIE_BASE0 0x11300000
3475+#define MTK_WED_PCIE_BASE1 0x11310000
3476+#define MTK_WED_PCIE_BASE2 0x11290000
3477 #endif
3478diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
3479index 58b5ce6..5e51790 100644
3480--- a/include/linux/netdevice.h
3481+++ b/include/linux/netdevice.h
3482@@ -873,6 +873,13 @@ struct net_device_path {
3483 u8 queue;
3484 u16 wcid;
3485 u8 bss;
3486+ u32 usr_info;
3487+ u8 tid;
3488+ u8 is_fixedrate;
3489+ u8 is_prior;
3490+ u8 is_sp;
3491+ u8 hf;
3492+ u8 amsdu_en;
3493 } mtk_wdma;
3494 };
3495 };
3496diff --git a/include/linux/soc/mediatek/mtk_wed.h b/include/linux/soc/mediatek/mtk_wed.h
3497index 27cf284..60336e0 100644
3498--- a/include/linux/soc/mediatek/mtk_wed.h
3499+++ b/include/linux/soc/mediatek/mtk_wed.h
3500@@ -5,11 +5,14 @@
3501 #include <linux/rcupdate.h>
3502 #include <linux/regmap.h>
3503 #include <linux/pci.h>
3504+#include <linux/skbuff.h>
3505+#include <linux/iopoll.h>
3506
3507 #define WED_WO_STA_REC 0x6
3508
3509 #define MTK_WED_TX_QUEUES 2
3510 #define MTK_WED_RX_QUEUES 2
3511+#define MTK_WED_RX_PAGE_QUEUES 3
3512
3513 enum mtk_wed_wo_cmd {
3514 MTK_WED_WO_CMD_WED_CFG,
3515@@ -55,10 +58,13 @@ enum mtk_wed_bus_tye {
3516 struct mtk_wed_hw;
3517 struct mtk_wdma_desc;
3518
3519+#define MTK_WED_RING_CONFIGURED BIT(0)
3520+
3521 struct mtk_wed_ring {
3522 struct mtk_wdma_desc *desc;
3523 dma_addr_t desc_phys;
3524 int size;
3525+ u32 flags;
3526
3527 u32 reg_base;
3528 void __iomem *wpdma;
3529@@ -69,11 +75,18 @@ struct mtk_rxbm_desc {
3530 __le32 token;
3531 } __packed __aligned(4);
3532
3533+struct dma_page_info {
3534+ void *addr;
3535+ dma_addr_t addr_phys;
3536+};
3537+
3538 struct dma_buf {
3539 int size;
3540- void **pages;
3541- struct mtk_wdma_desc *desc;
3542+ int pkt_nums;
3543+ void *desc;
3544+ int desc_size;
3545 dma_addr_t desc_phys;
3546+ struct dma_page_info *pages;
3547 };
3548
3549 struct dma_entry {
3550@@ -97,6 +110,7 @@ struct mtk_wed_device {
3551 struct device *dev;
3552 struct mtk_wed_hw *hw;
3553 bool init_done, running;
3554+ bool wdma_init_done;
3555 int wdma_idx;
3556 int irq;
3557 u8 ver;
3558@@ -108,7 +122,11 @@ struct mtk_wed_device {
3559 struct mtk_wed_ring rx_ring[MTK_WED_RX_QUEUES];
3560 struct mtk_wed_ring rx_wdma[MTK_WED_RX_QUEUES];
3561
3562- struct dma_buf buf_ring;
3563+ struct mtk_wed_ring rx_rro_ring[MTK_WED_RX_QUEUES];
3564+ struct mtk_wed_ring rx_page_ring[MTK_WED_RX_PAGE_QUEUES];
3565+ struct mtk_wed_ring ind_cmd_ring;
3566+
3567+ struct dma_buf tx_buf_ring;
3568
3569 struct {
3570 int size;
3571@@ -117,6 +135,8 @@ struct mtk_wed_device {
3572 dma_addr_t desc_phys;
3573 } rx_buf_ring;
3574
3575+ struct dma_buf rx_page_buf_ring;
3576+
3577 struct {
3578 struct mtk_wed_ring rro_ring;
3579 void __iomem *rro_desc;
3580@@ -131,8 +151,9 @@ struct mtk_wed_device {
3581 struct platform_device *platform_dev;
3582 struct pci_dev *pci_dev;
3583 };
3584+ enum mtk_wed_bus_tye bus_type;
3585 void __iomem *base;
3586- u32 bus_type;
3587+ void __iomem *regs;
3588 u32 phy_base;
3589
3590 u32 wpdma_phys;
3591@@ -142,9 +163,13 @@ struct mtk_wed_device {
3592 u32 wpdma_txfree;
3593 u32 wpdma_rx_glo;
3594 u32 wpdma_rx;
3595+ u32 wpdma_rx_rro[MTK_WED_RX_QUEUES];
3596+ u32 wpdma_rx_pg;
3597
3598 u8 tx_tbit[MTK_WED_TX_QUEUES];
3599 u8 rx_tbit[MTK_WED_RX_QUEUES];
3600+ u8 rro_rx_tbit[MTK_WED_RX_QUEUES];
3601+ u8 rx_pg_tbit[MTK_WED_RX_PAGE_QUEUES];
3602 u8 txfree_tbit;
3603
3604 u16 token_start;
3605@@ -154,12 +179,26 @@ struct mtk_wed_device {
3606 unsigned int rx_size;
3607
3608 bool wcid_512;
3609-
3610+ bool hwrro;
3611+ bool msi;
3612+
3613+ u8 max_amsdu_nums;
3614+ u32 max_amsdu_len;
3615+
3616+ struct {
3617+ u8 se_group_nums;
3618+ u16 win_size;
3619+ u16 particular_sid;
3620+ u32 ack_sn_addr;
3621+ dma_addr_t particular_se_phys;
3622+ dma_addr_t addr_elem_phys[1024];
3623+ } ind_cmd;
3624+
3625+ u32 chip_id;
3626 u32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id);
3627 int (*offload_enable)(struct mtk_wed_device *wed);
3628 void (*offload_disable)(struct mtk_wed_device *wed);
3629- u32 (*init_rx_buf)(struct mtk_wed_device *wed,
3630- int pkt_num);
3631+ u32 (*init_rx_buf)(struct mtk_wed_device *wed, int size);
3632 void (*release_rx_buf)(struct mtk_wed_device *wed);
3633 void (*update_wo_rx_stats)(struct mtk_wed_device *wed,
3634 struct mtk_wed_wo_rx_stats *stats);
3635@@ -180,6 +219,11 @@ struct mtk_wed_ops {
3636 void __iomem *regs);
3637 int (*rx_ring_setup)(struct mtk_wed_device *dev, int ring,
3638 void __iomem *regs, bool reset);
3639+ int (*rro_rx_ring_setup)(struct mtk_wed_device *dev, int ring,
3640+ void __iomem *regs);
3641+ int (*msdu_pg_rx_ring_setup)(struct mtk_wed_device *dev, int ring,
3642+ void __iomem *regs);
3643+ int (*ind_rx_ring_setup)(struct mtk_wed_device *dev, void __iomem *regs);
3644 int (*msg_update)(struct mtk_wed_device *dev, int cmd_id,
3645 void *data, int len);
3646 void (*detach)(struct mtk_wed_device *dev);
3647@@ -196,6 +240,7 @@ struct mtk_wed_ops {
3648 void (*irq_set_mask)(struct mtk_wed_device *dev, u32 mask);
3649 void (*ppe_check)(struct mtk_wed_device *dev, struct sk_buff *skb,
3650 u32 reason, u32 hash);
3651+ void (*start_hwrro)(struct mtk_wed_device *dev, u32 irq_mask);
3652 };
3653
3654 extern const struct mtk_wed_ops __rcu *mtk_soc_wed_ops;
3655@@ -224,12 +269,21 @@ static inline bool
3656 mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
3657 {
3658 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
3659+ if (dev->ver == 3 && !dev->wlan.hwrro)
3660+ return false;
3661+
3662 return dev->ver != 1;
3663 #else
3664 return false;
3665 #endif
3666 }
3667
3668+static inline bool
3669+mtk_wed_device_support_pao(struct mtk_wed_device *dev)
3670+{
3671+ return dev->ver == 3;
3672+}
3673+
3674 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
3675 #define mtk_wed_device_active(_dev) !!(_dev)->ops
3676 #define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev)
3677@@ -243,6 +297,12 @@ mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
3678 (_dev)->ops->txfree_ring_setup(_dev, _regs)
3679 #define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) \
3680 (_dev)->ops->rx_ring_setup(_dev, _ring, _regs, _reset)
3681+#define mtk_wed_device_rro_rx_ring_setup(_dev, _ring, _regs) \
3682+ (_dev)->ops->rro_rx_ring_setup(_dev, _ring, _regs)
3683+#define mtk_wed_device_msdu_pg_rx_ring_setup(_dev, _ring, _regs) \
3684+ (_dev)->ops->msdu_pg_rx_ring_setup(_dev, _ring, _regs)
3685+#define mtk_wed_device_ind_rx_ring_setup(_dev, _regs) \
3686+ (_dev)->ops->ind_rx_ring_setup(_dev, _regs)
3687 #define mtk_wed_device_update_msg(_dev, _id, _msg, _len) \
3688 (_dev)->ops->msg_update(_dev, _id, _msg, _len)
3689 #define mtk_wed_device_reg_read(_dev, _reg) \
3690@@ -257,6 +317,9 @@ mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
3691 (_dev)->ops->reset_dma(_dev)
3692 #define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) \
3693 (_dev)->ops->ppe_check(_dev, _skb, _reason, _hash)
3694+#define mtk_wed_device_start_hwrro(_dev, _mask) \
3695+ (_dev)->ops->start_hwrro(_dev, _mask)
3696+
3697 #else
3698 static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
3699 {
3700@@ -268,6 +331,9 @@ static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
3701 #define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV
3702 #define mtk_wed_device_txfree_ring_setup(_dev, _ring, _regs) -ENODEV
3703 #define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV
3704+#define mtk_wed_device_rro_rx_ring_setup(_dev, _ring, _regs) -ENODEV
3705+#define mtk_wed_device_msdu_pg_rx_ring_setup(_dev, _ring, _regs) -ENODEV
3706+#define mtk_wed_device_ind_rx_ring_setup(_dev, _regs) -ENODEV
3707 #define mtk_wed_device_reg_read(_dev, _reg) 0
3708 #define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0)
3709 #define mtk_wed_device_irq_get(_dev, _mask) 0
3710@@ -275,6 +341,7 @@ static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
3711 #define mtk_wed_device_dma_reset(_dev) do {} while (0)
3712 #define mtk_wed_device_setup_tc(_dev, _ndev, _type, _data) do {} while (0)
3713 #define mtk_wed_device_ppe_check(_dev, _hash) do {} while (0)
3714+#define mtk_wed_device_start_hwrro(_dev, _mask) do {} while (0)
3715 #endif
3716
3717 #endif
3718--
37192.18.0
3720