blob: 23a03335cc862fe4657475422c8bc85c1307b64c [file] [log] [blame]
developer7e3c5b72022-02-21 21:38:33 +08001Index: drivers/net/phy/Kconfig
2===================================================================
3--- a/drivers/net/phy/Kconfig
4+++ b/drivers/net/phy/Kconfig
5@@ -345,6 +345,11 @@ config SFP
6 depends on HWMON || HWMON=n
7 select MDIO_I2C
8
9+config AIROHA_EN8801S_PHY
10+ tristate "Drivers for Airoha EN8801S Gigabit PHYs"
11+ ---help---
12+ Currently supports the Airoha EN8801S PHY.
13+
14 config ADIN_PHY
15 tristate "Analog Devices Industrial Ethernet PHYs"
16 help
17Index: drivers/net/phy/Makefile
18===================================================================
19--- a/drivers/net/phy/Makefile
20+++ b/drivers/net/phy/Makefile
21@@ -67,6 +67,7 @@ aquantia-objs += aquantia_main.o
22 ifdef CONFIG_HWMON
23 aquantia-objs += aquantia_hwmon.o
24 endif
25+obj-$(CONFIG_AIROHA_EN8801S_PHY) += en8801s.o
26 obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
27 obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
28 obj-$(CONFIG_AT803X_PHY) += at803x.o
29Index: drivers/net/phy/en8801s.c
30===================================================================
31--- /dev/null
32+++ b/drivers/net/phy/en8801s.c
33@@ -0,0 +1,394 @@
34+// SPDX-License-Identifier: GPL-2.0
35+/* FILE NAME: airoha.c
36+ * PURPOSE:
37+ * EN8801S phy driver for Linux
38+ * NOTES:
39+ *
40+ */
41+
42+/* INCLUDE FILE DECLARATIONS
43+ */
44+
45+#include <linux/kernel.h>
46+#include <linux/string.h>
47+#include <linux/errno.h>
48+#include <linux/unistd.h>
49+#include <linux/interrupt.h>
50+#include <linux/init.h>
51+#include <linux/delay.h>
52+#include <linux/netdevice.h>
53+#include <linux/etherdevice.h>
54+#include <linux/skbuff.h>
55+#include <linux/spinlock.h>
56+#include <linux/mm.h>
57+#include <linux/module.h>
58+#include <linux/mii.h>
59+#include <linux/ethtool.h>
60+#include <linux/phy.h>
61+#include <linux/delay.h>
62+
63+//#include <linux/bitfield.h>
64+#include <linux/uaccess.h>
65+#include <linux/version.h>
66+
67+#include "en8801s.h"
68+
69+/* #define TEST_BOARD */
70+
71+MODULE_DESCRIPTION("Airoha EN8801S PHY drivers");
72+MODULE_AUTHOR("Airoha");
73+MODULE_LICENSE("GPL");
74+
75+static int preSpeed = 0;
76+/************************************************************************
77+* F U N C T I O N S
78+************************************************************************/
79+unsigned int mdiobus_write45(struct mii_bus *bus, u32 port, u32 devad, u32 reg, u16 val)
80+{
81+ mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG, devad);
82+ mdiobus_write(bus, port, MII_MMD_ADDR_DATA_REG, reg);
83+ mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad);
84+ mdiobus_write(bus, port, MII_MMD_ADDR_DATA_REG, val);
85+ return 0;
86+}
87+
88+unsigned int mdiobus_read45(struct mii_bus *bus, u32 port, u32 devad, u32 reg, u32 *read_data)
89+{
90+ mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG, devad);
91+ mdiobus_write(bus, port, MII_MMD_ADDR_DATA_REG, reg);
92+ mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad);
93+ *read_data = mdiobus_read(bus, port, MII_MMD_ADDR_DATA_REG);
94+ return 0;
95+}
96+
97+/* Airoha MII read function */
98+unsigned int ecnt_mii_cl22_read(struct mii_bus *ebus, unsigned int phy_addr,unsigned int phy_register,unsigned int *read_data)
99+{
100+ *read_data = mdiobus_read(ebus, phy_addr, phy_register);
101+ return 0;
102+}
103+
104+/* Airoha MII write function */
105+unsigned int ecnt_mii_cl22_write(struct mii_bus *ebus, unsigned int phy_addr, unsigned int phy_register,unsigned int write_data)
106+{
107+ mdiobus_write(ebus, phy_addr, phy_register, write_data);
108+ return 0;
109+}
110+
111+/* EN8801 PBUS write function */
112+void En8801_PbusRegWr(struct mii_bus *ebus, unsigned long pbus_address, unsigned long pbus_data)
113+{
114+ ecnt_mii_cl22_write(ebus, EN8801S_PBUS_PHY_ID, 0x1F, (unsigned int)(pbus_address >> 6));
115+ ecnt_mii_cl22_write(ebus, EN8801S_PBUS_PHY_ID, (unsigned int)((pbus_address >> 2) & 0xf), (unsigned int)(pbus_data & 0xFFFF));
116+ ecnt_mii_cl22_write(ebus, EN8801S_PBUS_PHY_ID, 0x10, (unsigned int)(pbus_data >> 16));
117+ return;
118+}
119+
120+/* EN8801 PBUS read function */
121+unsigned long En8801_PbusRegRd(struct mii_bus *ebus, unsigned long pbus_address)
122+{
123+ unsigned long pbus_data;
124+ unsigned int pbus_data_low, pbus_data_high;
125+
126+ ecnt_mii_cl22_write(ebus, EN8801S_PBUS_PHY_ID, 0x1F, (unsigned int)(pbus_address >> 6));
127+ ecnt_mii_cl22_read(ebus, EN8801S_PBUS_PHY_ID, (unsigned int)((pbus_address >> 2) & 0xf), &pbus_data_low);
128+ ecnt_mii_cl22_read(ebus, EN8801S_PBUS_PHY_ID, 0x10, &pbus_data_high);
129+ pbus_data = (pbus_data_high << 16) + pbus_data_low;
130+ return pbus_data;
131+}
132+
133+/* Use default PBUS_PHY_ID */
134+/* EN8801 PBUS write function */
135+void En8801_varPbusRegWr(struct mii_bus *ebus, unsigned long pbus_id,unsigned long pbus_address, unsigned long pbus_data)
136+{
137+ ecnt_mii_cl22_write(ebus, pbus_id, 0x1F, (unsigned int)(pbus_address >> 6));
138+ ecnt_mii_cl22_write(ebus, pbus_id, (unsigned int)((pbus_address >> 2) & 0xf), (unsigned int)(pbus_data & 0xFFFF));
139+ ecnt_mii_cl22_write(ebus, pbus_id, 0x10, (unsigned int)(pbus_data >> 16));
140+ return;
141+}
142+
143+/* EN8801 PBUS read function */
144+unsigned long En8801_varPbusRegRd(struct mii_bus *ebus, unsigned long pbus_id, unsigned long pbus_address)
145+{
146+ unsigned long pbus_data;
147+ unsigned int pbus_data_low, pbus_data_high;
148+
149+ ecnt_mii_cl22_write(ebus, pbus_id, 0x1F, (unsigned int)(pbus_address >> 6));
150+ ecnt_mii_cl22_read(ebus, pbus_id, (unsigned int)((pbus_address >> 2) & 0xf), &pbus_data_low);
151+ ecnt_mii_cl22_read(ebus, pbus_id, 0x10, &pbus_data_high);
152+ pbus_data = (pbus_data_high << 16) + pbus_data_low;
153+ return pbus_data;
154+}
155+
156+/* EN8801 Token Ring Write function */
157+void En8801_TR_RegWr(struct mii_bus *ebus, unsigned long tr_address, unsigned long tr_data)
158+{
159+ ecnt_mii_cl22_write(ebus, EN8801S_MDIO_PHY_ID, 0x1F, 0x52b5); /* page select */
160+ ecnt_mii_cl22_write(ebus, EN8801S_MDIO_PHY_ID, 0x11, (unsigned int)(tr_data & 0xffff));
161+ ecnt_mii_cl22_write(ebus, EN8801S_MDIO_PHY_ID, 0x12, (unsigned int)(tr_data >> 16));
162+ ecnt_mii_cl22_write(ebus, EN8801S_MDIO_PHY_ID, 0x10, (unsigned int)(tr_address | TrReg_WR));
163+ ecnt_mii_cl22_write(ebus, EN8801S_MDIO_PHY_ID, 0x1F, 0x0); /* page resetore */
164+ return;
165+}
166+
167+/* EN8801 Token Ring Read function */
168+unsigned long En8801_TR_RegRd(struct mii_bus *ebus, unsigned long tr_address)
169+{
170+ unsigned long tr_data;
171+ unsigned int tr_data_low, tr_data_high;
172+
173+ ecnt_mii_cl22_write(ebus, EN8801S_MDIO_PHY_ID, 0x1F, 0x52b5); /* page select */
174+ ecnt_mii_cl22_write(ebus, EN8801S_MDIO_PHY_ID, 0x10, (unsigned int)(tr_address | TrReg_RD));
175+ ecnt_mii_cl22_read(ebus, EN8801S_MDIO_PHY_ID, 0x11, &tr_data_low);
176+ ecnt_mii_cl22_read(ebus, EN8801S_MDIO_PHY_ID, 0x12, &tr_data_high);
177+ ecnt_mii_cl22_write(ebus, EN8801S_MDIO_PHY_ID, 0x1F, 0x0); /* page resetore */
178+ tr_data = (tr_data_high << 16) + tr_data_low;
179+ return tr_data;
180+}
181+
182+static int en8801s_config_init(struct phy_device *phydev)
183+{
184+ gephy_all_REG_LpiReg1Ch GPHY_RG_LPI_1C;
185+ gephy_all_REG_dev1Eh_reg324h GPHY_RG_1E_324;
186+ gephy_all_REG_dev1Eh_reg012h GPHY_RG_1E_012;
187+ gephy_all_REG_dev1Eh_reg017h GPHY_RG_1E_017;
188+ unsigned long pbus_data;
189+ unsigned int pbusAddress;
190+ u32 reg_value;
191+ int retry;
192+ struct mii_bus *mbus;
193+
194+ #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
195+ mbus = phydev->bus;
196+ #else
197+ mbus = phydev->mdio.bus;
198+ #endif
199+
200+ pbusAddress = EN8801S_PBUS_DEFAULT_ID;
201+ retry = MAX_OUI_CHECK;
202+ while(1)
203+ {
204+ pbus_data = En8801_varPbusRegRd(mbus, pbusAddress, EN8801S_RG_ETHER_PHY_OUI); /* PHY OUI */
205+ if(EN8801S_PBUS_OUI == pbus_data)
206+ {
207+ pbus_data = En8801_varPbusRegRd(mbus, pbusAddress, EN8801S_RG_SMI_ADDR); /* SMI ADDR */
208+ pbus_data = (pbus_data & 0xffff0000) | (unsigned long)(EN8801S_PBUS_PHY_ID << 8) | (unsigned long)(EN8801S_MDIO_PHY_ID );
209+ printk("[Airoha] EN8801S SMI_ADDR=%lx (renew)\n", pbus_data);
210+ En8801_varPbusRegWr(mbus, pbusAddress, EN8801S_RG_SMI_ADDR, pbus_data);
211+ En8801_varPbusRegWr(mbus, EN8801S_PBUS_PHY_ID, EN8801S_RG_BUCK_CTL, 0x03);
212+ mdelay(10);
213+ break;
214+ }
215+ else
216+ {
217+ pbusAddress = EN8801S_PBUS_PHY_ID;
218+ }
219+ retry --;
220+ if (0 == retry)
221+ {
222+ printk("[Airoha] EN8801S probe fail !\n");
223+ return 0;
224+ }
225+ }
226+
227+ reg_value = (En8801_PbusRegRd(mbus, EN8801S_RG_LTR_CTL) & 0xfffffffc) | 0x10 | (EN8801S_RX_POLARITY << 1) | EN8801S_TX_POLARITY;
228+ En8801_PbusRegWr(mbus, 0xcf8, reg_value);
229+ mdelay(10);
230+ reg_value &= 0xffffffef;
231+ En8801_PbusRegWr(mbus, 0xcf8, reg_value);
232+
233+ retry = MAX_RETRY;
234+ while (1)
235+ {
236+ mdelay(10);
237+ reg_value = phy_read(phydev, MII_PHYSID2);
238+ if (reg_value == EN8801S_PHY_ID2)
239+ {
240+ break; /* wait GPHY ready */
241+ }
242+ retry--;
243+ if (0 == retry)
244+ {
245+ printk("[Airoha] EN8801S initialize fail !\n");
246+ return 0;
247+ }
248+ }
249+ /* Software Reset PHY */
250+ reg_value = phy_read(phydev, MII_BMCR);
251+ reg_value |= BMCR_RESET;
252+ phy_write(phydev, MII_BMCR, reg_value);
253+ retry = MAX_RETRY;
254+ do
255+ {
256+ mdelay(10);
257+ reg_value = phy_read(phydev, MII_BMCR);
258+ retry--;
259+ if (0 == retry)
260+ {
261+ printk("[Airoha] EN8801S reset fail !\n");
262+ return 0;
263+ }
264+ } while (reg_value & BMCR_RESET);
265+
266+ En8801_PbusRegWr(mbus, 0x0600, 0x0c000c00);
267+ En8801_PbusRegWr(mbus, 0x10, 0xD801);
268+ En8801_PbusRegWr(mbus, 0x0, 0x9140);
269+
270+ En8801_PbusRegWr(mbus, 0x0A14, 0x0003);
271+ En8801_PbusRegWr(mbus, 0x0600, 0x0c000c00);
272+ /* Set FCM control */
273+ En8801_PbusRegWr(mbus, 0x1404, 0x004b);
274+ En8801_PbusRegWr(mbus, 0x140c, 0x0007);
275+ /* Set GPHY Perfomance*/
276+ /* Token Ring */
277+ En8801_TR_RegWr(mbus, RgAddr_PMA_01h, 0x6FB90A);
278+ En8801_TR_RegWr(mbus, RgAddr_PMA_18h, 0x0E2F00);
279+ En8801_TR_RegWr(mbus, RgAddr_DSPF_06h, 0x2EBAEF);
280+ En8801_TR_RegWr(mbus, RgAddr_DSPF_11h, 0x040001);
281+ En8801_TR_RegWr(mbus, RgAddr_DSPF_03h, 0x000004);
282+ En8801_TR_RegWr(mbus, RgAddr_DSPF_1Ch, 0x003210);
283+ En8801_TR_RegWr(mbus, RgAddr_DSPF_14h, 0x00024A);
284+ En8801_TR_RegWr(mbus, RgAddr_DSPF_0Ch, 0x00704D);
285+ En8801_TR_RegWr(mbus, RgAddr_DSPF_0Dh, 0x02314F);
286+ En8801_TR_RegWr(mbus, RgAddr_DSPF_10h, 0x005010);
287+ En8801_TR_RegWr(mbus, RgAddr_DSPF_0Fh, 0x003028);
288+ En8801_TR_RegWr(mbus, RgAddr_TR_26h, 0x444444);
289+ En8801_TR_RegWr(mbus, RgAddr_R1000DEC_15h,0x0055A0);
290+ /* CL22 & CL45 */
291+ phy_write(phydev, 0x1f, 0x03);
292+ GPHY_RG_LPI_1C.DATA = phy_read(phydev, RgAddr_LpiReg1Ch);
293+ GPHY_RG_LPI_1C.DataBitField.smi_deton_th = 0x0C;
294+ phy_write(phydev, RgAddr_LpiReg1Ch, GPHY_RG_LPI_1C.DATA);
295+ phy_write(phydev, 0x1f, 0x0);
296+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x122, 0xffff);
297+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x234, 0x0180);
298+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x238, 0x0120);
299+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x120, 0x9014);
300+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x239, 0x0117);
301+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x14A, 0xEE20);
302+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x19B, 0x0111);
303+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1F, 0x268, 0x07F4);
304+
305+ mdiobus_read45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x324, &reg_value);
306+ GPHY_RG_1E_324.DATA=(u16)reg_value;
307+ GPHY_RG_1E_324.DataBitField.smi_det_deglitch_off = 0;
308+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x324, (u32)GPHY_RG_1E_324.DATA);
309+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x19E, 0xC2);
310+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x013, 0x0);
311+
312+ /* EFUSE */
313+ En8801_PbusRegWr(mbus, 0x1C08, 0x40000040);
314+ retry = MAX_RETRY;
315+ while (0 != retry)
316+ {
317+ mdelay(1);
318+ reg_value = En8801_PbusRegRd(mbus, 0x1C08);
319+ if ((reg_value & (1 << 30)) == 0)
320+ {
321+ break;
322+ }
323+ retry--;
324+ }
325+ reg_value = En8801_PbusRegRd(mbus, 0x1C38); /* RAW#2 */
326+ GPHY_RG_1E_012.DataBitField.da_tx_i2mpb_a_tbt = reg_value & 0x03f;
327+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x12, (u32)GPHY_RG_1E_012.DATA);
328+ GPHY_RG_1E_017.DataBitField.da_tx_i2mpb_b_tbt=(reg_value >> 8) & 0x03f;
329+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x12, (u32)GPHY_RG_1E_017.DATA);
330+
331+ En8801_PbusRegWr(mbus, 0x1C08, 0x40400040);
332+ retry = MAX_RETRY;
333+ while (0 != retry)
334+ {
335+ mdelay(1);
336+ reg_value = En8801_PbusRegRd(mbus, 0x1C08);
337+ if ((reg_value & (1 << 30)) == 0)
338+ {
339+ break;
340+ }
341+ retry--;
342+ }
343+ reg_value = En8801_PbusRegRd(mbus, 0x1C30); /* RAW#16 */
344+ GPHY_RG_1E_324.DataBitField.smi_det_deglitch_off = (reg_value >> 12) & 0x01;
345+ mdiobus_write45(mbus, EN8801S_MDIO_PHY_ID, 0x1E, 0x324, (u32)GPHY_RG_1E_324.DATA);
346+
347+ printk("[Airoha] EN8801S initialize OK ! (1.0.5)\n");
348+ return 0;
349+}
350+
351+static int en8801s_read_status(struct phy_device *phydev)
352+{
353+ int ret;
354+ struct mii_bus *mbus;
355+
356+ #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
357+ mbus = phydev->bus;
358+ #else
359+ mbus = phydev->mdio.bus;
360+ #endif
361+
362+ ret = genphy_read_status(phydev);
363+ if (LINK_DOWN == phydev->link) preSpeed =0;
364+
365+ if ((preSpeed != phydev->speed) && (LINK_UP == phydev->link))
366+ {
367+ preSpeed = phydev->speed;
368+ En8801_PbusRegWr(mbus, 0x0600, 0x0c000c00);
369+ if (SPEED_1000 == preSpeed)
370+ {
371+ En8801_PbusRegWr(mbus, 0x10, 0xD801);
372+ En8801_PbusRegWr(mbus, 0x0, 0x9140);
373+
374+ En8801_PbusRegWr(mbus, 0x0A14, 0x0003);
375+ En8801_PbusRegWr(mbus, 0x0600, 0x0c000c00);
376+ mdelay(2); /* delay 2 ms */
377+ En8801_PbusRegWr(mbus, 0x1404, 0x004b);
378+ En8801_PbusRegWr(mbus, 0x140c, 0x0007);
379+ }
380+ else if (SPEED_100 == preSpeed)
381+ {
382+ En8801_PbusRegWr(mbus, 0x10, 0xD401);
383+ En8801_PbusRegWr(mbus, 0x0, 0x9140);
384+
385+ En8801_PbusRegWr(mbus, 0x0A14, 0x0007);
386+ En8801_PbusRegWr(mbus, 0x0600, 0x0c11);
387+ mdelay(2); /* delay 2 ms */
388+ En8801_PbusRegWr(mbus, 0x1404, 0x0027);
389+ En8801_PbusRegWr(mbus, 0x140c, 0x0007);
390+ }
391+ else if (SPEED_10 == preSpeed)
392+ {
393+ En8801_PbusRegWr(mbus, 0x10, 0xD001);
394+ En8801_PbusRegWr(mbus, 0x0, 0x9140);
395+
396+ En8801_PbusRegWr(mbus, 0x0A14, 0x000b);
397+ En8801_PbusRegWr(mbus, 0x0600, 0x0c11);
398+ mdelay(2); /* delay 2 ms */
399+ En8801_PbusRegWr(mbus, 0x1404, 0x0027);
400+ En8801_PbusRegWr(mbus, 0x140c, 0x0007);
401+ }
402+ }
403+ return ret;
404+}
405+
406+static struct phy_driver Airoha_driver[] = {
407+{
408+ .phy_id = EN8801S_PHY_ID,
409+ .name = "Airoha EN8801S",
410+ .phy_id_mask = 0x0ffffff0,
411+ .features = PHY_GBIT_FEATURES,
412+ .config_init = en8801s_config_init,
413+ .config_aneg = genphy_config_aneg,
414+ .read_status = en8801s_read_status,
415+ .suspend = genphy_suspend,
416+ .resume = genphy_resume,
417+} };
418+
419+module_phy_driver(Airoha_driver);
420+
421+static struct mdio_device_id __maybe_unused Airoha_tbl[] = {
422+ { EN8801S_PHY_ID, 0x0ffffff0 },
423+ { }
424+};
425+
426+MODULE_DEVICE_TABLE(mdio, Airoha_tbl);
427+MODULE_LICENSE("GPL");
428Index: drivers/net/phy/en8801s.h
429===================================================================
430--- /dev/null
431+++ b/drivers/net/phy/en8801s.h
432@@ -0,0 +1,153 @@
433+// SPDX-License-Identifier: GPL-2.0
434+/* FILE NAME: airoha.h
435+ * PURPOSE:
436+ * Define EN8801S driver function
437+ *
438+ * NOTES:
439+ *
440+ */
441+
442+#ifndef __AIROHA_H
443+#define __AIROHA_H
444+
445+/* NAMING DECLARATIONS
446+ */
447+#define PHY_ADDRESS_RANGE 0x18
448+#define EN8801S_PBUS_DEFAULT_ID 0x1e
449+#define EN8801S_MDIO_PHY_ID 0x18 /* Range PHY_ADDRESS_RANGE .. 0x1e */
450+#define EN8801S_PBUS_PHY_ID (EN8801S_MDIO_PHY_ID + 1)
451+
452+#define EN8801S_RG_ETHER_PHY_OUI 0x19a4
453+#define EN8801S_RG_SMI_ADDR 0x19a8
454+#define EN8801S_RG_BUCK_CTL 0x1a20
455+#define EN8801S_RG_LTR_CTL 0x0cf8
456+
457+#define EN8801S_PBUS_OUI 0x17a5
458+#define EN8801S_PHY_ID1 0x03a2
459+#define EN8801S_PHY_ID2 0x9461
460+#define EN8801S_PHY_ID (unsigned long)((EN8801S_PHY_ID1 << 16) | EN8801S_PHY_ID2)
461+
462+#define DEV1E_REG013_VALUE 0
463+#define DEV1E_REG19E_VALUE 0xC2
464+#define DEV1E_REG324_VALUE 0x200
465+
466+#define TRUE 1
467+#define FALSE 0
468+#define LINK_UP 1
469+#define LINK_DOWN 0
470+
471+#if defined(TEST_BOARD)
472+#define EN8801S_TX_POLARITY 1
473+#define EN8801S_RX_POLARITY 0
474+#else
475+#define EN8801S_TX_POLARITY 0
476+#define EN8801S_RX_POLARITY 1 /* The ping default assignment is set to 1 */
477+#endif
478+
479+#define MAX_RETRY 5
480+#define MAX_OUI_CHECK 2
481+/* CL45 MDIO control */
482+#define MII_MMD_ACC_CTL_REG 0x0d
483+#define MII_MMD_ADDR_DATA_REG 0x0e
484+#define MMD_OP_MODE_DATA BIT(14)
485+
486+#define MAX_TRG_COUNTER 5
487+
488+/* CL22 Reg Support Page Select */
489+#define RgAddr_Reg1Fh 0x1f
490+#define CL22_Page_Reg 0x0000
491+#define CL22_Page_ExtReg 0x0001
492+#define CL22_Page_MiscReg 0x0002
493+#define CL22_Page_LpiReg 0x0003
494+#define CL22_Page_tReg 0x02A3
495+#define CL22_Page_TrReg 0x52B5
496+
497+/* CL45 Reg Support DEVID */
498+#define DEVID_03 0x03
499+#define DEVID_07 0x07
500+#define DEVID_1E 0x1E
501+#define DEVID_1F 0x1F
502+
503+/* TokenRing Reg Access */
504+#define TrReg_PKT_XMT_STA 0x8000
505+#define TrReg_WR 0x8000
506+#define TrReg_RD 0xA000
507+
508+#define RgAddr_LpiReg1Ch 0x1c
509+#define RgAddr_PMA_01h 0x0f82
510+#define RgAddr_PMA_18h 0x0fb0
511+#define RgAddr_DSPF_03h 0x1686
512+#define RgAddr_DSPF_06h 0x168c
513+#define RgAddr_DSPF_0Ch 0x1698
514+#define RgAddr_DSPF_0Dh 0x169a
515+#define RgAddr_DSPF_0Fh 0x169e
516+#define RgAddr_DSPF_10h 0x16a0
517+#define RgAddr_DSPF_11h 0x16a2
518+#define RgAddr_DSPF_14h 0x16a8
519+#define RgAddr_DSPF_1Ch 0x16b8
520+#define RgAddr_TR_26h 0x0ecc
521+#define RgAddr_R1000DEC_15h 0x03aa
522+
523+/* DATA TYPE DECLARATIONS
524+ */
525+typedef struct
526+{
527+ u16 DATA_Lo;
528+ u16 DATA_Hi;
529+}TR_DATA_T;
530+
531+typedef union
532+{
533+ struct
534+ {
535+ /* b[15:00] */
536+ u16 smi_deton_wt : 3;
537+ u16 smi_det_mdi_inv : 1;
538+ u16 smi_detoff_wt : 3;
539+ u16 smi_sigdet_debouncing_en : 1;
540+ u16 smi_deton_th : 6;
541+ u16 rsv_14 : 2;
542+ } DataBitField;
543+ u16 DATA;
544+} gephy_all_REG_LpiReg1Ch, *Pgephy_all_REG_LpiReg1Ch;
545+
546+typedef union
547+{
548+ struct
549+ {
550+ /* b[15:00] */
551+ u16 rg_smi_detcnt_max : 6;
552+ u16 rsv_6 : 2;
553+ u16 rg_smi_det_max_en : 1;
554+ u16 smi_det_deglitch_off : 1;
555+ u16 rsv_10 : 6;
556+ } DataBitField;
557+ u16 DATA;
558+} gephy_all_REG_dev1Eh_reg324h, *Pgephy_all_REG_dev1Eh_reg324h;
559+
560+typedef union
561+{
562+ struct
563+ {
564+ /* b[15:00] */
565+ u16 da_tx_i2mpb_a_tbt : 6;
566+ u16 rsv_6 : 4;
567+ u16 da_tx_i2mpb_a_gbe : 6;
568+ } DataBitField;
569+ u16 DATA;
570+} gephy_all_REG_dev1Eh_reg012h, *Pgephy_all_REG_dev1Eh_reg012h;
571+
572+typedef union
573+{
574+ struct
575+ {
576+ /* b[15:00] */
577+ u16 da_tx_i2mpb_b_tbt : 6;
578+ u16 rsv_6 : 2;
579+ u16 da_tx_i2mpb_b_gbe : 6;
580+ u16 rsv_14 : 2;
581+ } DataBitField;
582+ u16 DATA;
583+} gephy_all_REG_dev1Eh_reg017h, *Pgephy_all_REG_dev1Eh_reg017h;
584+
585+#endif /* End of __AIROHA_H */