developer | 12a4279 | 2023-07-29 05:30:55 +0800 | [diff] [blame] | 1 | From 111207da0d2d75ebc63ab569e461f689bab307e2 Mon Sep 17 00:00:00 2001 |
developer | 2324aa2 | 2023-04-12 11:30:15 +0800 | [diff] [blame] | 2 | From: "sujuan.chen" <sujuan.chen@mediatek.com> |
| 3 | Date: Thu, 6 Apr 2023 17:50:52 +0800 |
developer | 8f0d89b | 2023-07-28 07:16:44 +0800 | [diff] [blame] | 4 | Subject: [PATCH 2007/2009] wifi: mt76: mt7915: add ctxd support for mt7916 |
developer | 2324aa2 | 2023-04-12 11:30:15 +0800 | [diff] [blame] | 5 | |
| 6 | Signed-off-by: sujuan.chen <sujuan.chen@mediatek.com> |
| 7 | --- |
| 8 | mt7915/dma.c | 20 ++++++++++++++++++++ |
| 9 | mt7915/regs.h | 15 +++++++++++++++ |
| 10 | 2 files changed, 35 insertions(+) |
| 11 | |
| 12 | diff --git a/mt7915/dma.c b/mt7915/dma.c |
developer | 2157bf8 | 2023-06-26 02:27:49 +0800 | [diff] [blame] | 13 | index 326c8c8..f71ec55 100644 |
developer | 2324aa2 | 2023-04-12 11:30:15 +0800 | [diff] [blame] | 14 | --- a/mt7915/dma.c |
| 15 | +++ b/mt7915/dma.c |
| 16 | @@ -433,6 +433,26 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2) |
| 17 | if (is_mt7915(mdev)) |
| 18 | mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP, |
| 19 | MT_WFDMA0_EXT0_RXWB_KEEP); |
| 20 | + else { |
developer | 2157bf8 | 2023-06-26 02:27:49 +0800 | [diff] [blame] | 21 | + if ((mt76_rr(dev, MT_CBTOP_RESV) & 0xff) == 2) { |
developer | 2324aa2 | 2023-04-12 11:30:15 +0800 | [diff] [blame] | 22 | + mt76_set(dev, MT_WFDMA0_GLO_CFG, MT_WFDMA0_GLO_CFG_DUMMY_REG); |
| 23 | + mt76_set(dev, MT_WFDMA0_CTXD_CFG, FIELD_PREP(MT_WFDMA0_CTXD_TIMEOUT, 0xa)); |
| 24 | + } else { |
| 25 | + mt76_set(dev, MT_WFDMA0_CTXD_CFG, FIELD_PREP(MT_WFDMA0_CTXD_TIMEOUT, 0xff)); |
| 26 | + |
| 27 | + /*Delay tick set to 0xFFFF, which is about 3449us*/ |
| 28 | + mt76_wr(dev, MT_WFDMA_WED_DLY_INT_TICK, 0xffff); |
| 29 | + } |
| 30 | + |
| 31 | + mt76_clear(dev, MT_WFDMA0_CTXD_CFG, MT_WFDMA0_CTXD_CASCADE_NUM); |
| 32 | + |
| 33 | + mt76_set(dev, MT_WFDMA0_CTXD_CFG, |
| 34 | + FIELD_PREP(MT_WFDMA0_BAND0_CTXD_RING_IDX, 18) | |
| 35 | + FIELD_PREP(MT_WFDMA0_BAND1_CTXD_RING_IDX, 19) | |
| 36 | + MT_WFDMA0_BAND0_CTXD_EN | MT_WFDMA0_BAND1_CTXD_EN); |
| 37 | + |
| 38 | + mt76_set(dev, MT_WFDMA0_CFG_EXT, MT_WFDMA0_EXT_TX_FCTRL_MODE); |
| 39 | + } |
| 40 | } |
| 41 | } else { |
| 42 | mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED); |
| 43 | diff --git a/mt7915/regs.h b/mt7915/regs.h |
developer | 2157bf8 | 2023-06-26 02:27:49 +0800 | [diff] [blame] | 44 | index 44da7b8..bc963ac 100644 |
developer | 2324aa2 | 2023-04-12 11:30:15 +0800 | [diff] [blame] | 45 | --- a/mt7915/regs.h |
| 46 | +++ b/mt7915/regs.h |
developer | 2157bf8 | 2023-06-26 02:27:49 +0800 | [diff] [blame] | 47 | @@ -606,6 +606,7 @@ enum offs_rev { |
developer | 2324aa2 | 2023-04-12 11:30:15 +0800 | [diff] [blame] | 48 | #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) |
| 49 | #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) |
| 50 | #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) |
| 51 | +#define MT_WFDMA0_GLO_CFG_DUMMY_REG BIT(10) |
| 52 | #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) |
| 53 | #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) |
| 54 | #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) |
developer | 2157bf8 | 2023-06-26 02:27:49 +0800 | [diff] [blame] | 55 | @@ -615,6 +616,17 @@ enum offs_rev { |
developer | 2324aa2 | 2023-04-12 11:30:15 +0800 | [diff] [blame] | 56 | #define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0) |
| 57 | #define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10) |
| 58 | |
| 59 | +#define MT_WFDMA0_CFG_EXT MT_WFDMA0(0x2b4) |
| 60 | +#define MT_WFDMA0_EXT_TX_FCTRL_MODE BIT(28) |
| 61 | + |
| 62 | +#define MT_WFDMA0_CTXD_CFG MT_WFDMA0(0x2bc) |
| 63 | +#define MT_WFDMA0_BAND0_CTXD_EN BIT(0) |
| 64 | +#define MT_WFDMA0_BAND0_CTXD_RING_IDX GENMASK(5, 1) |
| 65 | +#define MT_WFDMA0_BAND1_CTXD_EN BIT(6) |
| 66 | +#define MT_WFDMA0_BAND1_CTXD_RING_IDX GENMASK(11, 7) |
| 67 | +#define MT_WFDMA0_CTXD_CASCADE_NUM GENMASK(15, 12) |
| 68 | +#define MT_WFDMA0_CTXD_TIMEOUT GENMASK(23, 16) |
| 69 | + |
| 70 | #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) |
| 71 | #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4) |
| 72 | #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8) |
developer | 2157bf8 | 2023-06-26 02:27:49 +0800 | [diff] [blame] | 73 | @@ -658,6 +670,8 @@ enum offs_rev { |
developer | 2324aa2 | 2023-04-12 11:30:15 +0800 | [diff] [blame] | 74 | #define MT_WFDMA_WED_RING_CONTROL_TX1 GENMASK(12, 8) |
| 75 | #define MT_WFDMA_WED_RING_CONTROL_RX1 GENMASK(20, 16) |
| 76 | |
| 77 | +#define MT_WFDMA_WED_DLY_INT_TICK MT_WFDMA_EXT_CSR_PHYS(0x38) |
| 78 | + |
| 79 | #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR_PHYS(0x44) |
| 80 | #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) |
| 81 | |
developer | 2157bf8 | 2023-06-26 02:27:49 +0800 | [diff] [blame] | 82 | @@ -1186,6 +1200,7 @@ enum offs_rev { |
developer | 2324aa2 | 2023-04-12 11:30:15 +0800 | [diff] [blame] | 83 | |
| 84 | #define MT_HW_BOUND 0x70010020 |
| 85 | #define MT_HW_REV 0x70010204 |
| 86 | +#define MT_CBTOP_RESV 0x70010210 |
| 87 | #define MT_WF_SUBSYS_RST 0x70002600 |
| 88 | |
| 89 | /* PCIE MAC */ |
| 90 | -- |
| 91 | 2.18.0 |
| 92 | |