developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * switch_fun.c: switch function sets |
| 3 | */ |
| 4 | #include <stdio.h> |
| 5 | #include <stdlib.h> |
| 6 | #include <unistd.h> |
| 7 | #include <string.h> |
| 8 | #include <stdbool.h> |
| 9 | #include <sys/ioctl.h> |
| 10 | #include <sys/socket.h> |
| 11 | #include <linux/if.h> |
| 12 | #include <stdbool.h> |
| 13 | #include <time.h> |
developer | 997ed6b | 2024-03-26 14:03:42 +0800 | [diff] [blame] | 14 | #include <errno.h> |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 15 | |
| 16 | #include "switch_extend.h" |
| 17 | #include "switch_netlink.h" |
| 18 | #include "switch_ioctl.h" |
| 19 | #include "switch_fun.h" |
| 20 | |
| 21 | #define leaky_bucket 0 |
| 22 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 23 | struct switch_func_s mt753x_switch_func = { |
| 24 | .pf_table_dump = table_dump, |
| 25 | .pf_table_clear = table_clear, |
| 26 | .pf_switch_reset = switch_reset, |
| 27 | .pf_doArlAging = doArlAging, |
| 28 | .pf_read_mib_counters = read_mib_counters, |
| 29 | .pf_clear_mib_counters = clear_mib_counters, |
| 30 | .pf_read_output_queue_counters = read_output_queue_counters, |
| 31 | .pf_read_free_page_counters = read_free_page_counters, |
| 32 | .pf_rate_control = rate_control, |
| 33 | .pf_igress_rate_set = ingress_rate_set, |
| 34 | .pf_egress_rate_set = egress_rate_set, |
| 35 | .pf_table_add = table_add, |
| 36 | .pf_table_del_fid = table_del_fid, |
| 37 | .pf_table_del_vid = table_del_vid, |
| 38 | .pf_table_search_mac_fid = table_search_mac_fid, |
| 39 | .pf_table_search_mac_vid = table_search_mac_vid, |
| 40 | .pf_global_set_mac_fc = global_set_mac_fc, |
| 41 | .pf_set_mac_pfc = set_mac_pfc, |
| 42 | .pf_qos_sch_select = qos_sch_select, |
| 43 | .pf_qos_set_base = qos_set_base, |
| 44 | .pf_qos_wfq_set_weight = qos_wfq_set_weight, |
| 45 | .pf_qos_set_portpri = qos_set_portpri, |
| 46 | .pf_qos_set_dscppri = qos_set_dscppri, |
| 47 | .pf_qos_pri_mapping_queue = qos_pri_mapping_queue, |
| 48 | .pf_doStp = doStp, |
| 49 | .pf_sip_dump = sip_dump, |
| 50 | .pf_sip_add = sip_add, |
| 51 | .pf_sip_del = sip_del, |
| 52 | .pf_sip_clear = sip_clear, |
| 53 | .pf_dip_dump = dip_dump, |
| 54 | .pf_dip_add = dip_add, |
| 55 | .pf_dip_del = dip_del, |
| 56 | .pf_dip_clear = dip_clear, |
| 57 | .pf_set_mirror_to = set_mirror_to, |
| 58 | .pf_set_mirror_from = set_mirror_from, |
| 59 | .pf_doMirrorEn = doMirrorEn, |
| 60 | .pf_doMirrorPortBased = doMirrorPortBased, |
| 61 | .pf_acl_dip_add = acl_dip_add, |
| 62 | .pf_acl_dip_modify = acl_dip_modify, |
| 63 | .pf_acl_dip_pppoe = acl_dip_pppoe, |
| 64 | .pf_acl_dip_trtcm = acl_dip_trtcm, |
| 65 | .pf_acl_dip_meter = acl_dip_meter, |
| 66 | .pf_acl_mac_add = acl_mac_add, |
| 67 | .pf_acl_ethertype = acl_ethertype, |
| 68 | .pf_acl_sp_add = acl_sp_add, |
| 69 | .pf_acl_l4_add = acl_l4_add, |
| 70 | .pf_acl_port_enable = acl_port_enable, |
| 71 | .pf_acl_table_add = acl_table_add, |
| 72 | .pf_acl_mask_table_add = acl_mask_table_add, |
| 73 | .pf_acl_rule_table_add = acl_rule_table_add, |
| 74 | .pf_acl_rate_table_add = acl_rate_table_add, |
| 75 | .pf_vlan_dump = vlan_dump, |
| 76 | .pf_vlan_set = vlan_set, |
| 77 | .pf_vlan_clear = vlan_clear, |
| 78 | .pf_doVlanSetVid = doVlanSetVid, |
| 79 | .pf_doVlanSetPvid = doVlanSetPvid, |
| 80 | .pf_doVlanSetAccFrm = doVlanSetAccFrm, |
| 81 | .pf_doVlanSetPortAttr = doVlanSetPortAttr, |
| 82 | .pf_doVlanSetPortMode = doVlanSetPortMode, |
| 83 | .pf_doVlanSetEgressTagPCR = doVlanSetEgressTagPCR, |
| 84 | .pf_doVlanSetEgressTagPVC = doVlanSetEgressTagPVC, |
| 85 | .pf_igmp_on = igmp_on, |
| 86 | .pf_igmp_off = igmp_off, |
| 87 | .pf_igmp_enable = igmp_enable, |
| 88 | .pf_igmp_disable = igmp_disable, |
| 89 | .pf_collision_pool_enable = collision_pool_enable, |
| 90 | .pf_collision_pool_mac_dump = collision_pool_mac_dump, |
| 91 | .pf_collision_pool_dip_dump = collision_pool_dip_dump, |
| 92 | .pf_collision_pool_sip_dump = collision_pool_sip_dump, |
| 93 | .pf_pfc_get_rx_counter = pfc_get_rx_counter, |
| 94 | .pf_pfc_get_tx_counter = pfc_get_tx_counter, |
| 95 | .pf_eee_enable = eee_enable, |
| 96 | .pf_eee_dump = eee_dump, |
| 97 | }; |
| 98 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 99 | static int getnext(char *src, int separator, char *dest) |
| 100 | { |
| 101 | char *c; |
| 102 | int len; |
| 103 | |
| 104 | if ((src == NULL) || (dest == NULL)) |
| 105 | return -1; |
| 106 | |
| 107 | c = strchr(src, separator); |
| 108 | if (c == NULL) |
| 109 | return -1; |
| 110 | |
| 111 | len = c - src; |
| 112 | strncpy(dest, src, len); |
| 113 | dest[len] = '\0'; |
| 114 | return len + 1; |
| 115 | } |
| 116 | |
| 117 | static int str_to_ip(unsigned int *ip, char *str) |
| 118 | { |
| 119 | int i; |
| 120 | int len; |
| 121 | char *ptr = str; |
| 122 | char buf[128]; |
| 123 | unsigned char c[4]; |
| 124 | |
| 125 | for (i = 0; i < 3; ++i) { |
| 126 | if ((len = getnext(ptr, '.', buf)) == -1) |
| 127 | return 1; |
| 128 | c[i] = atoi(buf); |
| 129 | ptr += len; |
| 130 | } |
| 131 | c[3] = atoi(ptr); |
| 132 | *ip = (c[0] << 24) + (c[1] << 16) + (c[2] << 8) + c[3]; |
| 133 | return 0; |
| 134 | } |
| 135 | |
| 136 | /*convert IP address from number to string */ |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 137 | static void ip_to_str(char *str, size_t size, unsigned int ip) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 138 | { |
| 139 | unsigned char *ptr = (unsigned char *)&ip; |
| 140 | unsigned char c[4]; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 141 | int ret; |
| 142 | |
| 143 | if (str == NULL || size == 0) { |
| 144 | printf("convert IP address failed\n"); |
| 145 | return; |
| 146 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 147 | |
| 148 | c[0] = *(ptr); |
| 149 | c[1] = *(ptr + 1); |
| 150 | c[2] = *(ptr + 2); |
| 151 | c[3] = *(ptr + 3); |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 152 | |
| 153 | ret = snprintf(str, size, "%d.%d.%d.%d", c[3], c[2], c[1], c[0]); |
| 154 | if (ret < 0) { |
| 155 | printf("Encoding error in snprintf\n"); |
| 156 | return; |
| 157 | } else if ((size_t)ret >= size) { |
| 158 | printf("Required size %d, provided size %zu\n", ret, size); |
| 159 | return; |
| 160 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | int reg_read(unsigned int offset, unsigned int *value) |
| 164 | { |
| 165 | int ret = -1; |
| 166 | |
| 167 | if (nl_init_flag == true) { |
| 168 | ret = reg_read_netlink(attres, offset, value); |
| 169 | } else { |
| 170 | if (attres->dev_id == -1) |
| 171 | ret = reg_read_ioctl(offset, value); |
| 172 | } |
| 173 | if (ret < 0) { |
| 174 | printf("Read fail\n"); |
| 175 | *value = 0; |
| 176 | return ret; |
| 177 | } |
| 178 | |
| 179 | return 0; |
| 180 | } |
| 181 | |
| 182 | int reg_write(unsigned int offset, unsigned int value) |
| 183 | { |
| 184 | int ret = -1; |
| 185 | |
| 186 | if (nl_init_flag == true) { |
| 187 | ret = reg_write_netlink(attres, offset, value); |
| 188 | } else { |
| 189 | if (attres->dev_id == -1) |
| 190 | ret = reg_write_ioctl(offset, value); |
| 191 | } |
| 192 | if (ret < 0) { |
| 193 | printf("Write fail\n"); |
| 194 | exit_free(); |
| 195 | exit(0); |
| 196 | } |
| 197 | return 0; |
| 198 | } |
| 199 | |
| 200 | int mii_mgr_read(unsigned int port_num, unsigned int reg, unsigned int *value) |
| 201 | { |
| 202 | int ret; |
| 203 | |
| 204 | if (port_num > 31) { |
| 205 | printf("Invalid Port or PHY addr \n"); |
| 206 | return -1; |
| 207 | } |
| 208 | |
| 209 | if (nl_init_flag == true) |
| 210 | ret = phy_cl22_read_netlink(attres, port_num, reg, value); |
| 211 | else |
| 212 | ret = mii_mgr_cl22_read_ioctl(port_num, reg, value); |
| 213 | |
| 214 | if (ret < 0) { |
developer | 06979e4 | 2021-05-28 16:48:10 +0800 | [diff] [blame] | 215 | printf("Phy cl22 read fail\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 216 | exit_free(); |
| 217 | exit(0); |
| 218 | } |
| 219 | |
| 220 | return 0; |
| 221 | } |
| 222 | |
| 223 | int mii_mgr_write(unsigned int port_num, unsigned int reg, unsigned int value) |
| 224 | { |
| 225 | int ret; |
| 226 | |
| 227 | if (port_num > 31) { |
| 228 | printf("Invalid Port or PHY addr \n"); |
| 229 | return -1; |
| 230 | } |
| 231 | |
| 232 | if (nl_init_flag == true) |
| 233 | ret = phy_cl22_write_netlink(attres, port_num, reg, value); |
| 234 | else |
| 235 | ret = mii_mgr_cl22_write_ioctl(port_num, reg, value); |
| 236 | |
| 237 | if (ret < 0) { |
developer | 06979e4 | 2021-05-28 16:48:10 +0800 | [diff] [blame] | 238 | printf("Phy cl22 write fail\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 239 | exit_free(); |
| 240 | exit(0); |
| 241 | } |
| 242 | |
| 243 | return 0; |
| 244 | } |
| 245 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 246 | int mii_mgr_c45_read(unsigned int port_num, unsigned int dev, unsigned int reg, |
| 247 | unsigned int *value) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 248 | { |
| 249 | int ret; |
| 250 | |
| 251 | if (port_num > 31) { |
| 252 | printf("Invalid Port or PHY addr \n"); |
| 253 | return -1; |
| 254 | } |
| 255 | |
| 256 | if (nl_init_flag == true) |
| 257 | ret = phy_cl45_read_netlink(attres, port_num, dev, reg, value); |
| 258 | else |
| 259 | ret = mii_mgr_cl45_read_ioctl(port_num, dev, reg, value); |
| 260 | |
| 261 | if (ret < 0) { |
developer | 06979e4 | 2021-05-28 16:48:10 +0800 | [diff] [blame] | 262 | printf("Phy cl45 read fail\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 263 | exit_free(); |
| 264 | exit(0); |
| 265 | } |
| 266 | |
| 267 | return 0; |
| 268 | } |
| 269 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 270 | int mii_mgr_c45_write(unsigned int port_num, unsigned int dev, unsigned int reg, |
| 271 | unsigned int value) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 272 | { |
| 273 | int ret; |
| 274 | |
| 275 | if (port_num > 31) { |
| 276 | printf("Invalid Port or PHY addr \n"); |
| 277 | return -1; |
| 278 | } |
| 279 | |
| 280 | if (nl_init_flag == true) |
| 281 | ret = phy_cl45_write_netlink(attres, port_num, dev, reg, value); |
| 282 | else |
| 283 | ret = mii_mgr_cl45_write_ioctl(port_num, dev, reg, value); |
| 284 | |
| 285 | if (ret < 0) { |
developer | 06979e4 | 2021-05-28 16:48:10 +0800 | [diff] [blame] | 286 | printf("Phy cl45 write fail\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 287 | exit_free(); |
| 288 | exit(0); |
| 289 | } |
| 290 | |
| 291 | return 0; |
| 292 | } |
| 293 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 294 | int phy_dump(int phy_addr) |
| 295 | { |
| 296 | int ret; |
| 297 | |
| 298 | if (nl_init_flag == true) |
| 299 | ret = phy_dump_netlink(attres, phy_addr); |
| 300 | else |
| 301 | ret = phy_dump_ioctl(phy_addr); |
| 302 | |
| 303 | if (ret < 0) { |
| 304 | printf("Phy dump fail\n"); |
| 305 | exit_free(); |
| 306 | exit(0); |
| 307 | } |
| 308 | |
| 309 | return 0; |
| 310 | } |
| 311 | |
| 312 | void phy_crossover(int argc, char *argv[]) |
| 313 | { |
| 314 | unsigned int port_num = strtoul(argv[2], NULL, 10); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 315 | unsigned int value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 316 | int ret; |
| 317 | |
| 318 | if (port_num > 4) { |
| 319 | printf("invaild value, port_name:0~4\n"); |
| 320 | return; |
| 321 | } |
| 322 | |
| 323 | if (nl_init_flag == true) |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 324 | ret = |
| 325 | phy_cl45_read_netlink(attres, port_num, 0x1E, |
| 326 | MT7530_T10_TEST_CONTROL, &value); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 327 | else |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 328 | ret = |
| 329 | mii_mgr_cl45_read_ioctl(port_num, 0x1E, |
| 330 | MT7530_T10_TEST_CONTROL, &value); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 331 | if (ret < 0) { |
| 332 | printf("phy_cl45 read fail\n"); |
| 333 | exit_free(); |
| 334 | exit(0); |
| 335 | } |
| 336 | |
| 337 | printf("mii_mgr_cl45:"); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 338 | printf("Read: port#=%d, device=0x%x, reg=0x%x, value=0x%x\n", port_num, |
| 339 | 0x1E, MT7530_T10_TEST_CONTROL, value); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 340 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 341 | if (!strncmp(argv[3], "auto", 5)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 342 | value &= (~(0x3 << 3)); |
| 343 | } else if (!strncmp(argv[3], "mdi", 4)) { |
| 344 | value &= (~(0x3 << 3)); |
| 345 | value |= (0x2 << 3); |
| 346 | } else if (!strncmp(argv[3], "mdix", 5)) { |
| 347 | value |= (0x3 << 3); |
| 348 | } else { |
| 349 | printf("invaild parameter\n"); |
| 350 | return; |
| 351 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 352 | printf("Write: port#=%d, device=0x%x, reg=0x%x. value=0x%x\n", port_num, |
| 353 | 0x1E, MT7530_T10_TEST_CONTROL, value); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 354 | |
| 355 | if (nl_init_flag == true) |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 356 | ret = |
| 357 | phy_cl45_write_netlink(attres, port_num, 0x1E, |
| 358 | MT7530_T10_TEST_CONTROL, value); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 359 | else |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 360 | ret = |
| 361 | mii_mgr_cl45_write_ioctl(port_num, 0x1E, |
| 362 | MT7530_T10_TEST_CONTROL, value); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 363 | |
| 364 | if (ret < 0) { |
| 365 | printf("phy_cl45 write fail\n"); |
| 366 | exit_free(); |
| 367 | exit(0); |
| 368 | } |
| 369 | } |
| 370 | |
| 371 | int rw_phy_token_ring(int argc, char *argv[]) |
| 372 | { |
| 373 | int ch_addr, node_addr, data_addr; |
| 374 | unsigned int tr_reg_control; |
| 375 | unsigned int val_l = 0; |
| 376 | unsigned int val_h = 0; |
| 377 | unsigned int port_num; |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 378 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 379 | |
| 380 | if (argc < 4) |
| 381 | return -1; |
| 382 | |
| 383 | if (argv[2][0] == 'r') { |
| 384 | if (argc != 7) |
| 385 | return -1; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 386 | mii_mgr_write(0, 0x1f, 0x52b5); // r31 = 0x52b5 |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 387 | |
| 388 | errno = 0; |
| 389 | port_num = strtoul(argv[3], &endptr, 10); |
| 390 | if (errno != 0 || *endptr != '\0' || port_num > MAX_PORT) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 391 | printf("Illegal port index and port:0~6\n"); |
| 392 | return -1; |
| 393 | } |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 394 | |
| 395 | errno = 0; |
| 396 | ch_addr = strtoul(argv[4], &endptr, 10); |
| 397 | if (errno != 0 || *endptr != '\0') |
| 398 | goto error; |
| 399 | |
| 400 | errno = 0; |
| 401 | node_addr = strtoul(argv[5], &endptr, 16); |
| 402 | if (errno != 0 || *endptr != '\0') |
| 403 | goto error; |
| 404 | |
| 405 | errno = 0; |
| 406 | data_addr = strtoul(argv[6], &endptr, 16); |
| 407 | if (errno != 0 || *endptr != '\0') |
| 408 | goto error; |
| 409 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 410 | printf("port = %x, ch_addr = %x, node_addr=%x, data_addr=%x\n", |
| 411 | port_num, ch_addr, node_addr, data_addr); |
| 412 | tr_reg_control = |
| 413 | (1 << 15) | (1 << 13) | (ch_addr << 11) | (node_addr << 7) | |
| 414 | (data_addr << 1); |
| 415 | mii_mgr_write(port_num, 16, tr_reg_control); // r16 = tr_reg_control |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 416 | mii_mgr_read(port_num, 17, &val_l); |
| 417 | mii_mgr_read(port_num, 18, &val_h); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 418 | printf |
| 419 | ("switch trreg read tr_reg_control=%x, value_H=%x, value_L=%x\n", |
| 420 | tr_reg_control, val_h, val_l); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 421 | } else if (argv[2][0] == 'w') { |
| 422 | if (argc != 9) |
| 423 | return -1; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 424 | mii_mgr_write(0, 0x1f, 0x52b5); // r31 = 0x52b5 |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 425 | |
| 426 | errno = 0; |
| 427 | port_num = strtoul(argv[3], &endptr, 10); |
| 428 | if (errno != 0 || *endptr != '\0' || port_num > MAX_PORT) { |
| 429 | printf("Illegal port index and port:0~6\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 430 | return -1; |
| 431 | } |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 432 | |
| 433 | errno = 0; |
| 434 | ch_addr = strtoul(argv[4], &endptr, 10); |
| 435 | if (errno != 0 || *endptr != '\0') |
| 436 | goto error; |
| 437 | |
| 438 | errno = 0; |
| 439 | node_addr = strtoul(argv[5], &endptr, 16); |
| 440 | if (errno != 0 || *endptr != '\0') |
| 441 | goto error; |
| 442 | |
| 443 | errno = 0; |
| 444 | data_addr = strtoul(argv[6], &endptr, 16); |
| 445 | if (errno != 0 || *endptr != '\0') |
| 446 | goto error; |
| 447 | |
| 448 | errno = 0; |
| 449 | val_h = strtoul(argv[7], &endptr, 16); |
| 450 | if (errno != 0 || *endptr != '\0') |
| 451 | goto error; |
| 452 | |
| 453 | errno = 0; |
| 454 | val_l = strtoul(argv[8], &endptr, 16); |
| 455 | if (errno != 0 || *endptr != '\0') |
| 456 | goto error; |
| 457 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 458 | printf("port = %x, ch_addr = %x, node_addr=%x, data_addr=%x\n", |
| 459 | port_num, ch_addr, node_addr, data_addr); |
| 460 | tr_reg_control = |
| 461 | (1 << 15) | (0 << 13) | (ch_addr << 11) | (node_addr << 7) | |
| 462 | (data_addr << 1); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 463 | mii_mgr_write(port_num, 17, val_l); |
| 464 | mii_mgr_write(port_num, 18, val_h); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 465 | mii_mgr_write(port_num, 16, tr_reg_control); // r16 = tr_reg_control |
| 466 | printf |
| 467 | ("switch trreg Write tr_reg_control=%x, value_H=%x, value_L=%x\n", |
| 468 | tr_reg_control, val_h, val_l); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 469 | } else |
| 470 | return -1; |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 471 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 472 | return 0; |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 473 | |
| 474 | error: |
| 475 | printf("\n**Illegal parameters\n"); |
| 476 | return -1; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 477 | } |
| 478 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 479 | void write_acl_table(unsigned char tbl_idx, unsigned int vawd1, |
| 480 | unsigned int vawd2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 481 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 482 | unsigned int value = 0, reg = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 483 | unsigned int max_index; |
| 484 | |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 485 | if (chip_name == 0x7531 || chip_name == 0x7988) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 486 | max_index = 256; |
| 487 | else |
| 488 | max_index = 64; |
| 489 | |
| 490 | printf("Pattern_acl_tbl_idx:%d\n", tbl_idx); |
| 491 | |
| 492 | if (tbl_idx >= max_index) { |
| 493 | printf(HELP_ACL_ACL_TBL_ADD); |
| 494 | return; |
| 495 | } |
| 496 | |
| 497 | reg = REG_VTCR_ADDR; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 498 | while (1) { // wait until not busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 499 | reg_read(reg, &value); |
| 500 | if ((value & REG_VTCR_BUSY_MASK) == 0) { |
| 501 | break; |
| 502 | } |
| 503 | } |
| 504 | reg_write(REG_VAWD1_ADDR, vawd1); |
| 505 | printf("write reg: %x, value: %x\n", REG_VAWD1_ADDR, vawd1); |
| 506 | reg_write(REG_VAWD2_ADDR, vawd2); |
| 507 | printf("write reg: %x, value: %x\n", REG_VAWD2_ADDR, vawd2); |
| 508 | reg = REG_VTCR_ADDR; |
| 509 | value = REG_VTCR_BUSY_MASK | (0x05 << REG_VTCR_FUNC_OFFT) | tbl_idx; |
| 510 | reg_write(reg, value); |
| 511 | printf("write reg: %x, value: %x\n", reg, value); |
| 512 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 513 | while (1) { // wait until not busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 514 | reg_read(reg, &value); |
| 515 | if ((value & REG_VTCR_BUSY_MASK) == 0) |
| 516 | break; |
| 517 | } |
| 518 | } |
| 519 | |
| 520 | void acl_table_add(int argc, char *argv[]) |
| 521 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 522 | unsigned int vawd1 = 0, vawd2 = 0; |
| 523 | unsigned char tbl_idx = 0; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 524 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 525 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 526 | errno = 0; |
| 527 | tbl_idx = strtoul(argv[3], &endptr, 10); |
| 528 | if (errno != 0 || *endptr != '\0') { |
| 529 | printf("Error: wrong ACL rule table index\n"); |
| 530 | return; |
| 531 | } |
| 532 | |
| 533 | errno = 0; |
| 534 | vawd1 = strtoul(argv[4], &endptr, 16); |
| 535 | if (errno != 0 || *endptr != '\0') { |
| 536 | printf("Error: wrong ACL rule table write data 1\n"); |
| 537 | return; |
| 538 | } |
| 539 | |
| 540 | errno = 0; |
| 541 | vawd2 = strtoul(argv[5], &endptr, 16); |
| 542 | if (errno != 0 || *endptr != '\0') { |
| 543 | printf("Error: wrong ACL rule table write data 2\n"); |
| 544 | return; |
| 545 | } |
| 546 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 547 | write_acl_table(tbl_idx, vawd1, vawd2); |
| 548 | } |
| 549 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 550 | void write_acl_mask_table(unsigned char tbl_idx, unsigned int vawd1, |
| 551 | unsigned int vawd2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 552 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 553 | unsigned int value = 0, reg = 0; |
| 554 | unsigned int max_index = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 555 | |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 556 | if (chip_name == 0x7531 || chip_name == 0x7988) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 557 | max_index = 128; |
| 558 | else |
| 559 | max_index = 32; |
| 560 | |
| 561 | printf("Rule_mask_tbl_idx:%d\n", tbl_idx); |
| 562 | |
| 563 | if (tbl_idx >= max_index) { |
| 564 | printf(HELP_ACL_MASK_TBL_ADD); |
| 565 | return; |
| 566 | } |
| 567 | reg = REG_VTCR_ADDR; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 568 | while (1) { // wait until not busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 569 | reg_read(reg, &value); |
| 570 | if ((value & REG_VTCR_BUSY_MASK) == 0) |
| 571 | break; |
| 572 | } |
| 573 | reg_write(REG_VAWD1_ADDR, vawd1); |
| 574 | printf("write reg: %x, value: %x\n", REG_VAWD1_ADDR, vawd1); |
| 575 | reg_write(REG_VAWD2_ADDR, vawd2); |
| 576 | printf("write reg: %x, value: %x\n", REG_VAWD2_ADDR, vawd2); |
| 577 | reg = REG_VTCR_ADDR; |
| 578 | value = REG_VTCR_BUSY_MASK | (0x09 << REG_VTCR_FUNC_OFFT) | tbl_idx; |
| 579 | reg_write(reg, value); |
| 580 | printf("write reg: %x, value: %x\n", reg, value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 581 | while (1) { // wait until not busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 582 | reg_read(reg, &value); |
| 583 | if ((value & REG_VTCR_BUSY_MASK) == 0) |
| 584 | break; |
| 585 | } |
| 586 | } |
| 587 | |
| 588 | void acl_mask_table_add(int argc, char *argv[]) |
| 589 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 590 | unsigned int vawd1 = 0, vawd2 = 0; |
| 591 | unsigned char tbl_idx = 0; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 592 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 593 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 594 | errno = 0; |
| 595 | tbl_idx = strtoul(argv[3], &endptr, 10); |
| 596 | if (errno != 0 || *endptr != '\0') { |
| 597 | printf("Error: wrong ACL mask table index\n"); |
| 598 | return; |
| 599 | } |
| 600 | |
| 601 | errno = 0; |
| 602 | vawd1 = strtoul(argv[4], &endptr, 16); |
| 603 | if (errno != 0 || *endptr != '\0') { |
| 604 | printf("Error: wrong ACL mask table write data 1\n"); |
| 605 | return; |
| 606 | } |
| 607 | |
| 608 | errno = 0; |
| 609 | vawd2 = strtoul(argv[5], &endptr, 16); |
| 610 | if (errno != 0 || *endptr != '\0') { |
| 611 | printf("Error: wrong ACL mask table write data 2\n"); |
| 612 | return; |
| 613 | } |
| 614 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 615 | write_acl_mask_table(tbl_idx, vawd1, vawd2); |
| 616 | } |
| 617 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 618 | void write_acl_rule_table(unsigned char tbl_idx, unsigned int vawd1, |
| 619 | unsigned int vawd2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 620 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 621 | unsigned int value = 0, reg = 0; |
| 622 | unsigned int max_index = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 623 | |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 624 | if (chip_name == 0x7531 || chip_name == 0x7988) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 625 | max_index = 128; |
| 626 | else |
| 627 | max_index = 32; |
| 628 | |
| 629 | printf("Rule_control_tbl_idx:%d\n", tbl_idx); |
| 630 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 631 | if (tbl_idx >= max_index) { /* Check the input parameters is right or not. */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 632 | printf(HELP_ACL_RULE_TBL_ADD); |
| 633 | return; |
| 634 | } |
| 635 | reg = REG_VTCR_ADDR; |
| 636 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 637 | while (1) { // wait until not busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 638 | reg_read(reg, &value); |
| 639 | if ((value & REG_VTCR_BUSY_MASK) == 0) { |
| 640 | break; |
| 641 | } |
| 642 | } |
| 643 | reg_write(REG_VAWD1_ADDR, vawd1); |
| 644 | printf("write reg: %x, value: %x\n", REG_VAWD1_ADDR, vawd1); |
| 645 | reg_write(REG_VAWD2_ADDR, vawd2); |
| 646 | printf("write reg: %x, value: %x\n", REG_VAWD2_ADDR, vawd2); |
| 647 | reg = REG_VTCR_ADDR; |
| 648 | value = REG_VTCR_BUSY_MASK | (0x0B << REG_VTCR_FUNC_OFFT) | tbl_idx; |
| 649 | reg_write(reg, value); |
| 650 | printf("write reg: %x, value: %x\n", reg, value); |
| 651 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 652 | while (1) { // wait until not busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 653 | reg_read(reg, &value); |
| 654 | if ((value & REG_VTCR_BUSY_MASK) == 0) { |
| 655 | break; |
| 656 | } |
| 657 | } |
| 658 | } |
| 659 | |
| 660 | void acl_rule_table_add(int argc, char *argv[]) |
| 661 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 662 | unsigned int vawd1 = 0, vawd2 = 0; |
| 663 | unsigned char tbl_idx = 0; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 664 | char *endptr; |
| 665 | |
| 666 | errno = 0; |
| 667 | tbl_idx = strtoul(argv[3], &endptr, 10); |
| 668 | if (errno != 0 || *endptr != '\0') { |
| 669 | printf("Error: wrong ACL rule control table index\n"); |
| 670 | return; |
| 671 | } |
| 672 | |
| 673 | errno = 0; |
| 674 | vawd1 = strtoul(argv[4], &endptr, 16); |
| 675 | if (errno != 0 || *endptr != '\0') { |
| 676 | printf("Error: wrong ACL rule control table write data 1\n"); |
| 677 | return; |
| 678 | } |
| 679 | |
| 680 | errno = 0; |
| 681 | vawd2 = strtoul(argv[5], &endptr, 16); |
| 682 | if (errno != 0 || *endptr != '\0') { |
| 683 | printf("Error: wrong ACL rule control table write data 2\n"); |
| 684 | return; |
| 685 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 686 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 687 | write_acl_rule_table(tbl_idx, vawd1, vawd2); |
| 688 | } |
| 689 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 690 | void write_rate_table(unsigned char tbl_idx, unsigned int vawd1, |
| 691 | unsigned int vawd2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 692 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 693 | unsigned int value = 0, reg = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 694 | unsigned int max_index = 32; |
| 695 | |
| 696 | printf("Rule_action_tbl_idx:%d\n", tbl_idx); |
| 697 | |
| 698 | if (tbl_idx >= max_index) { |
| 699 | printf(HELP_ACL_RATE_TBL_ADD); |
| 700 | return; |
| 701 | } |
| 702 | |
| 703 | reg = REG_VTCR_ADDR; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 704 | while (1) { // wait until not busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 705 | reg_read(reg, &value); |
| 706 | if ((value & REG_VTCR_BUSY_MASK) == 0) |
| 707 | break; |
| 708 | } |
| 709 | |
| 710 | reg_write(REG_VAWD1_ADDR, vawd1); |
| 711 | printf("write reg: %x, value: %x\n", REG_VAWD1_ADDR, vawd1); |
| 712 | reg_write(REG_VAWD2_ADDR, vawd2); |
| 713 | printf("write reg: %x, value: %x\n", REG_VAWD2_ADDR, vawd2); |
| 714 | reg = REG_VTCR_ADDR; |
| 715 | value = REG_VTCR_BUSY_MASK | (0x0D << REG_VTCR_FUNC_OFFT) | tbl_idx; |
| 716 | reg_write(reg, value); |
| 717 | printf("write reg: %x, value: %x\n", reg, value); |
| 718 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 719 | while (1) { // wait until not busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 720 | reg_read(reg, &value); |
| 721 | if ((value & REG_VTCR_BUSY_MASK) == 0) |
| 722 | break; |
| 723 | } |
| 724 | } |
| 725 | |
| 726 | void acl_rate_table_add(int argc, char *argv[]) |
| 727 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 728 | unsigned int vawd1 = 0, vawd2 = 0; |
| 729 | unsigned char tbl_idx = 0; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 730 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 731 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 732 | errno = 0; |
| 733 | tbl_idx = strtoul(argv[3], &endptr, 10); |
| 734 | if (errno != 0 || *endptr != '\0') { |
| 735 | printf("Error: wrong ACL rate control table index\n"); |
| 736 | return; |
| 737 | } |
| 738 | |
| 739 | errno = 0; |
| 740 | vawd1 = strtoul(argv[4], &endptr, 16); |
| 741 | if (errno != 0 || *endptr != '\0') { |
| 742 | printf("Error: wrong ACL rate control table write data 1\n"); |
| 743 | return; |
| 744 | } |
| 745 | |
| 746 | errno = 0; |
| 747 | vawd2 = strtoul(argv[5], &endptr, 16); |
| 748 | if (errno != 0 || *endptr != '\0') { |
| 749 | printf("Error: wrong ACL rate control table write data 2\n"); |
| 750 | return; |
| 751 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 752 | |
| 753 | write_rate_table(tbl_idx, vawd1, vawd2); |
| 754 | } |
| 755 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 756 | void write_trTCM_table(unsigned char tbl_idx, unsigned int vawd1, |
| 757 | unsigned int vawd2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 758 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 759 | unsigned int value = 0, reg = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 760 | unsigned int max_index = 32; |
| 761 | |
| 762 | printf("trTCM_tbl_idx:%d\n", tbl_idx); |
| 763 | |
| 764 | if (tbl_idx >= max_index) { |
| 765 | printf(HELP_ACL_TRTCM_TBL_ADD); |
| 766 | return; |
| 767 | } |
| 768 | |
| 769 | reg = REG_VTCR_ADDR; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 770 | while (1) { // wait until not busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 771 | reg_read(reg, &value); |
| 772 | if ((value & REG_VTCR_BUSY_MASK) == 0) |
| 773 | break; |
| 774 | } |
| 775 | |
| 776 | reg_write(REG_VAWD1_ADDR, vawd1); |
| 777 | printf("write reg: %x, value: %x\n", REG_VAWD1_ADDR, vawd1); |
| 778 | reg_write(REG_VAWD2_ADDR, vawd2); |
| 779 | printf("write reg: %x, value: %x\n", REG_VAWD2_ADDR, vawd2); |
| 780 | reg = REG_VTCR_ADDR; |
| 781 | value = REG_VTCR_BUSY_MASK | (0x07 << REG_VTCR_FUNC_OFFT) | tbl_idx; |
| 782 | reg_write(reg, value); |
| 783 | printf("write reg: %x, value: %x\n", reg, value); |
| 784 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 785 | while (1) { // wait until not busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 786 | reg_read(reg, &value); |
| 787 | if ((value & REG_VTCR_BUSY_MASK) == 0) |
| 788 | break; |
| 789 | } |
| 790 | } |
| 791 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 792 | int acl_parameters_pre_del(int len1, int len2, int argc, char *argv[], |
| 793 | int *port) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 794 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 795 | int i = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 796 | |
| 797 | *port = 0; |
| 798 | if (argc < len1) { |
| 799 | printf("insufficient arguments!\n"); |
| 800 | return -1; |
| 801 | } |
| 802 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 803 | if (len2 == 12) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 804 | if (!argv[4] || strlen(argv[4]) != len2) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 805 | printf |
| 806 | ("The [%s] format error, should be of length %d\n", |
| 807 | argv[4], len2); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 808 | return -1; |
| 809 | } |
| 810 | } |
| 811 | |
| 812 | if (!argv[5] || strlen(argv[5]) != 8) { |
| 813 | printf("portsmap format error, should be of length 7\n"); |
| 814 | return -1; |
| 815 | } |
| 816 | |
| 817 | for (i = 0; i < 7; i++) { |
| 818 | if (argv[5][i] != '0' && argv[5][i] != '1') { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 819 | printf |
| 820 | ("portmap format error, should be of combination of 0 or 1\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 821 | return -1; |
| 822 | } |
| 823 | *port += (argv[5][i] - '0') * (1 << i); |
| 824 | } |
| 825 | return 0; |
| 826 | } |
| 827 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 828 | void acl_compare_pattern(int ports, int comparion, int base, int word, |
| 829 | unsigned char table_index) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 830 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 831 | unsigned int value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 832 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 833 | comparion |= 0xffff0000; //compare mask |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 834 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 835 | value = ports << 8; //w_port_map |
| 836 | value |= 0x1 << 19; //enable |
| 837 | value |= base << 16; //mac header |
| 838 | value |= word << 1; //word offset |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 839 | |
| 840 | write_acl_table(table_index, comparion, value); |
| 841 | } |
| 842 | |
| 843 | void acl_mac_add(int argc, char *argv[]) |
| 844 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 845 | unsigned int value = 0; |
| 846 | int ports = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 847 | char tmpstr[5]; |
| 848 | int ret; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 849 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 850 | |
| 851 | ret = acl_parameters_pre_del(6, 12, argc, argv, &ports); |
| 852 | if (ret < 0) |
| 853 | return; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 854 | /* Set pattern */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 855 | strncpy(tmpstr, argv[4], 4); |
| 856 | tmpstr[4] = '\0'; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 857 | errno = 0; |
| 858 | value = strtoul(tmpstr, &endptr, 16); |
| 859 | if (errno != 0 || *endptr != '\0') |
| 860 | goto error; |
| 861 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 862 | acl_compare_pattern(ports, value, 0x0, 0, 0); |
| 863 | |
| 864 | strncpy(tmpstr, argv[4] + 4, 4); |
| 865 | tmpstr[4] = '\0'; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 866 | errno = 0; |
| 867 | value = strtoul(tmpstr, &endptr, 16); |
| 868 | if (errno != 0 || *endptr != '\0') |
| 869 | goto error; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 870 | acl_compare_pattern(ports, value, 0x0, 1, 1); |
| 871 | |
| 872 | strncpy(tmpstr, argv[4] + 8, 4); |
| 873 | tmpstr[4] = '\0'; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 874 | errno = 0; |
| 875 | value = strtoul(tmpstr, &endptr, 16); |
| 876 | if (errno != 0 || *endptr != '\0') |
| 877 | goto error; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 878 | acl_compare_pattern(ports, value, 0x0, 2, 2); |
| 879 | |
| 880 | //set mask |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 881 | write_acl_mask_table(0, 0x7, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 882 | |
| 883 | //set action |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 884 | value = 0x7; //drop |
| 885 | value |= 1 << 28; //acl intterupt enable |
| 886 | value |= 1 << 27; //acl hit count |
| 887 | value |= 2 << 24; //acl hit count group index (0~3) |
| 888 | write_acl_rule_table(0, value, 0); |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 889 | return; |
| 890 | |
| 891 | error: |
| 892 | printf("Error: string converting\n"); |
| 893 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 894 | } |
| 895 | |
| 896 | void acl_dip_meter(int argc, char *argv[]) |
| 897 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 898 | unsigned int value = 0, ip_value = 0, meter = 0; |
| 899 | int ports = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 900 | int ret; |
| 901 | |
| 902 | ip_value = 0; |
| 903 | ret = acl_parameters_pre_del(7, -1, argc, argv, &ports); |
| 904 | if (ret < 0) |
| 905 | return; |
| 906 | |
| 907 | str_to_ip(&ip_value, argv[4]); |
| 908 | //set pattern |
| 909 | value = (ip_value >> 16); |
| 910 | acl_compare_pattern(ports, value, 0x2, 0x8, 0); |
| 911 | |
| 912 | //set pattern |
| 913 | value = (ip_value & 0xffff); |
| 914 | acl_compare_pattern(ports, value, 0x2, 0x9, 1); |
| 915 | |
| 916 | //set mask |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 917 | write_acl_mask_table(0, 0x3, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 918 | |
| 919 | //set action |
| 920 | meter = strtoul(argv[6], NULL, 0); |
| 921 | if (((chip_name == 0x7530) && (meter > 1000000)) || |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 922 | ((chip_name == 0x7531) && (meter > 2500000)) || |
| 923 | ((chip_name == 0x7988) && (meter > 4000000))) { |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 924 | printf("\n**Illegal meter input, and 7530: 0~1000000Kpbs, 7531: 0~2500000Kpbs, 7988: 0~4000000Kpbs**\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 925 | return; |
| 926 | } |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 927 | if (((chip_name == 0x7531 || chip_name == 0x7988) && (meter > 1000000))) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 928 | reg_read(0xc, &value); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 929 | value |= 0x1 << 30; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 930 | reg_write(0xC, value); |
| 931 | printf("AGC: 0x%x\n", value); |
| 932 | value = meter / 1000; //uint is 1Mbps |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 933 | } else { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 934 | reg_read(0xc, &value); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 935 | value &= ~(0x1 << 30); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 936 | reg_write(0xC, value); |
| 937 | printf("AGC: 0x%x\n", value); |
| 938 | value = meter >> 6; //uint is 64Kbps |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 939 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 940 | value |= 0x1 << 15; //enable rate control |
| 941 | printf("Acl rate control:0x%x\n", value); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 942 | write_rate_table(0, value, 0); |
| 943 | } |
| 944 | |
| 945 | void acl_dip_trtcm(int argc, char *argv[]) |
| 946 | { |
| 947 | unsigned int value, value2, ip_value; |
| 948 | unsigned int CIR, CBS, PIR, PBS; |
| 949 | int ports; |
| 950 | int ret; |
| 951 | |
| 952 | ip_value = 0; |
| 953 | ret = acl_parameters_pre_del(10, -1, argc, argv, &ports); |
| 954 | if (ret < 0) |
| 955 | return; |
| 956 | |
| 957 | str_to_ip(&ip_value, argv[4]); |
| 958 | //set pattern |
| 959 | value = (ip_value >> 16); |
| 960 | acl_compare_pattern(ports, value, 0x2, 0x8, 0); |
| 961 | |
| 962 | //set pattern |
| 963 | value = (ip_value & 0xffff); |
| 964 | acl_compare_pattern(ports, value, 0x2, 0x9, 1); |
| 965 | |
| 966 | //set CBS PBS |
| 967 | CIR = strtoul(argv[6], NULL, 0); |
| 968 | CBS = strtoul(argv[7], NULL, 0); |
| 969 | PIR = strtoul(argv[8], NULL, 0); |
| 970 | PBS = strtoul(argv[9], NULL, 0); |
| 971 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 972 | if (CIR > 65535 * 64 || CBS > 65535 || PIR > 65535 * 64 || PBS > 65535) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 973 | printf("\n**Illegal input parameters**\n"); |
| 974 | return; |
| 975 | } |
| 976 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 977 | value = CBS << 16; //bit16~31 |
| 978 | value |= PBS; //bit0~15 |
| 979 | //value |= 1;//valid |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 980 | CIR = CIR >> 6; |
| 981 | PIR = PIR >> 6; |
| 982 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 983 | value2 = CIR << 16; //bit16~31 |
| 984 | value2 |= PIR; //bit0~15 |
| 985 | write_trTCM_table(0, value, value2); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 986 | |
| 987 | //set pattern |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 988 | write_acl_mask_table(0, 0x3, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 989 | |
| 990 | //set action |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 991 | value = 0x1 << (11 + 1); //TrTCM green meter#0 Low drop |
| 992 | value |= 0x2 << (8 + 1); //TrTCM yellow meter#0 Med drop |
| 993 | value |= 0x3 << (5 + 1); //TrTCM red meter#0 Hig drop |
| 994 | value |= 0x1 << 0; //TrTCM drop pcd select |
| 995 | write_acl_rule_table(0, 0, value); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 996 | } |
| 997 | |
| 998 | void acl_ethertype(int argc, char *argv[]) |
| 999 | { |
| 1000 | unsigned int value, ethertype; |
| 1001 | int ports; |
| 1002 | int ret; |
| 1003 | |
| 1004 | ret = acl_parameters_pre_del(6, -1, argc, argv, &ports); |
| 1005 | if (ret < 0) |
| 1006 | return; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1007 | printf("ports:0x%x\n", ports); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1008 | ethertype = strtoul(argv[4], NULL, 16); |
| 1009 | //set pattern |
| 1010 | value = ethertype; |
| 1011 | acl_compare_pattern(ports, value, 0x0, 0x6, 0); |
| 1012 | |
| 1013 | //set pattern |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1014 | write_acl_mask_table(0, 0x1, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1015 | |
| 1016 | //set action(drop) |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1017 | value = 0x7; //default. Nodrop |
| 1018 | value |= 1 << 28; //acl intterupt enable |
| 1019 | value |= 1 << 27; //acl hit count |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1020 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1021 | write_acl_rule_table(0, value, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1022 | } |
| 1023 | |
| 1024 | void acl_dip_modify(int argc, char *argv[]) |
| 1025 | { |
| 1026 | unsigned int value, ip_value; |
| 1027 | int ports; |
| 1028 | int priority; |
| 1029 | int ret; |
| 1030 | |
| 1031 | ip_value = 0; |
| 1032 | priority = strtoul(argv[6], NULL, 16); |
| 1033 | if (priority < 0 || priority > 7) { |
| 1034 | printf("\n**Illegal priority value!**\n"); |
| 1035 | return; |
| 1036 | } |
| 1037 | |
| 1038 | ret = acl_parameters_pre_del(6, -1, argc, argv, &ports); |
| 1039 | if (ret < 0) |
| 1040 | return; |
| 1041 | |
| 1042 | str_to_ip(&ip_value, argv[4]); |
| 1043 | //set pattern |
| 1044 | value = (ip_value >> 16); |
| 1045 | acl_compare_pattern(ports, value, 0x2, 0x8, 0); |
| 1046 | |
| 1047 | //set pattern |
| 1048 | value = (ip_value & 0xffff); |
| 1049 | acl_compare_pattern(ports, value, 0x2, 0x9, 1); |
| 1050 | |
| 1051 | //set pattern |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1052 | write_acl_mask_table(0, 0x3, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1053 | |
| 1054 | //set action |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1055 | value = 0x0; //default. Nodrop |
| 1056 | value |= 1 << 28; //acl intterupt enable |
| 1057 | value |= 1 << 27; //acl hit count |
| 1058 | value |= priority << 4; //acl UP |
| 1059 | write_acl_rule_table(0, value, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1060 | } |
| 1061 | |
| 1062 | void acl_dip_pppoe(int argc, char *argv[]) |
| 1063 | { |
| 1064 | unsigned int value, ip_value; |
| 1065 | int ports; |
| 1066 | int ret; |
| 1067 | |
| 1068 | ip_value = 0; |
| 1069 | ret = acl_parameters_pre_del(6, -1, argc, argv, &ports); |
| 1070 | if (ret < 0) |
| 1071 | return; |
| 1072 | |
| 1073 | str_to_ip(&ip_value, argv[4]); |
| 1074 | //set pattern |
| 1075 | value = (ip_value >> 16); |
| 1076 | acl_compare_pattern(ports, value, 0x2, 0x8, 0); |
| 1077 | |
| 1078 | //set pattern |
| 1079 | value = (ip_value & 0xffff); |
| 1080 | acl_compare_pattern(ports, value, 0x2, 0x9, 1); |
| 1081 | |
| 1082 | //set pattern |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1083 | write_acl_mask_table(0, 0x3, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1084 | |
| 1085 | //set action |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1086 | value = 0x0; //default. Nodrop |
| 1087 | value |= 1 << 28; //acl intterupt enable |
| 1088 | value |= 1 << 27; //acl hit count |
| 1089 | value |= 1 << 20; //pppoe header remove |
| 1090 | value |= 1 << 21; //SA MAC SWAP |
| 1091 | value |= 1 << 22; //DA MAC SWAP |
| 1092 | write_acl_rule_table(0, value, 7); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1093 | } |
| 1094 | |
| 1095 | void acl_dip_add(int argc, char *argv[]) |
| 1096 | { |
| 1097 | unsigned int value, ip_value; |
| 1098 | int ports; |
| 1099 | int ret; |
| 1100 | |
| 1101 | ip_value = 0; |
| 1102 | ret = acl_parameters_pre_del(6, -1, argc, argv, &ports); |
| 1103 | if (ret < 0) |
| 1104 | return; |
| 1105 | |
| 1106 | str_to_ip(&ip_value, argv[4]); |
| 1107 | //set pattern |
| 1108 | value = (ip_value >> 16); |
| 1109 | acl_compare_pattern(ports, value, 0x2, 0x8, 0); |
| 1110 | |
| 1111 | //set pattern |
| 1112 | value = (ip_value & 0xffff); |
| 1113 | acl_compare_pattern(ports, value, 0x2, 0x9, 1); |
| 1114 | |
| 1115 | //set pattern |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1116 | write_acl_mask_table(0, 0x3, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1117 | |
| 1118 | //set action |
| 1119 | //value = 0x0; //default |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1120 | value = 0x7; //drop |
| 1121 | value |= 1 << 28; //acl intterupt enable |
| 1122 | value |= 1 << 27; //acl hit count |
| 1123 | value |= 2 << 24; //acl hit count group index (0~3) |
| 1124 | write_acl_rule_table(0, value, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1125 | } |
| 1126 | |
| 1127 | void acl_l4_add(int argc, char *argv[]) |
| 1128 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1129 | unsigned int value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1130 | int ports; |
| 1131 | int ret; |
| 1132 | |
| 1133 | ret = acl_parameters_pre_del(6, -1, argc, argv, &ports); |
| 1134 | if (ret < 0) |
| 1135 | return; |
| 1136 | |
| 1137 | //set pattern |
| 1138 | value = strtoul(argv[4], NULL, 16); |
| 1139 | acl_compare_pattern(ports, value, 0x5, 0x0, 0); |
| 1140 | |
| 1141 | //set rue mask |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1142 | write_acl_mask_table(0, 0x1, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1143 | //set action |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1144 | value = 0x7; //drop |
| 1145 | //value |= 1;//valid |
| 1146 | write_acl_rule_table(0, value, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1147 | } |
| 1148 | |
| 1149 | void acl_sp_add(int argc, char *argv[]) |
| 1150 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1151 | unsigned int value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1152 | int ports; |
| 1153 | int ret; |
| 1154 | |
| 1155 | ret = acl_parameters_pre_del(6, -1, argc, argv, &ports); |
| 1156 | if (ret < 0) |
| 1157 | return; |
| 1158 | //set pattern |
| 1159 | value = strtoul(argv[4], NULL, 0); |
| 1160 | acl_compare_pattern(ports, value, 0x4, 0x0, 0); |
| 1161 | |
| 1162 | //set rue mask |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1163 | write_acl_mask_table(0, 0x1, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1164 | |
| 1165 | //set action |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1166 | value = 0x7; //drop |
| 1167 | //value |= 1;//valid |
| 1168 | write_acl_rule_table(0, value, 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1169 | } |
| 1170 | |
| 1171 | void acl_port_enable(int argc, char *argv[]) |
| 1172 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1173 | unsigned int value = 0, reg = 0; |
| 1174 | unsigned char acl_port = 0, acl_en = 0; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 1175 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1176 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 1177 | errno = 0; |
| 1178 | acl_port = strtoul(argv[3], &endptr, 10); |
| 1179 | if (errno != 0 || *endptr != '\0' || acl_port > MAX_PORT) { |
| 1180 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 1181 | return; |
| 1182 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1183 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 1184 | errno = 0; |
| 1185 | acl_en = strtoul(argv[4], &endptr, 10); |
| 1186 | if (errno != 0 || *endptr != '\0' || acl_en > 1) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1187 | printf(HELP_ACL_SETPORTEN); |
| 1188 | return; |
| 1189 | } |
| 1190 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 1191 | printf("acl_port:%d, acl_en:%d\n", acl_port, acl_en); |
| 1192 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1193 | reg = REG_PCR_P0_ADDR + (0x100 * acl_port); // 0x2004[10] |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1194 | reg_read(reg, &value); |
| 1195 | value &= (~REG_PORT_ACL_EN_MASK); |
| 1196 | value |= (acl_en << REG_PORT_ACL_EN_OFFT); |
| 1197 | |
| 1198 | printf("write reg: %x, value: %x\n", reg, value); |
| 1199 | reg_write(reg, value); |
| 1200 | } |
| 1201 | |
| 1202 | static void dip_dump_internal(int type) |
| 1203 | { |
| 1204 | unsigned int i, j, value, mac, mac2, value2; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1205 | char tmpstr[16] = { 0 }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1206 | int table_size = 0; |
| 1207 | int hit_value1 = 0; |
| 1208 | int hit_value2 = 0; |
| 1209 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1210 | if (type == GENERAL_TABLE) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1211 | table_size = 0x800; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1212 | reg_write(REG_ATC_ADDR, 0x8104); //dip search command |
| 1213 | } else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1214 | table_size = 0x40; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1215 | reg_write(REG_ATC_ADDR, 0x811c); //dip search command |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1216 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1217 | printf |
| 1218 | ("hash port(0:6) rsp_cnt flag timer dip-address ATRD\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1219 | for (i = 0; i < table_size; i++) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1220 | while (1) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1221 | reg_read(REG_ATC_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1222 | if (type == GENERAL_TABLE) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1223 | hit_value1 = value & (0x1 << 13); |
| 1224 | hit_value2 = 1; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1225 | } else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1226 | hit_value1 = value & (0x1 << 13); |
| 1227 | hit_value2 = value & (0x1 << 28); |
| 1228 | } |
| 1229 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1230 | if (hit_value1 && hit_value2) { //search_rdy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1231 | reg_read(REG_ATRD_ADDR, &value2); |
| 1232 | //printf("REG_ATRD_ADDR=0x%x\n\r",value2); |
| 1233 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1234 | printf("%03x: ", (value >> 16) & 0xfff); //hash_addr_lu |
| 1235 | j = (value2 >> 4) & 0xff; //r_port_map |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1236 | printf("%c", (j & 0x01) ? '1' : '-'); |
| 1237 | printf("%c", (j & 0x02) ? '1' : '-'); |
| 1238 | printf("%c", (j & 0x04) ? '1' : '-'); |
| 1239 | printf("%c ", (j & 0x08) ? '1' : '-'); |
| 1240 | printf("%c", (j & 0x10) ? '1' : '-'); |
| 1241 | printf("%c", (j & 0x20) ? '1' : '-'); |
| 1242 | printf("%c", (j & 0x40) ? '1' : '-'); |
| 1243 | |
| 1244 | reg_read(REG_TSRA2_ADDR, &mac2); |
| 1245 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1246 | printf(" 0x%4x", (mac2 & 0xffff)); //RESP_CNT |
| 1247 | printf(" 0x%2x", ((mac2 >> 16) & 0xff)); //RESP_FLAG |
| 1248 | printf(" %3d", ((mac2 >> 24) & 0xff)); //RESP_TIMER |
| 1249 | //printf(" %4d", (value2 >> 24) & 0xff); //r_age_field |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1250 | reg_read(REG_TSRA1_ADDR, &mac); |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 1251 | ip_to_str(tmpstr, sizeof(tmpstr), mac); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1252 | printf(" %s", tmpstr); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1253 | printf(" 0x%8x\n", value2); //ATRD |
| 1254 | //printf("%04x", ((mac2 >> 16) & 0xffff)); |
| 1255 | //printf(" %c\n", (((value2 >> 20) & 0x03)== 0x03)? 'y':'-'); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1256 | if (value & 0x4000) { |
| 1257 | printf("end of table %d\n", i); |
| 1258 | return; |
| 1259 | } |
| 1260 | break; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1261 | } else if (value & 0x4000) { //at_table_end |
| 1262 | printf("found the last entry %d (not ready)\n", |
| 1263 | i); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1264 | return; |
| 1265 | } |
| 1266 | usleep(5000); |
| 1267 | } |
| 1268 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1269 | if (type == GENERAL_TABLE) |
| 1270 | reg_write(REG_ATC_ADDR, 0x8105); //search for next dip address |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1271 | else |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1272 | reg_write(REG_ATC_ADDR, 0x811d); //search for next dip address |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1273 | usleep(5000); |
| 1274 | } |
| 1275 | } |
| 1276 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1277 | void dip_dump(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1278 | { |
| 1279 | dip_dump_internal(GENERAL_TABLE); |
| 1280 | |
| 1281 | } |
| 1282 | |
| 1283 | void dip_add(int argc, char *argv[]) |
| 1284 | { |
| 1285 | unsigned int value = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1286 | unsigned int i = 0, j = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1287 | |
| 1288 | value = 0; |
| 1289 | |
| 1290 | str_to_ip(&value, argv[3]); |
| 1291 | |
| 1292 | reg_write(REG_ATA1_ADDR, value); |
| 1293 | printf("REG_ATA1_ADDR is 0x%x\n\r", value); |
| 1294 | |
| 1295 | #if 0 |
| 1296 | reg_write(REG_ATA2_ADDR, value); |
| 1297 | printf("REG_ATA2_ADDR is 0x%x\n\r", value); |
| 1298 | #endif |
| 1299 | if (!argv[4] || strlen(argv[4]) != 8) { |
| 1300 | printf("portmap format error, should be of length 7\n"); |
| 1301 | return; |
| 1302 | } |
| 1303 | j = 0; |
| 1304 | for (i = 0; i < 7; i++) { |
| 1305 | if (argv[4][i] != '0' && argv[4][i] != '1') { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1306 | printf |
| 1307 | ("portmap format error, should be of combination of 0 or 1\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1308 | return; |
| 1309 | } |
| 1310 | j += (argv[4][i] - '0') * (1 << i); |
| 1311 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1312 | value = j << 4; //w_port_map |
| 1313 | value |= (0x3 << 2); //static |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1314 | |
| 1315 | reg_write(REG_ATWD_ADDR, value); |
| 1316 | |
| 1317 | usleep(5000); |
| 1318 | reg_read(REG_ATWD_ADDR, &value); |
| 1319 | printf("REG_ATWD_ADDR is 0x%x\n\r", value); |
| 1320 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1321 | value = 0x8011; //single w_dip_cmd |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1322 | reg_write(REG_ATC_ADDR, value); |
| 1323 | |
| 1324 | usleep(1000); |
| 1325 | |
| 1326 | for (i = 0; i < 20; i++) { |
| 1327 | reg_read(REG_ATC_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1328 | if ((value & 0x8000) == 0) { //mac address busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1329 | printf("done.\n"); |
| 1330 | return; |
| 1331 | } |
| 1332 | usleep(1000); |
| 1333 | } |
| 1334 | if (i == 20) |
| 1335 | printf("timeout.\n"); |
| 1336 | } |
| 1337 | |
| 1338 | void dip_del(int argc, char *argv[]) |
| 1339 | { |
| 1340 | unsigned int i, value; |
| 1341 | |
| 1342 | value = 0; |
| 1343 | str_to_ip(&value, argv[3]); |
| 1344 | |
| 1345 | reg_write(REG_ATA1_ADDR, value); |
| 1346 | |
| 1347 | value = 0; |
| 1348 | reg_write(REG_ATA2_ADDR, value); |
| 1349 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1350 | value = 0; //STATUS=0, delete dip |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1351 | reg_write(REG_ATWD_ADDR, value); |
| 1352 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1353 | value = 0x8011; //w_dip_cmd |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1354 | reg_write(REG_ATC_ADDR, value); |
| 1355 | |
| 1356 | for (i = 0; i < 20; i++) { |
| 1357 | reg_read(REG_ATC_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1358 | if ((value & 0x8000) == 0) { //mac address busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1359 | if (argv[1] != NULL) |
| 1360 | printf("done.\n"); |
| 1361 | return; |
| 1362 | } |
| 1363 | usleep(1000); |
| 1364 | } |
| 1365 | if (i == 20) |
| 1366 | printf("timeout.\n"); |
| 1367 | } |
| 1368 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1369 | void dip_clear(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1370 | { |
| 1371 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1372 | unsigned int value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1373 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1374 | reg_write(REG_ATC_ADDR, 0x8102); //clear all dip |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1375 | usleep(5000); |
| 1376 | reg_read(REG_ATC_ADDR, &value); |
| 1377 | printf("REG_ATC_ADDR is 0x%x\n\r", value); |
| 1378 | } |
| 1379 | |
| 1380 | static void sip_dump_internal(int type) |
| 1381 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1382 | unsigned int i = 0, j = 0, value = 0, mac = 0, mac2 = 0, value2 = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1383 | int table_size = 0; |
| 1384 | int hit_value1 = 0; |
| 1385 | int hit_value2 = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1386 | char tmpstr[16] = { 0 }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1387 | |
| 1388 | if (type == GENERAL_TABLE) { |
| 1389 | table_size = 0x800; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1390 | reg_write(REG_ATC_ADDR, 0x8204); //sip search command |
| 1391 | } else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1392 | table_size = 0x40; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1393 | reg_write(REG_ATC_ADDR, 0x822c); //sip search command |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1394 | } |
| 1395 | printf("hash port(0:6) dip-address sip-address ATRD\n"); |
| 1396 | for (i = 0; i < table_size; i++) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1397 | while (1) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1398 | reg_read(REG_ATC_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1399 | if (type == GENERAL_TABLE) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1400 | hit_value1 = value & (0x1 << 13); |
| 1401 | hit_value2 = 1; |
| 1402 | } else { |
| 1403 | hit_value1 = value & (0x1 << 13); |
| 1404 | hit_value2 = value & (0x1 << 28); |
| 1405 | } |
| 1406 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1407 | if (hit_value1 && hit_value2) { //search_rdy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1408 | reg_read(REG_ATRD_ADDR, &value2); |
| 1409 | //printf("REG_ATRD_ADDR=0x%x\n\r",value2); |
| 1410 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1411 | printf("%03x: ", (value >> 16) & 0xfff); //hash_addr_lu |
| 1412 | j = (value2 >> 4) & 0xff; //r_port_map |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1413 | printf("%c", (j & 0x01) ? '1' : '-'); |
| 1414 | printf("%c", (j & 0x02) ? '1' : '-'); |
| 1415 | printf("%c", (j & 0x04) ? '1' : '-'); |
| 1416 | printf("%c", (j & 0x08) ? '1' : '-'); |
| 1417 | printf(" %c", (j & 0x10) ? '1' : '-'); |
| 1418 | printf("%c", (j & 0x20) ? '1' : '-'); |
| 1419 | printf("%c", (j & 0x40) ? '1' : '-'); |
| 1420 | |
| 1421 | reg_read(REG_TSRA2_ADDR, &mac2); |
| 1422 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 1423 | ip_to_str(tmpstr, sizeof(tmpstr), mac2); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1424 | printf(" %s", tmpstr); |
| 1425 | |
| 1426 | //printf(" %4d", (value2 >> 24) & 0xff); //r_age_field |
| 1427 | reg_read(REG_TSRA1_ADDR, &mac); |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 1428 | ip_to_str(tmpstr, sizeof(tmpstr), mac); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1429 | printf(" %s", tmpstr); |
| 1430 | printf(" 0x%x\n", value2); |
| 1431 | //printf("%04x", ((mac2 >> 16) & 0xffff)); |
| 1432 | //printf(" %c\n", (((value2 >> 20) & 0x03)== 0x03)? 'y':'-'); |
| 1433 | if (value & 0x4000) { |
| 1434 | printf("end of table %d\n", i); |
| 1435 | return; |
| 1436 | } |
| 1437 | break; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1438 | } else if (value & 0x4000) { //at_table_end |
| 1439 | printf("found the last entry %d (not ready)\n", |
| 1440 | i); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1441 | return; |
| 1442 | } |
| 1443 | usleep(5000); |
| 1444 | } |
| 1445 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1446 | if (type == GENERAL_TABLE) |
| 1447 | reg_write(REG_ATC_ADDR, 0x8205); //search for next sip address |
| 1448 | else |
| 1449 | reg_write(REG_ATC_ADDR, 0x822d); //search for next sip address |
| 1450 | usleep(5000); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1451 | } |
| 1452 | } |
| 1453 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1454 | void sip_dump(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1455 | { |
| 1456 | |
| 1457 | sip_dump_internal(GENERAL_TABLE); |
| 1458 | |
| 1459 | } |
| 1460 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1461 | void sip_add(int argc, char *argv[]) |
| 1462 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1463 | unsigned int i = 0, j = 0, value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1464 | |
| 1465 | value = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1466 | str_to_ip(&value, argv[3]); //SIP |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1467 | |
| 1468 | reg_write(REG_ATA2_ADDR, value); |
| 1469 | printf("REG_ATA2_ADDR is 0x%x\n\r", value); |
| 1470 | |
| 1471 | value = 0; |
| 1472 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1473 | str_to_ip(&value, argv[4]); //DIP |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1474 | reg_write(REG_ATA1_ADDR, value); |
| 1475 | printf("REG_ATA1_ADDR is 0x%x\n\r", value); |
| 1476 | |
| 1477 | if (!argv[5] || strlen(argv[5]) != 8) { |
| 1478 | printf("portmap format error, should be of length 7\n"); |
| 1479 | return; |
| 1480 | } |
| 1481 | j = 0; |
| 1482 | for (i = 0; i < 7; i++) { |
| 1483 | if (argv[5][i] != '0' && argv[5][i] != '1') { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1484 | printf |
| 1485 | ("portmap format error, should be of combination of 0 or 1\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1486 | return; |
| 1487 | } |
| 1488 | j += (argv[5][i] - '0') * (1 << i); |
| 1489 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1490 | value = j << 4; //w_port_map |
| 1491 | value |= (0x3 << 2); //static |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1492 | |
| 1493 | reg_write(REG_ATWD_ADDR, value); |
| 1494 | |
| 1495 | usleep(5000); |
| 1496 | reg_read(REG_ATWD_ADDR, &value); |
| 1497 | printf("REG_ATWD_ADDR is 0x%x\n\r", value); |
| 1498 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1499 | value = 0x8021; //single w_sip_cmd |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1500 | reg_write(REG_ATC_ADDR, value); |
| 1501 | |
| 1502 | usleep(1000); |
| 1503 | |
| 1504 | for (i = 0; i < 20; i++) { |
| 1505 | reg_read(REG_ATC_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1506 | if ((value & 0x8000) == 0) { //mac address busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1507 | printf("done.\n"); |
| 1508 | return; |
| 1509 | } |
| 1510 | usleep(1000); |
| 1511 | } |
| 1512 | if (i == 20) |
| 1513 | printf("timeout.\n"); |
| 1514 | } |
| 1515 | |
| 1516 | void sip_del(int argc, char *argv[]) |
| 1517 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1518 | unsigned int i = 0, value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1519 | |
| 1520 | value = 0; |
| 1521 | str_to_ip(&value, argv[3]); |
| 1522 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1523 | reg_write(REG_ATA2_ADDR, value); //SIP |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1524 | |
| 1525 | str_to_ip(&value, argv[4]); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1526 | reg_write(REG_ATA1_ADDR, value); //DIP |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1527 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1528 | value = 0; //STATUS=0, delete sip |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1529 | reg_write(REG_ATWD_ADDR, value); |
| 1530 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1531 | value = 0x8021; //w_sip_cmd |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1532 | reg_write(REG_ATC_ADDR, value); |
| 1533 | |
| 1534 | for (i = 0; i < 20; i++) { |
| 1535 | reg_read(REG_ATC_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1536 | if ((value & 0x8000) == 0) { //mac address busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1537 | if (argv[1] != NULL) |
| 1538 | printf("done.\n"); |
| 1539 | return; |
| 1540 | } |
| 1541 | usleep(1000); |
| 1542 | } |
| 1543 | if (i == 20) |
| 1544 | printf("timeout.\n"); |
| 1545 | } |
| 1546 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1547 | void sip_clear(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1548 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1549 | unsigned int value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1550 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1551 | reg_write(REG_ATC_ADDR, 0x8202); //clear all sip |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1552 | usleep(5000); |
| 1553 | reg_read(REG_ATC_ADDR, &value); |
| 1554 | printf("REG_ATC_ADDR is 0x%x\n\r", value); |
| 1555 | } |
| 1556 | |
| 1557 | static void table_dump_internal(int type) |
| 1558 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1559 | unsigned int i = 0, j = 0, value = 0, mac = 0, mac2 = 0, value2 = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1560 | int table_size = 0; |
| 1561 | int table_end = 0; |
| 1562 | int hit_value1 = 0; |
| 1563 | int hit_value2 = 0; |
| 1564 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1565 | if (type == GENERAL_TABLE) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1566 | table_size = 0x800; |
| 1567 | table_end = 0x7FF; |
| 1568 | reg_write(REG_ATC_ADDR, 0x8004); |
| 1569 | } else { |
| 1570 | table_size = 0x40; |
| 1571 | table_end = 0x3F; |
| 1572 | reg_write(REG_ATC_ADDR, 0x800C); |
| 1573 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1574 | printf |
| 1575 | ("hash port(0:6) fid vid age(s) mac-address filter my_mac\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1576 | for (i = 0; i < table_size; i++) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1577 | while (1) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1578 | reg_read(REG_ATC_ADDR, &value); |
| 1579 | //printf("ATC = 0x%x\n", value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1580 | if (type == GENERAL_TABLE) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1581 | hit_value1 = value & (0x1 << 13); |
| 1582 | hit_value2 = 1; |
| 1583 | } else { |
| 1584 | hit_value1 = value & (0x1 << 13); |
| 1585 | hit_value2 = value & (0x1 << 28); |
| 1586 | } |
| 1587 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1588 | if (hit_value1 && hit_value2 |
| 1589 | && (((value >> 15) & 0x1) == 0)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1590 | printf("%03x: ", (value >> 16) & 0xfff); |
| 1591 | reg_read(REG_ATRD_ADDR, &value2); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1592 | j = (value2 >> 4) & 0xff; //r_port_map |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1593 | printf("%c", (j & 0x01) ? '1' : '-'); |
| 1594 | printf("%c", (j & 0x02) ? '1' : '-'); |
| 1595 | printf("%c", (j & 0x04) ? '1' : '-'); |
| 1596 | printf("%c", (j & 0x08) ? '1' : '-'); |
| 1597 | printf("%c", (j & 0x10) ? '1' : '-'); |
| 1598 | printf("%c", (j & 0x20) ? '1' : '-'); |
| 1599 | printf("%c", (j & 0x40) ? '1' : '-'); |
| 1600 | printf("%c", (j & 0x80) ? '1' : '-'); |
| 1601 | |
| 1602 | reg_read(REG_TSRA2_ADDR, &mac2); |
| 1603 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1604 | printf(" %2d", (mac2 >> 12) & 0x7); //FID |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1605 | printf(" %4d", (mac2 & 0xfff)); |
| 1606 | if (((value2 >> 24) & 0xff) == 0xFF) |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1607 | printf(" --- "); //r_age_field:static |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1608 | else |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1609 | printf(" %5d ", (((value2 >> 24) & 0xff) + 1) * 2); //r_age_field |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1610 | reg_read(REG_TSRA1_ADDR, &mac); |
| 1611 | printf(" %08x", mac); |
| 1612 | printf("%04x", ((mac2 >> 16) & 0xffff)); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1613 | printf(" %c", |
| 1614 | (((value2 >> 20) & 0x03) == |
| 1615 | 0x03) ? 'y' : '-'); |
| 1616 | printf(" %c\n", |
| 1617 | (((value2 >> 23) & 0x01) == |
| 1618 | 0x01) ? 'y' : '-'); |
| 1619 | if ((value & 0x4000) |
| 1620 | && (((value >> 16) & 0xfff) == table_end)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1621 | printf("end of table %d\n", i); |
| 1622 | return; |
| 1623 | } |
| 1624 | break; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1625 | } else if ((value & 0x4000) && (((value >> 15) & 0x1) == 0) && (((value >> 16) & 0xfff) == table_end)) { //at_table_end |
| 1626 | printf("found the last entry %d (not ready)\n", |
| 1627 | i); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1628 | return; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1629 | } else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1630 | usleep(5); |
| 1631 | } |
| 1632 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1633 | if (type == GENERAL_TABLE) |
| 1634 | reg_write(REG_ATC_ADDR, 0x8005); //search for next address |
| 1635 | else |
| 1636 | reg_write(REG_ATC_ADDR, 0x800d); //search for next address |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1637 | usleep(5); |
| 1638 | } |
| 1639 | } |
| 1640 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1641 | void table_dump(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1642 | { |
| 1643 | table_dump_internal(GENERAL_TABLE); |
| 1644 | |
| 1645 | } |
| 1646 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1647 | void table_add(int argc, char *argv[]) |
| 1648 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1649 | unsigned int i = 0, j = 0, value = 0, is_filter = 0, is_mymac = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1650 | char tmpstr[9]; |
| 1651 | |
| 1652 | is_filter = (argv[1][0] == 'f') ? 1 : 0; |
| 1653 | is_mymac = (argv[1][0] == 'm') ? 1 : 0; |
| 1654 | if (!argv[2] || strlen(argv[2]) != 12) { |
| 1655 | printf("MAC address format error, should be of length 12\n"); |
| 1656 | return; |
| 1657 | } |
| 1658 | strncpy(tmpstr, argv[2], 8); |
| 1659 | tmpstr[8] = '\0'; |
| 1660 | value = strtoul(tmpstr, NULL, 16); |
| 1661 | reg_write(REG_ATA1_ADDR, value); |
| 1662 | printf("REG_ATA1_ADDR is 0x%x\n\r", value); |
| 1663 | |
| 1664 | strncpy(tmpstr, argv[2] + 8, 4); |
| 1665 | tmpstr[4] = '\0'; |
| 1666 | |
| 1667 | value = strtoul(tmpstr, NULL, 16); |
| 1668 | value = (value << 16); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1669 | value |= (1 << 15); //IVL=1 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1670 | |
| 1671 | if (argc > 4) { |
| 1672 | j = strtoul(argv[4], NULL, 0); |
| 1673 | if (4095 < j) { |
| 1674 | printf("wrong vid range, should be within 0~4095\n"); |
| 1675 | return; |
| 1676 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1677 | value |= j; //vid |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1678 | } |
| 1679 | |
| 1680 | reg_write(REG_ATA2_ADDR, value); |
| 1681 | printf("REG_ATA2_ADDR is 0x%x\n\r", value); |
| 1682 | |
| 1683 | if (!argv[3] || strlen(argv[3]) != 8) { |
| 1684 | if (is_filter) |
| 1685 | argv[3] = "11111111"; |
| 1686 | else { |
| 1687 | printf("portmap format error, should be of length 8\n"); |
| 1688 | return; |
| 1689 | } |
| 1690 | } |
| 1691 | j = 0; |
| 1692 | for (i = 0; i < 7; i++) { |
| 1693 | if (argv[3][i] != '0' && argv[3][i] != '1') { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1694 | printf |
| 1695 | ("portmap format error, should be of combination of 0 or 1\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1696 | return; |
| 1697 | } |
| 1698 | j += (argv[3][i] - '0') * (1 << i); |
| 1699 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1700 | value = j << 4; //w_port_map |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1701 | |
| 1702 | if (argc > 5) { |
| 1703 | j = strtoul(argv[5], NULL, 0); |
| 1704 | if (j < 1 || 255 < j) { |
| 1705 | printf("wrong age range, should be within 1~255\n"); |
| 1706 | return; |
| 1707 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1708 | value |= (j << 24); //w_age_field |
| 1709 | value |= (0x1 << 2); //dynamic |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1710 | } else { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1711 | value |= (0xff << 24); //w_age_field |
| 1712 | value |= (0x3 << 2); //static |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1713 | } |
| 1714 | |
| 1715 | if (argc > 6) { |
| 1716 | j = strtoul(argv[6], NULL, 0); |
| 1717 | if (7 < j) { |
| 1718 | printf("wrong eg-tag range, should be within 0~7\n"); |
| 1719 | return; |
| 1720 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1721 | value |= (j << 13); //EG_TAG |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1722 | } |
| 1723 | |
| 1724 | if (is_filter) |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1725 | value |= (7 << 20); //sa_filter |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1726 | |
| 1727 | if (is_mymac) |
| 1728 | value |= (1 << 23); |
| 1729 | |
| 1730 | reg_write(REG_ATWD_ADDR, value); |
| 1731 | |
| 1732 | usleep(5000); |
| 1733 | reg_read(REG_ATWD_ADDR, &value); |
| 1734 | printf("REG_ATWD_ADDR is 0x%x\n\r", value); |
| 1735 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1736 | value = 0x8001; //w_mac_cmd |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1737 | reg_write(REG_ATC_ADDR, value); |
| 1738 | |
| 1739 | usleep(1000); |
| 1740 | |
| 1741 | for (i = 0; i < 20; i++) { |
| 1742 | reg_read(REG_ATC_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1743 | if ((value & 0x8000) == 0) { //mac address busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1744 | printf("done.\n"); |
| 1745 | return; |
| 1746 | } |
| 1747 | usleep(1000); |
| 1748 | } |
| 1749 | if (i == 20) |
| 1750 | printf("timeout.\n"); |
| 1751 | } |
| 1752 | |
| 1753 | void table_search_mac_vid(int argc, char *argv[]) |
| 1754 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1755 | unsigned int i = 0, j = 0, value = 0, mac = 0, mac2 = 0, value2 = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1756 | char tmpstr[9]; |
| 1757 | |
| 1758 | if (!argv[3] || strlen(argv[3]) != 12) { |
| 1759 | printf("MAC address format error, should be of length 12\n"); |
| 1760 | return; |
| 1761 | } |
| 1762 | strncpy(tmpstr, argv[3], 8); |
| 1763 | tmpstr[8] = '\0'; |
| 1764 | value = strtoul(tmpstr, NULL, 16); |
| 1765 | reg_write(REG_ATA1_ADDR, value); |
| 1766 | //printf("REG_ATA1_ADDR is 0x%x\n\r",value); |
| 1767 | |
| 1768 | strncpy(tmpstr, argv[3] + 8, 4); |
| 1769 | tmpstr[4] = '\0'; |
| 1770 | |
| 1771 | value = strtoul(tmpstr, NULL, 16); |
| 1772 | value = (value << 16); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1773 | value |= (1 << 15); //IVL=1 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1774 | |
| 1775 | j = strtoul(argv[5], NULL, 0); |
| 1776 | if (4095 < j) { |
| 1777 | printf("wrong vid range, should be within 0~4095\n"); |
| 1778 | return; |
| 1779 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1780 | value |= j; //vid |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1781 | |
| 1782 | reg_write(REG_ATA2_ADDR, value); |
| 1783 | //printf("REG_ATA2_ADDR is 0x%x\n\r",value); |
| 1784 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1785 | value = 0x8000; //w_mac_cmd |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1786 | reg_write(REG_ATC_ADDR, value); |
| 1787 | |
| 1788 | usleep(1000); |
| 1789 | |
| 1790 | for (i = 0; i < 20; i++) { |
| 1791 | reg_read(REG_ATC_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1792 | if ((value & 0x8000) == 0) { //mac address busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1793 | break; |
| 1794 | } |
| 1795 | usleep(1000); |
| 1796 | } |
| 1797 | if (i == 20) { |
| 1798 | printf("search timeout.\n"); |
| 1799 | return; |
| 1800 | } |
| 1801 | |
| 1802 | if (value & 0x1000) { |
| 1803 | printf("search no entry.\n"); |
| 1804 | return; |
| 1805 | } |
| 1806 | |
| 1807 | printf("search done.\n"); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1808 | printf |
| 1809 | ("hash port(0:6) fid vid age mac-address filter my_mac\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1810 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1811 | printf("%03x: ", (value >> 16) & 0xfff); //hash_addr_lu |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1812 | reg_read(REG_ATRD_ADDR, &value2); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1813 | j = (value2 >> 4) & 0xff; //r_port_map |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1814 | printf("%c", (j & 0x01) ? '1' : '-'); |
| 1815 | printf("%c", (j & 0x02) ? '1' : '-'); |
| 1816 | printf("%c", (j & 0x04) ? '1' : '-'); |
| 1817 | printf("%c ", (j & 0x08) ? '1' : '-'); |
| 1818 | printf("%c", (j & 0x10) ? '1' : '-'); |
| 1819 | printf("%c", (j & 0x20) ? '1' : '-'); |
| 1820 | printf("%c", (j & 0x40) ? '1' : '-'); |
| 1821 | printf("%c", (j & 0x80) ? '1' : '-'); |
| 1822 | |
| 1823 | reg_read(REG_TSRA2_ADDR, &mac2); |
| 1824 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1825 | printf(" %2d", (mac2 >> 12) & 0x7); //FID |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1826 | printf(" %4d", (mac2 & 0xfff)); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1827 | printf(" %4d", (value2 >> 24) & 0xff); //r_age_field |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1828 | reg_read(REG_TSRA1_ADDR, &mac); |
| 1829 | printf(" %08x", mac); |
| 1830 | printf("%04x", ((mac2 >> 16) & 0xffff)); |
| 1831 | printf(" %c", (((value2 >> 20) & 0x03) == 0x03) ? 'y' : '-'); |
| 1832 | printf(" %c\n", (((value2 >> 23) & 0x01) == 0x01) ? 'y' : '-'); |
| 1833 | } |
| 1834 | |
| 1835 | void table_search_mac_fid(int argc, char *argv[]) |
| 1836 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1837 | unsigned int i = 0, j = 0, value = 0, mac = 0, mac2 = 0, value2 = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1838 | char tmpstr[9]; |
| 1839 | |
| 1840 | if (!argv[3] || strlen(argv[3]) != 12) { |
| 1841 | printf("MAC address format error, should be of length 12\n"); |
| 1842 | return; |
| 1843 | } |
| 1844 | strncpy(tmpstr, argv[3], 8); |
| 1845 | tmpstr[8] = '\0'; |
| 1846 | value = strtoul(tmpstr, NULL, 16); |
| 1847 | reg_write(REG_ATA1_ADDR, value); |
| 1848 | //printf("REG_ATA1_ADDR is 0x%x\n\r",value); |
| 1849 | |
| 1850 | strncpy(tmpstr, argv[3] + 8, 4); |
| 1851 | tmpstr[4] = '\0'; |
| 1852 | |
| 1853 | value = strtoul(tmpstr, NULL, 16); |
| 1854 | value = (value << 16); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1855 | value &= ~(1 << 15); //IVL=0 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1856 | |
| 1857 | j = strtoul(argv[5], NULL, 0); |
| 1858 | if (7 < j) { |
| 1859 | printf("wrong fid range, should be within 0~7\n"); |
| 1860 | return; |
| 1861 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1862 | value |= (j << 12); //vid |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1863 | |
| 1864 | reg_write(REG_ATA2_ADDR, value); |
| 1865 | //printf("REG_ATA2_ADDR is 0x%x\n\r",value); |
| 1866 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1867 | value = 0x8000; //w_mac_cmd |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1868 | reg_write(REG_ATC_ADDR, value); |
| 1869 | |
| 1870 | usleep(1000); |
| 1871 | |
| 1872 | for (i = 0; i < 20; i++) { |
| 1873 | reg_read(REG_ATC_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1874 | if ((value & 0x8000) == 0) { //mac address busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1875 | break; |
| 1876 | } |
| 1877 | usleep(1000); |
| 1878 | } |
| 1879 | if (i == 20) { |
| 1880 | printf("search timeout.\n"); |
| 1881 | return; |
| 1882 | } |
| 1883 | |
| 1884 | if (value & 0x1000) { |
| 1885 | printf("search no entry.\n"); |
| 1886 | return; |
| 1887 | } |
| 1888 | |
| 1889 | printf("search done.\n"); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1890 | printf |
| 1891 | ("hash port(0:6) fid vid age mac-address filter my_mac\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1892 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1893 | printf("%03x: ", (value >> 16) & 0xfff); //hash_addr_lu |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1894 | reg_read(REG_ATRD_ADDR, &value2); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1895 | j = (value2 >> 4) & 0xff; //r_port_map |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1896 | printf("%c", (j & 0x01) ? '1' : '-'); |
| 1897 | printf("%c", (j & 0x02) ? '1' : '-'); |
| 1898 | printf("%c", (j & 0x04) ? '1' : '-'); |
| 1899 | printf("%c ", (j & 0x08) ? '1' : '-'); |
| 1900 | printf("%c", (j & 0x10) ? '1' : '-'); |
| 1901 | printf("%c", (j & 0x20) ? '1' : '-'); |
| 1902 | printf("%c", (j & 0x40) ? '1' : '-'); |
| 1903 | printf("%c", (j & 0x80) ? '1' : '-'); |
| 1904 | |
| 1905 | reg_read(REG_TSRA2_ADDR, &mac2); |
| 1906 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1907 | printf(" %2d", (mac2 >> 12) & 0x7); //FID |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1908 | printf(" %4d", (mac2 & 0xfff)); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1909 | printf(" %4d", (value2 >> 24) & 0xff); //r_age_field |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1910 | reg_read(REG_TSRA1_ADDR, &mac); |
| 1911 | printf(" %08x", mac); |
| 1912 | printf("%04x", ((mac2 >> 16) & 0xffff)); |
| 1913 | printf(" %c", (((value2 >> 20) & 0x03) == 0x03) ? 'y' : '-'); |
| 1914 | printf(" %c\n", (((value2 >> 23) & 0x01) == 0x01) ? 'y' : '-'); |
| 1915 | } |
| 1916 | |
| 1917 | void table_del_fid(int argc, char *argv[]) |
| 1918 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1919 | unsigned int i = 0, j = 0, value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1920 | char tmpstr[9]; |
| 1921 | |
| 1922 | if (!argv[3] || strlen(argv[3]) != 12) { |
| 1923 | printf("MAC address format error, should be of length 12\n"); |
| 1924 | return; |
| 1925 | } |
| 1926 | strncpy(tmpstr, argv[3], 8); |
| 1927 | tmpstr[8] = '\0'; |
| 1928 | value = strtoul(tmpstr, NULL, 16); |
| 1929 | reg_write(REG_ATA1_ADDR, value); |
| 1930 | strncpy(tmpstr, argv[3] + 8, 4); |
| 1931 | tmpstr[4] = '\0'; |
| 1932 | value = strtoul(tmpstr, NULL, 16); |
| 1933 | value = (value << 16); |
| 1934 | |
| 1935 | if (argc > 5) { |
| 1936 | j = strtoul(argv[5], NULL, 0); |
| 1937 | if (j > 7) { |
| 1938 | printf("wrong fid range, should be within 0~7\n"); |
| 1939 | return; |
| 1940 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1941 | value |= (j << 12); /* fid */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1942 | } |
| 1943 | |
| 1944 | reg_write(REG_ATA2_ADDR, value); |
| 1945 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1946 | value = 0; /* STATUS=0, delete mac */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1947 | reg_write(REG_ATWD_ADDR, value); |
| 1948 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1949 | value = 0x8001; //w_mac_cmd |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1950 | reg_write(REG_ATC_ADDR, value); |
| 1951 | |
| 1952 | for (i = 0; i < 20; i++) { |
| 1953 | reg_read(REG_ATC_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1954 | if ((value & 0x8000) == 0) { /* mac address busy */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1955 | if (argv[1] != NULL) |
| 1956 | printf("done.\n"); |
| 1957 | return; |
| 1958 | } |
| 1959 | usleep(1000); |
| 1960 | } |
| 1961 | if (i == 20) |
| 1962 | printf("timeout.\n"); |
| 1963 | } |
| 1964 | |
| 1965 | void table_del_vid(int argc, char *argv[]) |
| 1966 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1967 | unsigned int i = 0, j = 0, value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1968 | char tmpstr[9]; |
| 1969 | |
| 1970 | if (!argv[3] || strlen(argv[3]) != 12) { |
| 1971 | printf("MAC address format error, should be of length 12\n"); |
| 1972 | return; |
| 1973 | } |
| 1974 | strncpy(tmpstr, argv[3], 8); |
| 1975 | tmpstr[8] = '\0'; |
| 1976 | value = strtoul(tmpstr, NULL, 16); |
| 1977 | reg_write(REG_ATA1_ADDR, value); |
| 1978 | |
| 1979 | strncpy(tmpstr, argv[3] + 8, 4); |
| 1980 | tmpstr[4] = '\0'; |
| 1981 | value = strtoul(tmpstr, NULL, 16); |
| 1982 | value = (value << 16); |
| 1983 | |
| 1984 | j = strtoul(argv[5], NULL, 0); |
| 1985 | if (j > 4095) { |
| 1986 | printf("wrong fid range, should be within 0~4095\n"); |
| 1987 | return; |
| 1988 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1989 | value |= j; //vid |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1990 | value |= 1 << 15; |
| 1991 | reg_write(REG_ATA2_ADDR, value); |
| 1992 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1993 | value = 0; //STATUS=0, delete mac |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1994 | reg_write(REG_ATWD_ADDR, value); |
| 1995 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 1996 | value = 0x8001; //w_mac_cmd |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1997 | reg_write(REG_ATC_ADDR, value); |
| 1998 | |
| 1999 | for (i = 0; i < 20; i++) { |
| 2000 | reg_read(REG_ATC_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2001 | if ((value & 0x8000) == 0) { //mac address busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2002 | if (argv[1] != NULL) |
| 2003 | printf("done.\n"); |
| 2004 | return; |
| 2005 | } |
| 2006 | usleep(1000); |
| 2007 | } |
| 2008 | if (i == 20) |
| 2009 | printf("timeout.\n"); |
| 2010 | } |
| 2011 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2012 | void table_clear(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2013 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2014 | unsigned int value = 0; |
| 2015 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2016 | reg_write(REG_ATC_ADDR, 0x8002); |
| 2017 | usleep(5000); |
| 2018 | reg_read(REG_ATC_ADDR, &value); |
| 2019 | |
| 2020 | printf("REG_ATC_ADDR is 0x%x\n\r", value); |
| 2021 | } |
| 2022 | |
| 2023 | void set_mirror_to(int argc, char *argv[]) |
| 2024 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2025 | unsigned int value = 0; |
| 2026 | int idx = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2027 | |
| 2028 | idx = strtoul(argv[3], NULL, 0); |
| 2029 | if (idx < 0 || MAX_PORT < idx) { |
| 2030 | printf("wrong port member, should be within 0~%d\n", MAX_PORT); |
| 2031 | return; |
| 2032 | } |
| 2033 | if (chip_name == 0x7530) { |
| 2034 | |
| 2035 | reg_read(REG_MFC_ADDR, &value); |
| 2036 | value |= 0x1 << 3; |
| 2037 | value &= 0xfffffff8; |
| 2038 | value |= idx << 0; |
| 2039 | |
| 2040 | reg_write(REG_MFC_ADDR, value); |
| 2041 | } else { |
| 2042 | |
| 2043 | reg_read(REG_CFC_ADDR, &value); |
| 2044 | value &= (~REG_CFC_MIRROR_EN_MASK); |
| 2045 | value |= (1 << REG_CFC_MIRROR_EN_OFFT); |
| 2046 | value &= (~REG_CFC_MIRROR_PORT_MASK); |
| 2047 | value |= (idx << REG_CFC_MIRROR_PORT_OFFT); |
| 2048 | reg_write(REG_CFC_ADDR, value); |
| 2049 | } |
| 2050 | } |
| 2051 | |
| 2052 | void set_mirror_from(int argc, char *argv[]) |
| 2053 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2054 | unsigned int offset = 0, value = 0; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2055 | unsigned int idx = 0, mirror = 0; |
| 2056 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2057 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2058 | errno = 0; |
| 2059 | idx = strtoul(argv[3], &endptr, 0); |
| 2060 | if (errno != 0 || *endptr != '\0' || idx > MAX_PORT) { |
| 2061 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2062 | return; |
| 2063 | } |
| 2064 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2065 | errno = 0; |
| 2066 | mirror = strtoul(argv[4], &endptr, 0); |
| 2067 | |
| 2068 | if (errno != 0 || *endptr != '\0' || mirror > 3) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2069 | printf("wrong mirror setting, should be within 0~3\n"); |
| 2070 | return; |
| 2071 | } |
| 2072 | |
| 2073 | offset = (0x2004 | (idx << 8)); |
| 2074 | reg_read(offset, &value); |
| 2075 | |
| 2076 | value &= 0xfffffcff; |
| 2077 | value |= mirror << 8; |
| 2078 | |
| 2079 | reg_write(offset, value); |
| 2080 | } |
| 2081 | |
| 2082 | void vlan_dump(int argc, char *argv[]) |
| 2083 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2084 | unsigned int i = 0, j = 0, value = 0, value2 = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2085 | int eg_tag = 0; |
| 2086 | |
| 2087 | if (argc == 4) { |
| 2088 | if (!strncmp(argv[3], "egtag", 6)) |
| 2089 | eg_tag = 1; |
| 2090 | } |
| 2091 | |
| 2092 | if (eg_tag) |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2093 | printf |
| 2094 | (" vid fid portmap s-tag\teg_tag(0:untagged 2:tagged)\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2095 | else |
| 2096 | printf(" vid fid portmap s-tag\n"); |
| 2097 | |
| 2098 | for (i = 1; i < 4095; i++) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2099 | value = (0x80000000 + i); //r_vid_cmd |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2100 | reg_write(REG_VTCR_ADDR, value); |
| 2101 | |
| 2102 | for (j = 0; j < 20; j++) { |
| 2103 | reg_read(REG_VTCR_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2104 | if ((value & 0x80000000) == 0) { //mac address busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2105 | break; |
| 2106 | } |
| 2107 | usleep(1000); |
| 2108 | } |
| 2109 | if (j == 20) |
| 2110 | printf("timeout.\n"); |
| 2111 | |
| 2112 | reg_read(REG_VAWD1_ADDR, &value); |
| 2113 | reg_read(REG_VAWD2_ADDR, &value2); |
| 2114 | //printf("REG_VAWD1_ADDR value%d is 0x%x\n\r", i, value); |
| 2115 | //printf("REG_VAWD2_ADDR value%d is 0x%x\n\r", i, value2); |
| 2116 | |
| 2117 | if ((value & 0x01) != 0) { |
| 2118 | printf(" %4d ", i); |
| 2119 | printf(" %2d ", ((value & 0xe) >> 1)); |
| 2120 | printf(" %c", (value & 0x00010000) ? '1' : '-'); |
| 2121 | printf("%c", (value & 0x00020000) ? '1' : '-'); |
| 2122 | printf("%c", (value & 0x00040000) ? '1' : '-'); |
| 2123 | printf("%c", (value & 0x00080000) ? '1' : '-'); |
| 2124 | printf("%c", (value & 0x00100000) ? '1' : '-'); |
| 2125 | printf("%c", (value & 0x00200000) ? '1' : '-'); |
| 2126 | printf("%c", (value & 0x00400000) ? '1' : '-'); |
| 2127 | printf("%c", (value & 0x00800000) ? '1' : '-'); |
| 2128 | printf(" %4d", ((value & 0xfff0) >> 4)); |
| 2129 | if (eg_tag) { |
| 2130 | printf("\t"); |
| 2131 | if ((value & (0x3 << 28)) == (0x3 << 28)) { |
| 2132 | /* VTAG_EN=1 and EG_CON=1 */ |
| 2133 | printf("CONSISTENT"); |
| 2134 | } else if (value & (0x1 << 28)) { |
| 2135 | /* VTAG_EN=1 */ |
| 2136 | printf("%d", (value2 & 0x0003) >> 0); |
| 2137 | printf("%d", (value2 & 0x000c) >> 2); |
| 2138 | printf("%d", (value2 & 0x0030) >> 4); |
| 2139 | printf("%d", (value2 & 0x00c0) >> 6); |
| 2140 | printf("%d", (value2 & 0x0300) >> 8); |
| 2141 | printf("%d", (value2 & 0x0c00) >> 10); |
| 2142 | printf("%d", (value2 & 0x3000) >> 12); |
| 2143 | printf("%d", (value2 & 0xc000) >> 14); |
| 2144 | } else { |
| 2145 | /* VTAG_EN=0 */ |
| 2146 | printf("DISABLED"); |
| 2147 | } |
| 2148 | } |
| 2149 | printf("\n"); |
| 2150 | } else { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2151 | /*print 16 vid for reference information */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2152 | if (i <= 16) { |
| 2153 | printf(" %4d ", i); |
| 2154 | printf(" %2d ", ((value & 0xe) >> 1)); |
| 2155 | printf(" invalid\n"); |
| 2156 | } |
| 2157 | } |
| 2158 | } |
| 2159 | } |
| 2160 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2161 | static long timespec_diff_us(struct timespec start, struct timespec end) |
| 2162 | { |
| 2163 | struct timespec temp; |
| 2164 | unsigned long duration = 0; |
| 2165 | |
| 2166 | if ((end.tv_nsec - start.tv_nsec) < 0) { |
| 2167 | temp.tv_sec = end.tv_sec - start.tv_sec - 1; |
| 2168 | temp.tv_nsec = 1000000000 + end.tv_nsec - start.tv_nsec; |
| 2169 | } else { |
| 2170 | temp.tv_sec = end.tv_sec - start.tv_sec; |
| 2171 | temp.tv_nsec = end.tv_nsec - start.tv_nsec; |
| 2172 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2173 | /* calculate second part */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2174 | duration += temp.tv_sec * 1000000; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2175 | /* calculate ns part */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2176 | duration += temp.tv_nsec >> 10; |
| 2177 | |
| 2178 | return duration; |
| 2179 | } |
| 2180 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2181 | void vlan_clear(int argc, char *argv[]) |
| 2182 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2183 | unsigned int value = 0; |
| 2184 | int vid = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2185 | unsigned long duration_us = 0; |
| 2186 | struct timespec start, end; |
| 2187 | |
| 2188 | for (vid = 0; vid < 4096; vid++) { |
| 2189 | clock_gettime(CLOCK_REALTIME, &start); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2190 | value = 0; //invalid |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2191 | reg_write(REG_VAWD1_ADDR, value); |
| 2192 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2193 | value = (0x80001000 + vid); //w_vid_cmd |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2194 | reg_write(REG_VTCR_ADDR, value); |
| 2195 | while (duration_us <= 1000) { |
| 2196 | reg_read(REG_VTCR_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2197 | if ((value & 0x80000000) == 0) { //table busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2198 | break; |
| 2199 | } |
| 2200 | clock_gettime(CLOCK_REALTIME, &end); |
| 2201 | duration_us = timespec_diff_us(start, end); |
| 2202 | } |
| 2203 | if (duration_us > 1000) |
| 2204 | printf("config vlan timeout: %ld.\n", duration_us); |
| 2205 | } |
| 2206 | } |
| 2207 | |
| 2208 | void vlan_set(int argc, char *argv[]) |
| 2209 | { |
| 2210 | unsigned int vlan_mem = 0; |
| 2211 | unsigned int value = 0; |
| 2212 | unsigned int value2 = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2213 | int i = 0, vid = 0, fid = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2214 | int stag = 0; |
| 2215 | unsigned long eg_con = 0; |
| 2216 | unsigned int eg_tag = 0; |
| 2217 | |
| 2218 | if (argc < 5) { |
| 2219 | printf("insufficient arguments!\n"); |
| 2220 | return; |
| 2221 | } |
| 2222 | |
| 2223 | fid = strtoul(argv[3], NULL, 0); |
| 2224 | if (fid < 0 || fid > 7) { |
| 2225 | printf("wrong filtering db id range, should be within 0~7\n"); |
| 2226 | return; |
| 2227 | } |
| 2228 | value |= (fid << 1); |
| 2229 | |
| 2230 | vid = strtoul(argv[4], NULL, 0); |
| 2231 | if (vid < 0 || 0xfff < vid) { |
| 2232 | printf("wrong vlan id range, should be within 0~4095\n"); |
| 2233 | return; |
| 2234 | } |
| 2235 | |
| 2236 | if (strlen(argv[5]) != 8) { |
| 2237 | printf("portmap format error, should be of length 7\n"); |
| 2238 | return; |
| 2239 | } |
| 2240 | |
| 2241 | vlan_mem = 0; |
| 2242 | for (i = 0; i < 8; i++) { |
| 2243 | if (argv[5][i] != '0' && argv[5][i] != '1') { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2244 | printf |
| 2245 | ("portmap format error, should be of combination of 0 or 1\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2246 | return; |
| 2247 | } |
| 2248 | vlan_mem += (argv[5][i] - '0') * (1 << i); |
| 2249 | } |
| 2250 | |
| 2251 | /* VLAN stag */ |
| 2252 | if (argc > 6) { |
| 2253 | stag = strtoul(argv[6], NULL, 16); |
| 2254 | if (stag < 0 || 0xfff < stag) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2255 | printf |
| 2256 | ("wrong stag id range, should be within 0~4095\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2257 | return; |
| 2258 | } |
| 2259 | //printf("STAG is 0x%x\n", stag); |
| 2260 | } |
| 2261 | |
| 2262 | /* set vlan member */ |
| 2263 | value |= (vlan_mem << 16); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2264 | value |= (1 << 30); //IVL=1 |
| 2265 | value |= ((stag & 0xfff) << 4); //stag |
| 2266 | value |= 1; //valid |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2267 | |
| 2268 | if (argc > 7) { |
| 2269 | eg_con = strtoul(argv[7], NULL, 2); |
| 2270 | eg_con = !!eg_con; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2271 | value |= (eg_con << 29); //eg_con |
| 2272 | value |= (1 << 28); //eg tag control enable |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2273 | } |
| 2274 | |
| 2275 | if (argc > 8 && !eg_con) { |
| 2276 | if (strlen(argv[8]) != 8) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2277 | printf |
| 2278 | ("egtag portmap format error, should be of length 7\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2279 | return; |
| 2280 | } |
| 2281 | |
| 2282 | for (i = 0; i < 8; i++) { |
| 2283 | if (argv[8][i] < '0' || argv[8][i] > '3') { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2284 | printf |
| 2285 | ("egtag portmap format error, should be of combination of 0 or 3\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2286 | return; |
| 2287 | } |
| 2288 | //eg_tag += (argv[8][i] - '0') * (1 << i * 2); |
| 2289 | eg_tag |= (argv[8][i] - '0') << (i * 2); |
| 2290 | } |
| 2291 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2292 | value |= (1 << 28); //eg tag control enable |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2293 | value2 &= ~(0xffff); |
| 2294 | value2 |= eg_tag; |
| 2295 | } |
| 2296 | reg_write(REG_VAWD1_ADDR, value); |
| 2297 | reg_write(REG_VAWD2_ADDR, value2); |
| 2298 | //printf("VAWD1=0x%08x VAWD2=0x%08x ", value, value2); |
| 2299 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2300 | value = (0x80001000 + vid); //w_vid_cmd |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2301 | reg_write(REG_VTCR_ADDR, value); |
| 2302 | //printf("VTCR=0x%08x\n", value); |
| 2303 | |
| 2304 | for (i = 0; i < 300; i++) { |
| 2305 | usleep(1000); |
| 2306 | reg_read(REG_VTCR_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2307 | if ((value & 0x80000000) == 0) //table busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2308 | break; |
| 2309 | } |
| 2310 | |
| 2311 | if (i == 300) |
| 2312 | printf("config vlan timeout.\n"); |
| 2313 | } |
| 2314 | |
| 2315 | void igmp_on(int argc, char *argv[]) |
| 2316 | { |
| 2317 | unsigned int leaky_en = 0; |
| 2318 | unsigned int wan_num = 4; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2319 | unsigned int port = 0, offset = 0, value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2320 | char cmd[80]; |
| 2321 | int ret; |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 2322 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2323 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 2324 | if (argc > 3) { |
| 2325 | errno = 0; |
| 2326 | leaky_en = strtoul(argv[3], &endptr, 10); |
| 2327 | if (errno != 0 || *endptr != '\0') { |
| 2328 | printf("Error: string converting\n"); |
| 2329 | return; |
| 2330 | } |
| 2331 | } |
| 2332 | if (argc > 4) { |
| 2333 | errno = 0; |
| 2334 | wan_num = strtoul(argv[4], &endptr, 10); |
| 2335 | if (errno != 0 || *endptr != '\0') { |
| 2336 | printf("Error: string converting\n"); |
| 2337 | return; |
| 2338 | } |
| 2339 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2340 | |
| 2341 | if (leaky_en == 1) { |
| 2342 | if (wan_num == 4) { |
| 2343 | /* reg_write(0x2410, 0x810000c8); */ |
| 2344 | reg_read(0x2410, &value); |
| 2345 | reg_write(0x2410, value | (1 << 3)); |
| 2346 | /* reg_write(0x2010, 0x810000c0); */ |
| 2347 | reg_read(0x2010, &value); |
| 2348 | reg_write(0x2010, value & (~(1 << 3))); |
| 2349 | reg_write(REG_ISC_ADDR, 0x10027d10); |
| 2350 | } else { |
| 2351 | /* reg_write(0x2010, 0x810000c8); */ |
| 2352 | reg_read(0x2010, &value); |
| 2353 | reg_write(0x2010, value | (1 << 3)); |
| 2354 | /* reg_write(0x2410, 0x810000c0); */ |
| 2355 | reg_read(0x2410, &value); |
| 2356 | reg_write(0x2410, value & (~(1 << 3))); |
| 2357 | reg_write(REG_ISC_ADDR, 0x01027d01); |
| 2358 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2359 | } else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2360 | reg_write(REG_ISC_ADDR, 0x10027d60); |
| 2361 | |
| 2362 | reg_write(0x1c, 0x08100810); |
| 2363 | reg_write(0x2008, 0xb3ff); |
| 2364 | reg_write(0x2108, 0xb3ff); |
| 2365 | reg_write(0x2208, 0xb3ff); |
| 2366 | reg_write(0x2308, 0xb3ff); |
| 2367 | reg_write(0x2408, 0xb3ff); |
| 2368 | reg_write(0x2608, 0xb3ff); |
| 2369 | /* Enable Port ACL |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2370 | * reg_write(0x2P04, 0xff0403); |
| 2371 | */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2372 | for (port = 0; port <= 6; port++) { |
| 2373 | offset = 0x2004 + port * 0x100; |
| 2374 | reg_read(offset, &value); |
| 2375 | reg_write(offset, value | (1 << 10)); |
| 2376 | } |
| 2377 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2378 | /*IGMP query only p4 -> p5 */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2379 | reg_write(0x94, 0x00ff0002); |
| 2380 | if (wan_num == 4) |
| 2381 | reg_write(0x98, 0x000a1008); |
| 2382 | else |
| 2383 | reg_write(0x98, 0x000a0108); |
| 2384 | reg_write(0x90, 0x80005000); |
| 2385 | reg_write(0x94, 0xff001100); |
| 2386 | if (wan_num == 4) |
| 2387 | reg_write(0x98, 0x000B1000); |
| 2388 | else |
| 2389 | reg_write(0x98, 0x000B0100); |
| 2390 | reg_write(0x90, 0x80005001); |
| 2391 | reg_write(0x94, 0x3); |
| 2392 | reg_write(0x98, 0x0); |
| 2393 | reg_write(0x90, 0x80009000); |
| 2394 | reg_write(0x94, 0x1a002080); |
| 2395 | reg_write(0x98, 0x0); |
| 2396 | reg_write(0x90, 0x8000b000); |
| 2397 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2398 | /*IGMP p5 -> p4 */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2399 | reg_write(0x94, 0x00ff0002); |
| 2400 | reg_write(0x98, 0x000a2008); |
| 2401 | reg_write(0x90, 0x80005002); |
| 2402 | reg_write(0x94, 0x4); |
| 2403 | reg_write(0x98, 0x0); |
| 2404 | reg_write(0x90, 0x80009001); |
| 2405 | if (wan_num == 4) |
| 2406 | reg_write(0x94, 0x1a001080); |
| 2407 | else |
| 2408 | reg_write(0x94, 0x1a000180); |
| 2409 | reg_write(0x98, 0x0); |
| 2410 | reg_write(0x90, 0x8000b001); |
| 2411 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2412 | /*IGMP p0~p3 -> p6 */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2413 | reg_write(0x94, 0x00ff0002); |
| 2414 | if (wan_num == 4) |
| 2415 | reg_write(0x98, 0x000a0f08); |
| 2416 | else |
| 2417 | reg_write(0x98, 0x000a1e08); |
| 2418 | reg_write(0x90, 0x80005003); |
| 2419 | reg_write(0x94, 0x8); |
| 2420 | reg_write(0x98, 0x0); |
| 2421 | reg_write(0x90, 0x80009002); |
| 2422 | reg_write(0x94, 0x1a004080); |
| 2423 | reg_write(0x98, 0x0); |
| 2424 | reg_write(0x90, 0x8000b002); |
| 2425 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2426 | /*IGMP query only p6 -> p0~p3 */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2427 | reg_write(0x94, 0x00ff0002); |
| 2428 | reg_write(0x98, 0x000a4008); |
| 2429 | reg_write(0x90, 0x80005004); |
| 2430 | reg_write(0x94, 0xff001100); |
| 2431 | reg_write(0x98, 0x000B4000); |
| 2432 | reg_write(0x90, 0x80005005); |
| 2433 | reg_write(0x94, 0x30); |
| 2434 | reg_write(0x98, 0x0); |
| 2435 | reg_write(0x90, 0x80009003); |
| 2436 | if (wan_num == 4) |
| 2437 | reg_write(0x94, 0x1a000f80); |
| 2438 | else |
| 2439 | reg_write(0x94, 0x1a001e80); |
| 2440 | reg_write(0x98, 0x0); |
| 2441 | reg_write(0x90, 0x8000b003); |
| 2442 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2443 | /*Force eth2 to receive all igmp packets */ |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 2444 | ret = snprintf(cmd, sizeof(cmd), |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2445 | "echo 2 > /sys/devices/virtual/net/%s/brif/%s/multicast_router", |
| 2446 | BR_DEVNAME, ETH_DEVNAME); |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 2447 | |
| 2448 | if (ret < 0 || ret >= sizeof(cmd)) |
| 2449 | goto error; |
| 2450 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2451 | ret = system(cmd); |
| 2452 | if (ret) |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 2453 | goto error; |
| 2454 | |
| 2455 | return; |
| 2456 | |
| 2457 | error: |
| 2458 | printf("Failed to set /sys/devices/virtual/net/%s/brif/%s/multicast_router\n", |
| 2459 | BR_DEVNAME, ETH_DEVNAME); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2460 | } |
| 2461 | |
| 2462 | void igmp_disable(int argc, char *argv[]) |
| 2463 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2464 | unsigned int reg_offset = 0, value = 0; |
| 2465 | int port_num = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2466 | |
| 2467 | if (argc < 4) { |
| 2468 | printf("insufficient arguments!\n"); |
| 2469 | return; |
| 2470 | } |
| 2471 | port_num = strtoul(argv[3], NULL, 0); |
| 2472 | if (port_num < 0 || 6 < port_num) { |
| 2473 | printf("wrong port range, should be within 0~6\n"); |
| 2474 | return; |
| 2475 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2476 | //set ISC: IGMP Snooping Control Register (offset: 0x0018) |
| 2477 | reg_offset = 0x2008; |
| 2478 | reg_offset |= (port_num << 8); |
| 2479 | value = 0x8000; |
| 2480 | |
| 2481 | reg_write(reg_offset, value); |
| 2482 | } |
| 2483 | |
| 2484 | void igmp_enable(int argc, char *argv[]) |
| 2485 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2486 | unsigned int reg_offset = 0, value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2487 | int port_num; |
| 2488 | |
| 2489 | if (argc < 4) { |
| 2490 | printf("insufficient arguments!\n"); |
| 2491 | return; |
| 2492 | } |
| 2493 | port_num = strtoul(argv[3], NULL, 0); |
| 2494 | if (port_num < 0 || 6 < port_num) { |
| 2495 | printf("wrong port range, should be within 0~6\n"); |
| 2496 | return; |
| 2497 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2498 | //set ISC: IGMP Snooping Control Register (offset: 0x0018) |
| 2499 | reg_offset = 0x2008; |
| 2500 | reg_offset |= (port_num << 8); |
| 2501 | value = 0x9755; |
| 2502 | reg_write(reg_offset, value); |
| 2503 | } |
| 2504 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2505 | void igmp_off(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2506 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2507 | unsigned int value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2508 | //set ISC: IGMP Snooping Control Register (offset: 0x0018) |
| 2509 | reg_read(REG_ISC_ADDR, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2510 | value &= ~(1 << 18); //disable |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2511 | reg_write(REG_ISC_ADDR, value); |
| 2512 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2513 | /*restore wan port multicast leaky vlan function: default disabled */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2514 | reg_read(0x2010, &value); |
| 2515 | reg_write(0x2010, value & (~(1 << 3))); |
| 2516 | reg_read(0x2410, &value); |
| 2517 | reg_write(0x2410, value & (~(1 << 3))); |
| 2518 | |
| 2519 | printf("config igmpsnoop off.\n"); |
| 2520 | } |
| 2521 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2522 | void switch_reset(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2523 | { |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 2524 | if (chip_name == 0x7988) |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2525 | return; |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 2526 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2527 | unsigned int value = 0; |
| 2528 | /*Software Register Reset and Software System Reset */ |
| 2529 | reg_write(0x7000, 0x3); |
| 2530 | reg_read(0x7000, &value); |
| 2531 | printf("SYS_CTRL(0x7000) register value =0x%x \n", value); |
| 2532 | if (chip_name == 0x7531) { |
| 2533 | reg_write(0x7c0c, 0x11111111); |
| 2534 | reg_read(0x7c0c, &value); |
| 2535 | printf("GPIO Mode (0x7c0c) select value =0x%x \n", value); |
| 2536 | } |
| 2537 | printf("Switch Software Reset !!! \n"); |
| 2538 | } |
| 2539 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2540 | void phy_set_fc(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2541 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2542 | unsigned int port = 0, pause_capable = 0; |
| 2543 | unsigned int phy_value = 0; |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 2544 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2545 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 2546 | errno = 0; |
| 2547 | port = strtoul(argv[3], &endptr, 10); |
| 2548 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT - 2) { |
| 2549 | printf("Error: wrong PHY port number, should be within 0~4\n"); |
| 2550 | return; |
| 2551 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2552 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 2553 | errno = 0; |
| 2554 | pause_capable = strtoul(argv[4], &endptr, 10); |
| 2555 | if (errno != 0 || *endptr != '\0' || pause_capable > 1) { |
| 2556 | printf("Illegal parameter, full_duplex_pause_capable:0|1\n"); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2557 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2558 | } |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 2559 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2560 | printf("port=%d, full_duplex_pause_capable:%d\n", port, pause_capable); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2561 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2562 | mii_mgr_read(port, 4, &phy_value); |
| 2563 | printf("read phy_value:0x%x\r\n", phy_value); |
| 2564 | phy_value &= (~(0x1 << 10)); |
| 2565 | phy_value &= (~(0x1 << 11)); |
| 2566 | if (pause_capable == 1) { |
| 2567 | phy_value |= (0x1 << 10); |
| 2568 | phy_value |= (0x1 << 11); |
| 2569 | } |
| 2570 | mii_mgr_write(port, 4, phy_value); |
| 2571 | printf("write phy_value:0x%x\r\n", phy_value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2572 | return; |
| 2573 | } /*end phy_set_fc */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2574 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2575 | void phy_set_an(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2576 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2577 | unsigned int port = 0, auto_negotiation_en = 0; |
| 2578 | unsigned int phy_value = 0; |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 2579 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2580 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 2581 | errno = 0; |
| 2582 | port = strtoul(argv[3], &endptr, 10); |
| 2583 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT - 2) { |
| 2584 | printf("Error: wrong PHY port number, should be within 0~4\n"); |
| 2585 | return; |
| 2586 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2587 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 2588 | errno = 0; |
| 2589 | auto_negotiation_en = strtoul(argv[4], &endptr, 10); |
| 2590 | if (errno != 0 || *endptr != '\0' || auto_negotiation_en > 1) { |
| 2591 | printf("Illegal parameter, auto_negotiation_en:0|1\n"); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2592 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2593 | } |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 2594 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2595 | printf("port=%d, auto_negotiation_en:%d\n", port, auto_negotiation_en); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2596 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2597 | mii_mgr_read(port, 0, &phy_value); |
| 2598 | printf("read phy_value:0x%x\r\n", phy_value); |
| 2599 | phy_value &= (~(1 << 12)); |
| 2600 | phy_value |= (auto_negotiation_en << 12); |
| 2601 | mii_mgr_write(port, 0, phy_value); |
| 2602 | printf("write phy_value:0x%x\r\n", phy_value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2603 | } /*end phy_set_an */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2604 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2605 | void set_mac_pfc(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2606 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2607 | unsigned int value = 0; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2608 | unsigned int port, enable = 0; |
| 2609 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2610 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2611 | errno = 0; |
| 2612 | port = strtoul(argv[3], &endptr, 10); |
| 2613 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 2614 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 2615 | return; |
| 2616 | } |
| 2617 | |
| 2618 | errno = 0; |
| 2619 | enable = strtoul(argv[4], &endptr, 10); |
| 2620 | if (errno != 0 || *endptr != '\0' || enable > 1) { |
| 2621 | printf("Error: Illegal paramete, enable|diable:0|1\n"); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2622 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2623 | } |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2624 | printf("enable: %d\n", enable); |
| 2625 | |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 2626 | if (chip_name == 0x7531 || chip_name == 0x7988) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2627 | reg_read(REG_PFC_CTRL_ADDR, &value); |
| 2628 | value &= ~(1 << port); |
| 2629 | value |= (enable << port); |
| 2630 | printf("write reg: %x, value: %x\n", REG_PFC_CTRL_ADDR, value); |
| 2631 | reg_write(REG_PFC_CTRL_ADDR, value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2632 | } else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2633 | printf("\nCommand not support by this chip.\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2634 | } |
| 2635 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2636 | void global_set_mac_fc(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2637 | { |
| 2638 | unsigned char enable = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2639 | unsigned int value = 0, reg = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2640 | |
| 2641 | if (chip_name == 0x7530) { |
| 2642 | enable = atoi(argv[3]); |
| 2643 | printf("enable: %d\n", enable); |
| 2644 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2645 | /*Check the input parameters is right or not. */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2646 | if (enable > 1) { |
| 2647 | printf(HELP_MACCTL_FC); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2648 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2649 | } |
| 2650 | reg_write(0x7000, 0x3); |
| 2651 | reg = REG_GFCCR0_ADDR; |
| 2652 | reg_read(REG_GFCCR0_ADDR, &value); |
| 2653 | value &= (~REG_FC_EN_MASK); |
| 2654 | value |= (enable << REG_FC_EN_OFFT); |
| 2655 | printf("write reg: %x, value: %x\n", reg, value); |
| 2656 | reg_write(REG_GFCCR0_ADDR, value); |
| 2657 | } else |
| 2658 | printf("\r\nCommand not support by this chip.\n"); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2659 | } /*end mac_set_fc */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2660 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2661 | void qos_sch_select(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2662 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2663 | unsigned char port = 0, queue = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2664 | unsigned char type = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2665 | unsigned int value = 0, reg = 0; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2666 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2667 | |
| 2668 | if (argc < 7) |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2669 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2670 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2671 | errno = 0; |
| 2672 | port = strtoul(argv[3], &endptr, 10); |
| 2673 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 2674 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 2675 | return; |
| 2676 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2677 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2678 | errno = 0; |
| 2679 | queue = strtoul(argv[4], &endptr, 10); |
| 2680 | if (errno != 0 || *endptr != '\0' || queue > 7) { |
| 2681 | printf("Error: wrong port queue member\n"); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2682 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2683 | } |
| 2684 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2685 | errno = 0; |
| 2686 | type = strtoul(argv[6], &endptr, 10); |
| 2687 | if (errno != 0 || *endptr != '\0' || type > 2) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2688 | printf(HELP_QOS_TYPE); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2689 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2690 | } |
| 2691 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2692 | printf("\r\nswitch qos type: %d.\n", type); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2693 | |
| 2694 | if (!strncmp(argv[5], "min", 4)) { |
| 2695 | |
| 2696 | if (type == 0) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2697 | /*min sharper-->round roubin, disable min sharper rate limit */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2698 | reg = GSW_MMSCR0_Q(queue) + 0x100 * port; |
| 2699 | reg_read(reg, &value); |
| 2700 | value = 0x0; |
| 2701 | reg_write(reg, value); |
| 2702 | } else if (type == 1) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2703 | /*min sharper-->sp, disable min sharper rate limit */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2704 | reg = GSW_MMSCR0_Q(queue) + 0x100 * port; |
| 2705 | reg_read(reg, &value); |
| 2706 | value = 0x0; |
| 2707 | value |= (1 << 31); |
| 2708 | reg_write(reg, value); |
| 2709 | } else { |
| 2710 | printf("min sharper only support: rr or sp\n"); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2711 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2712 | } |
| 2713 | } else if (!strncmp(argv[5], "max", 4)) { |
| 2714 | if (type == 1) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2715 | /*max sharper-->sp, disable max sharper rate limit */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2716 | reg = GSW_MMSCR1_Q(queue) + 0x100 * port; |
| 2717 | reg_read(reg, &value); |
| 2718 | value = 0x0; |
| 2719 | value |= (1 << 31); |
| 2720 | reg_write(reg, value); |
| 2721 | } else if (type == 2) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2722 | /*max sharper-->wfq, disable max sharper rate limit */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2723 | reg = GSW_MMSCR1_Q(queue) + 0x100 * port; |
| 2724 | reg_read(reg, &value); |
| 2725 | value = 0x0; |
| 2726 | reg_write(reg, value); |
| 2727 | } else { |
| 2728 | printf("max sharper only support: wfq or sp\n"); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2729 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2730 | } |
| 2731 | } else { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2732 | printf("\r\nIllegal sharper:%s\n", argv[5]); |
| 2733 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2734 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2735 | printf("reg:0x%x--value:0x%x\n", reg, value); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2736 | } |
| 2737 | |
| 2738 | void get_upw(unsigned int *value, unsigned char base) |
| 2739 | { |
| 2740 | *value &= (~((0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | |
| 2741 | (0x7 << 16) | (0x7 << 20))); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2742 | switch (base) { |
| 2743 | case 0: /* port-based 0x2x40[18:16] */ |
| 2744 | *value |= ((0x2 << 0) | (0x2 << 4) | (0x2 << 8) | |
| 2745 | (0x2 << 12) | (0x7 << 16) | (0x2 << 20)); |
| 2746 | break; |
| 2747 | case 1: /* tagged-based 0x2x40[10:8] */ |
| 2748 | *value |= ((0x2 << 0) | (0x2 << 4) | (0x7 << 8) | |
| 2749 | (0x2 << 12) | (0x2 << 16) | (0x2 << 20)); |
| 2750 | break; |
| 2751 | case 2: /* DSCP-based 0x2x40[14:12] */ |
| 2752 | *value |= ((0x2 << 0) | (0x2 << 4) | (0x2 << 8) | |
| 2753 | (0x7 << 12) | (0x2 << 16) | (0x2 << 20)); |
| 2754 | break; |
| 2755 | case 3: /* acl-based 0x2x40[2:0] */ |
| 2756 | *value |= ((0x7 << 0) | (0x2 << 4) | (0x2 << 8) | |
| 2757 | (0x2 << 12) | (0x2 << 16) | (0x2 << 20)); |
| 2758 | break; |
| 2759 | case 4: /* arl-based 0x2x40[22:20] */ |
| 2760 | *value |= ((0x2 << 0) | (0x2 << 4) | (0x2 << 8) | |
| 2761 | (0x2 << 12) | (0x2 << 16) | (0x7 << 20)); |
| 2762 | break; |
| 2763 | case 5: /* stag-based 0x2x40[6:4] */ |
| 2764 | *value |= ((0x2 << 0) | (0x7 << 4) | (0x2 << 8) | |
| 2765 | (0x2 << 12) | (0x2 << 16) | (0x2 << 20)); |
| 2766 | break; |
| 2767 | default: |
| 2768 | break; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2769 | } |
| 2770 | } |
| 2771 | |
| 2772 | void qos_set_base(int argc, char *argv[]) |
| 2773 | { |
| 2774 | unsigned char base = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2775 | unsigned char port = 0; |
| 2776 | unsigned int value = 0; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2777 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2778 | |
| 2779 | if (argc < 5) |
| 2780 | return; |
| 2781 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2782 | errno = 0; |
| 2783 | port = strtoul(argv[3], &endptr, 10); |
| 2784 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 2785 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2786 | return; |
| 2787 | } |
| 2788 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2789 | errno = 0; |
| 2790 | base = strtoul(argv[4], &endptr, 10); |
| 2791 | if (errno != 0 || *endptr != '\0' || base > 5) { |
| 2792 | printf(HELP_QOS_BASE); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2793 | return; |
| 2794 | } |
| 2795 | |
| 2796 | printf("\r\nswitch qos base : %d. (port-based:0, tag-based:1,\ |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2797 | dscp-based:2, acl-based:3, arl-based:4, stag-based:5)\n", base); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2798 | if (chip_name == 0x7530) { |
| 2799 | |
| 2800 | reg_read(0x44, &value); |
| 2801 | get_upw(&value, base); |
| 2802 | reg_write(0x44, value); |
| 2803 | printf("reg: 0x44, value: 0x%x\n", value); |
| 2804 | |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 2805 | } else if (chip_name == 0x7531 || chip_name == 0x7988) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2806 | |
| 2807 | reg_read(GSW_UPW(port), &value); |
| 2808 | get_upw(&value, base); |
| 2809 | reg_write(GSW_UPW(port), value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2810 | printf("reg:0x%x, value: 0x%x\n", GSW_UPW(port), value); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2811 | |
| 2812 | } else { |
| 2813 | printf("unknown switch device"); |
| 2814 | return; |
| 2815 | } |
| 2816 | } |
| 2817 | |
| 2818 | void qos_wfq_set_weight(int argc, char *argv[]) |
| 2819 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2820 | int port = 0, weight[8], i = 0; |
| 2821 | unsigned char queue = 0; |
| 2822 | unsigned int reg = 0, value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2823 | |
| 2824 | port = atoi(argv[3]); |
| 2825 | |
| 2826 | for (i = 0; i < 8; i++) { |
| 2827 | weight[i] = atoi(argv[i + 4]); |
| 2828 | } |
| 2829 | |
| 2830 | /* MT7530 total 7 port */ |
| 2831 | if (port < 0 || port > 6) { |
| 2832 | printf(HELP_QOS_PORT_WEIGHT); |
| 2833 | return; |
| 2834 | } |
| 2835 | |
| 2836 | for (i = 0; i < 8; i++) { |
| 2837 | if (weight[i] < 1 || weight[i] > 16) { |
| 2838 | printf(HELP_QOS_PORT_WEIGHT); |
| 2839 | return; |
| 2840 | } |
| 2841 | } |
| 2842 | printf("port: %x, q0: %x, q1: %x, q2: %x, q3: %x, \ |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2843 | q4: %x, q5: %x, q6: %x, q7: %x\n", port, weight[0], weight[1], weight[2], weight[3], weight[4], weight[5], weight[6], weight[7]); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2844 | |
| 2845 | for (queue = 0; queue < 8; queue++) { |
| 2846 | reg = GSW_MMSCR1_Q(queue) + 0x100 * port; |
| 2847 | reg_read(reg, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2848 | value &= (~(0xf << 24)); //bit24~27 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2849 | value |= (((weight[queue] - 1) & 0xf) << 24); |
| 2850 | printf("reg: %x, value: %x\n", reg, value); |
| 2851 | reg_write(reg, value); |
| 2852 | } |
| 2853 | } |
| 2854 | |
| 2855 | void qos_set_portpri(int argc, char *argv[]) |
| 2856 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2857 | unsigned char port = 0, prio = 0; |
| 2858 | unsigned int value = 0; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2859 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2860 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2861 | errno = 0; |
| 2862 | port = strtoul(argv[3], &endptr, 10); |
| 2863 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 2864 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 2865 | return; |
| 2866 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2867 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2868 | errno = 0; |
| 2869 | prio = strtoul(argv[4], &endptr, 10); |
| 2870 | if (errno != 0 || *endptr != '\0' || prio > 7) { |
| 2871 | printf("Error: wrong priority, should be within 0~7\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2872 | return; |
| 2873 | } |
| 2874 | |
| 2875 | reg_read(GSW_PCR(port), &value); |
| 2876 | value &= (~(0x7 << 24)); |
| 2877 | value |= (prio << 24); |
| 2878 | reg_write(GSW_PCR(port), value); |
| 2879 | printf("write reg: %x, value: %x\n", GSW_PCR(port), value); |
| 2880 | } |
| 2881 | |
| 2882 | void qos_set_dscppri(int argc, char *argv[]) |
| 2883 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2884 | unsigned char prio = 0, dscp = 0, pim_n = 0, pim_offset = 0; |
| 2885 | unsigned int value = 0, reg = 0; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2886 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2887 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2888 | errno = 0; |
| 2889 | dscp = strtoul(argv[3], &endptr, 10); |
| 2890 | if (errno != 0 || *endptr != '\0' || dscp > 63) { |
| 2891 | printf(HELP_QOS_DSCP_PRIO); |
| 2892 | return; |
| 2893 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2894 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2895 | errno = 0; |
| 2896 | prio = strtoul(argv[4], &endptr, 10); |
| 2897 | if (errno != 0 || *endptr != '\0' || prio > 7) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2898 | printf(HELP_QOS_DSCP_PRIO); |
| 2899 | return; |
| 2900 | } |
| 2901 | |
| 2902 | pim_n = dscp / 10; |
| 2903 | pim_offset = (dscp - pim_n * 10) * 3; |
| 2904 | reg = 0x0058 + pim_n * 4; |
| 2905 | reg_read(reg, &value); |
| 2906 | value &= (~(0x7 << pim_offset)); |
| 2907 | value |= ((prio & 0x7) << pim_offset); |
| 2908 | reg_write(reg, value); |
| 2909 | printf("write reg: %x, value: %x\n", reg, value); |
| 2910 | } |
| 2911 | |
| 2912 | void qos_pri_mapping_queue(int argc, char *argv[]) |
| 2913 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2914 | unsigned char prio = 0, queue = 0, pem_n = 0, port = 0; |
| 2915 | unsigned int value = 0, reg = 0; |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2916 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2917 | |
| 2918 | if (argc < 6) |
| 2919 | return; |
| 2920 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2921 | errno = 0; |
| 2922 | port = strtoul(argv[3], &endptr, 10); |
| 2923 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 2924 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 2925 | return; |
| 2926 | } |
| 2927 | |
| 2928 | errno = 0; |
| 2929 | prio = strtoul(argv[4], &endptr, 10); |
| 2930 | if (errno != 0 || *endptr != '\0' || prio > 7) { |
| 2931 | printf(HELP_QOS_PRIO_QMAP); |
| 2932 | return; |
| 2933 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2934 | |
developer | 546b279 | 2024-06-15 20:31:38 +0800 | [diff] [blame] | 2935 | errno = 0; |
| 2936 | queue = strtoul(argv[5], &endptr, 10); |
| 2937 | if (errno != 0 || *endptr != '\0' || queue > 7) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2938 | printf(HELP_QOS_PRIO_QMAP); |
| 2939 | return; |
| 2940 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2941 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2942 | if (chip_name == 0x7530) { |
| 2943 | pem_n = prio / 2; |
| 2944 | reg = pem_n * 0x4 + 0x48; |
| 2945 | reg_read(reg, &value); |
| 2946 | if (prio % 2) { |
| 2947 | value &= (~(0x7 << 24)); |
| 2948 | value |= ((queue & 0x7) << 24); |
| 2949 | } else { |
| 2950 | value &= (~(0x7 << 8)); |
| 2951 | value |= ((queue & 0x7) << 8); |
| 2952 | } |
| 2953 | reg_write(reg, value); |
| 2954 | printf("write reg: %x, value: %x\n", reg, value); |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 2955 | } else if (chip_name == 0x7531 || chip_name == 0x7988) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2956 | pem_n = prio / 2; |
| 2957 | reg = GSW_PEM(pem_n) + 0x100 * port; |
| 2958 | reg_read(reg, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2959 | if (prio % 2) { // 1 1 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2960 | value &= (~(0x7 << 25)); |
| 2961 | value |= ((queue & 0x7) << 25); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2962 | } else { // 0 0 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2963 | value &= (~(0x7 << 9)); |
| 2964 | value |= ((queue & 0x7) << 9); |
| 2965 | } |
| 2966 | reg_write(reg, value); |
| 2967 | printf("write reg: %x, value: %x\n", reg, value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2968 | } else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2969 | printf("unknown switch device"); |
| 2970 | return; |
| 2971 | } |
| 2972 | } |
| 2973 | |
| 2974 | static int macMT753xVlanSetVid(unsigned char index, unsigned char active, |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2975 | unsigned short vid, unsigned char portMap, |
| 2976 | unsigned char tagPortMap, unsigned char ivl_en, |
| 2977 | unsigned char fid, unsigned short stag) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2978 | { |
| 2979 | unsigned int value = 0; |
| 2980 | unsigned int value2 = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2981 | unsigned int reg = 0; |
| 2982 | int i = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2983 | |
| 2984 | printf("index: %x, active: %x, vid: %x, portMap: %x, \ |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 2985 | tagPortMap: %x, ivl_en: %x, fid: %x, stag: %x\n", index, active, vid, portMap, tagPortMap, ivl_en, fid, stag); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2986 | |
| 2987 | value = (portMap << 16); |
| 2988 | value |= (stag << 4); |
| 2989 | value |= (ivl_en << 30); |
| 2990 | value |= (fid << 1); |
| 2991 | value |= (active ? 1 : 0); |
| 2992 | |
| 2993 | // total 7 ports |
| 2994 | for (i = 0; i < 7; i++) { |
| 2995 | if (tagPortMap & (1 << i)) |
| 2996 | value2 |= 0x2 << (i * 2); |
| 2997 | } |
| 2998 | |
| 2999 | if (value2) |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3000 | value |= (1 << 28); // eg_tag |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3001 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3002 | reg = 0x98; // VAWD2 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3003 | reg_write(reg, value2); |
| 3004 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3005 | reg = 0x94; // VAWD1 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3006 | reg_write(reg, value); |
| 3007 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3008 | reg = 0x90; // VTCR |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3009 | value = (0x80001000 + vid); |
| 3010 | reg_write(reg, value); |
| 3011 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3012 | reg = 0x90; // VTCR |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3013 | while (1) { |
| 3014 | reg_read(reg, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3015 | if ((value & 0x80000000) == 0) //table busy |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3016 | break; |
| 3017 | } |
| 3018 | |
| 3019 | /* switch clear */ |
| 3020 | reg = 0x80; |
| 3021 | reg_write(reg, 0x8002); |
| 3022 | usleep(5000); |
| 3023 | reg_read(reg, &value); |
| 3024 | |
| 3025 | printf("SetVid: index:%d active:%d vid:%d portMap:%x tagPortMap:%x\r\n", |
| 3026 | index, active, vid, portMap, tagPortMap); |
| 3027 | return 0; |
| 3028 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3029 | } /*end macMT753xVlanSetVid */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3030 | |
| 3031 | static int macMT753xVlanSetPvid(unsigned char port, unsigned short pvid) |
| 3032 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3033 | unsigned int value = 0; |
| 3034 | unsigned int reg = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3035 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3036 | /*Parameters is error */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3037 | if (port > 6) |
| 3038 | return -1; |
| 3039 | |
| 3040 | reg = 0x2014 + (port * 0x100); |
| 3041 | reg_read(reg, &value); |
| 3042 | value &= ~0xfff; |
| 3043 | value |= pvid; |
| 3044 | reg_write(reg, value); |
| 3045 | |
| 3046 | /* switch clear */ |
| 3047 | reg = 0x80; |
| 3048 | reg_write(reg, 0x8002); |
| 3049 | usleep(5000); |
| 3050 | reg_read(reg, &value); |
| 3051 | |
| 3052 | printf("SetPVID: port:%d pvid:%d\r\n", port, pvid); |
| 3053 | return 0; |
| 3054 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3055 | |
| 3056 | void doVlanSetPvid(int argc, char *argv[]) |
| 3057 | { |
| 3058 | unsigned char port = 0; |
| 3059 | unsigned short pvid = 0; |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3060 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3061 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3062 | errno = 0; |
| 3063 | port = strtoul(argv[3], &endptr, 10); |
| 3064 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 3065 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 3066 | return; |
| 3067 | } |
| 3068 | |
| 3069 | errno = 0; |
| 3070 | pvid = strtoul(argv[4], &endptr, 10); |
| 3071 | if (errno != 0 || *endptr != '\0' || pvid > MAX_VID_VALUE) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3072 | printf(HELP_VLAN_PVID); |
| 3073 | return; |
| 3074 | } |
| 3075 | |
| 3076 | macMT753xVlanSetPvid(port, pvid); |
| 3077 | |
| 3078 | printf("port:%d pvid:%d,vlancap: max_port:%d maxvid:%d\r\n", |
| 3079 | port, pvid, SWITCH_MAX_PORT, MAX_VID_VALUE); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3080 | } /*end doVlanSetPvid */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3081 | |
| 3082 | void doVlanSetVid(int argc, char *argv[]) |
| 3083 | { |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3084 | unsigned char index = 0, active = 0; |
| 3085 | unsigned char portMap = 0, tagPortMap = 0; |
| 3086 | unsigned short vid = 0, stag = 0; |
| 3087 | unsigned char ivl_en = 0, fid = 0; |
| 3088 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3089 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3090 | errno = 0; |
| 3091 | index = strtoul(argv[3], &endptr, 10); |
| 3092 | if (errno != 0 || *endptr != '\0' || index >= MAX_VLAN_RULE) { |
| 3093 | printf(HELP_VLAN_VID); |
| 3094 | return; |
| 3095 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3096 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3097 | errno = 0; |
| 3098 | active = strtoul(argv[4], &endptr, 10); |
| 3099 | if (errno != 0 || *endptr != '\0' || active > ACTIVED) { |
| 3100 | printf(HELP_VLAN_VID); |
| 3101 | return; |
| 3102 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3103 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3104 | errno = 0; |
| 3105 | vid = strtoul(argv[5], &endptr, 10); |
| 3106 | if (errno != 0 || *endptr != '\0' || vid >= 4096) { |
| 3107 | printf(HELP_VLAN_VID); |
| 3108 | return; |
| 3109 | } |
| 3110 | |
| 3111 | errno = 0; |
| 3112 | portMap = strtoul(argv[6], &endptr, 10); |
| 3113 | if (errno != 0 || *endptr != '\0') { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3114 | printf(HELP_VLAN_VID); |
| 3115 | return; |
| 3116 | } |
| 3117 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3118 | errno = 0; |
| 3119 | tagPortMap = strtoul(argv[7], &endptr, 10); |
| 3120 | if (errno != 0 || *endptr != '\0') { |
| 3121 | printf(HELP_VLAN_VID); |
| 3122 | return; |
| 3123 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3124 | |
| 3125 | printf("subcmd parameter argc = %d\r\n", argc); |
| 3126 | if (argc >= 9) { |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3127 | errno = 0; |
| 3128 | ivl_en = strtoul(argv[8], &endptr, 10); |
| 3129 | if (errno != 0 || *endptr != '\0') { |
| 3130 | printf(HELP_VLAN_VID); |
| 3131 | return; |
| 3132 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3133 | if (argc >= 10) { |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3134 | errno = 0; |
| 3135 | fid = strtoul(argv[9], &endptr, 16); |
| 3136 | if (errno != 0 || *endptr != '\0') { |
| 3137 | printf(HELP_VLAN_VID); |
| 3138 | return; |
| 3139 | } |
| 3140 | if (argc >= 11) { |
| 3141 | errno = 0; |
| 3142 | stag = strtoul(argv[10], &endptr, 10); |
| 3143 | if (errno != 0 || *endptr != '\0') { |
| 3144 | printf(HELP_VLAN_VID); |
| 3145 | return; |
| 3146 | } |
| 3147 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3148 | } |
| 3149 | } |
| 3150 | macMT753xVlanSetVid(index, active, vid, portMap, tagPortMap, |
| 3151 | ivl_en, fid, stag); |
| 3152 | printf("index:%d active:%d vid:%d\r\n", index, active, vid); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3153 | } /*end doVlanSetVid */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3154 | |
| 3155 | void doVlanSetAccFrm(int argc, char *argv[]) |
| 3156 | { |
| 3157 | unsigned char port = 0; |
| 3158 | unsigned char type = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3159 | unsigned int value = 0; |
| 3160 | unsigned int reg = 0; |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3161 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3162 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3163 | errno = 0; |
| 3164 | port = strtoul(argv[3], &endptr, 10); |
| 3165 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 3166 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 3167 | return; |
| 3168 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3169 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3170 | errno = 0; |
| 3171 | type = strtoul(argv[4], &endptr, 10); |
| 3172 | if (errno != 0 || *endptr != '\0' || type > REG_PVC_ACC_FRM_RELMASK) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3173 | printf(HELP_VLAN_ACC_FRM); |
| 3174 | return; |
| 3175 | } |
| 3176 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3177 | printf("port: %d, type: %d\n", port, type); |
| 3178 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3179 | reg = REG_PVC_P0_ADDR + port * 0x100; |
| 3180 | reg_read(reg, &value); |
| 3181 | value &= (~REG_PVC_ACC_FRM_MASK); |
| 3182 | value |= ((unsigned int)type << REG_PVC_ACC_FRM_OFFT); |
| 3183 | |
| 3184 | printf("write reg: %x, value: %x\n", reg, value); |
| 3185 | reg_write(reg, value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3186 | } /*end doVlanSetAccFrm */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3187 | |
| 3188 | void doVlanSetPortAttr(int argc, char *argv[]) |
| 3189 | { |
| 3190 | unsigned char port = 0; |
| 3191 | unsigned char attr = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3192 | unsigned int value = 0; |
| 3193 | unsigned int reg = 0; |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3194 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3195 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3196 | errno = 0; |
| 3197 | port = strtoul(argv[3], &endptr, 10); |
| 3198 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 3199 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 3200 | return; |
| 3201 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3202 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3203 | errno = 0; |
| 3204 | attr = strtoul(argv[4], &endptr, 10); |
| 3205 | if (errno != 0 || *endptr != '\0' || attr > 3) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3206 | printf(HELP_VLAN_PORT_ATTR); |
| 3207 | return; |
| 3208 | } |
| 3209 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3210 | printf("port: %x, attr: %x\n", port, attr); |
| 3211 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3212 | reg = 0x2010 + port * 0x100; |
| 3213 | reg_read(reg, &value); |
| 3214 | value &= (0xffffff3f); |
| 3215 | value |= (attr << 6); |
| 3216 | |
| 3217 | printf("write reg: %x, value: %x\n", reg, value); |
| 3218 | reg_write(reg, value); |
| 3219 | } |
| 3220 | |
| 3221 | void doVlanSetPortMode(int argc, char *argv[]) |
| 3222 | { |
| 3223 | unsigned char port = 0; |
| 3224 | unsigned char mode = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3225 | unsigned int value = 0; |
| 3226 | unsigned int reg = 0; |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3227 | char *endptr; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3228 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3229 | errno = 0; |
| 3230 | port = strtoul(argv[3], &endptr, 10); |
| 3231 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 3232 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 3233 | return; |
| 3234 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3235 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3236 | errno = 0; |
| 3237 | mode = strtoul(argv[4], &endptr, 10); |
| 3238 | if (errno != 0 || *endptr != '\0' || mode > 3) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3239 | printf(HELP_VLAN_PORT_MODE); |
| 3240 | return; |
| 3241 | } |
| 3242 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3243 | printf("port: %x, mode: %x\n", port, mode); |
| 3244 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3245 | reg = 0x2004 + port * 0x100; |
| 3246 | reg_read(reg, &value); |
| 3247 | value &= (~((1 << 0) | (1 << 1))); |
| 3248 | value |= (mode & 0x3); |
| 3249 | printf("write reg: %x, value: %x\n", reg, value); |
| 3250 | reg_write(reg, value); |
| 3251 | } |
| 3252 | |
| 3253 | void doVlanSetEgressTagPCR(int argc, char *argv[]) |
| 3254 | { |
| 3255 | unsigned char port = 0; |
| 3256 | unsigned char eg_tag = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3257 | unsigned int value = 0; |
| 3258 | unsigned int reg = 0; |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3259 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3260 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3261 | errno = 0; |
| 3262 | port = strtoul(argv[3], &endptr, 10); |
| 3263 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 3264 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 3265 | return; |
| 3266 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3267 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3268 | errno = 0; |
| 3269 | eg_tag = strtoul(argv[4], &endptr, 10); |
| 3270 | if (errno != 0 || *endptr != '\0' || (eg_tag > REG_PCR_EG_TAG_RELMASK)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3271 | printf(HELP_VLAN_EGRESS_TAG_PCR); |
| 3272 | return; |
| 3273 | } |
| 3274 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3275 | printf("port: %d, eg_tag: %d\n", port, eg_tag); |
| 3276 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3277 | reg = REG_PCR_P0_ADDR + port * 0x100; |
| 3278 | reg_read(reg, &value); |
| 3279 | value &= (~REG_PCR_EG_TAG_MASK); |
| 3280 | value |= ((unsigned int)eg_tag << REG_PCR_EG_TAG_OFFT); |
| 3281 | |
| 3282 | printf("write reg: %x, value: %x\n", reg, value); |
| 3283 | reg_write(reg, value); |
| 3284 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3285 | } /*end doVlanSetEgressTagPCR */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3286 | |
| 3287 | void doVlanSetEgressTagPVC(int argc, char *argv[]) |
| 3288 | { |
| 3289 | unsigned char port = 0; |
| 3290 | unsigned char eg_tag = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3291 | unsigned int value = 0; |
| 3292 | unsigned int reg = 0; |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3293 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3294 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3295 | errno = 0; |
| 3296 | port = strtoul(argv[3], &endptr, 10); |
| 3297 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 3298 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 3299 | return; |
| 3300 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3301 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3302 | errno = 0; |
| 3303 | eg_tag = strtoul(argv[4], &endptr, 10); |
| 3304 | if (errno != 0 || *endptr != '\0' || (eg_tag > REG_PVC_EG_TAG_RELMASK)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3305 | printf(HELP_VLAN_EGRESS_TAG_PVC); |
| 3306 | return; |
| 3307 | } |
| 3308 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3309 | printf("port: %d, eg_tag: %d\n", port, eg_tag); |
| 3310 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3311 | reg = REG_PVC_P0_ADDR + port * 0x100; |
| 3312 | reg_read(reg, &value); |
| 3313 | value &= (~REG_PVC_EG_TAG_MASK); |
| 3314 | value |= ((unsigned int)eg_tag << REG_PVC_EG_TAG_OFFT); |
| 3315 | |
| 3316 | printf("write reg: %x, value: %x\n", reg, value); |
| 3317 | reg_write(reg, value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3318 | } /*end doVlanSetEgressTagPVC */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3319 | |
| 3320 | void doArlAging(int argc, char *argv[]) |
| 3321 | { |
| 3322 | unsigned char aging_en = 0; |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3323 | unsigned int time = 0, aging_cnt = 0, aging_unit = 0; |
| 3324 | unsigned int value = 0, reg = 0; |
| 3325 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3326 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3327 | errno = 0; |
| 3328 | aging_en = strtoul(argv[3], &endptr, 10); |
| 3329 | if (errno != 0 || *endptr != '\0' || aging_en > 1) { |
| 3330 | printf(HELP_ARL_AGING); |
| 3331 | return; |
| 3332 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3333 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3334 | errno = 0; |
| 3335 | time = strtoul(argv[4], &endptr, 10); |
| 3336 | if (errno != 0 || *endptr != '\0' || (time <= 0 || time > 65536)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3337 | printf(HELP_ARL_AGING); |
| 3338 | return; |
| 3339 | } |
| 3340 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3341 | printf("aging_en: %x, aging time: %x\n", aging_en, time); |
| 3342 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3343 | reg = 0xa0; |
| 3344 | reg_read(reg, &value); |
| 3345 | value &= (~(1 << 20)); |
| 3346 | if (!aging_en) { |
| 3347 | value |= (1 << 20); |
| 3348 | } |
| 3349 | |
| 3350 | aging_unit = (time / 0x100) + 1; |
| 3351 | aging_cnt = (time / aging_unit); |
| 3352 | aging_unit--; |
| 3353 | aging_cnt--; |
| 3354 | |
| 3355 | value &= (0xfff00000); |
| 3356 | value |= ((aging_cnt << 12) | aging_unit); |
| 3357 | |
| 3358 | printf("aging_unit: %x, aging_cnt: %x\n", aging_unit, aging_cnt); |
| 3359 | printf("write reg: %x, value: %x\n", reg, value); |
| 3360 | |
| 3361 | reg_write(reg, value); |
| 3362 | } |
| 3363 | |
| 3364 | void doMirrorEn(int argc, char *argv[]) |
| 3365 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3366 | unsigned char mirror_en = 0; |
| 3367 | unsigned char mirror_port = 0; |
| 3368 | unsigned int value = 0, reg = 0; |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3369 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3370 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3371 | errno = 0; |
| 3372 | mirror_en = strtoul(argv[3], &endptr, 10); |
| 3373 | if (errno != 0 || *endptr != '\0' || mirror_en > 1) { |
| 3374 | printf(HELP_MIRROR_EN); |
| 3375 | return; |
| 3376 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3377 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3378 | errno = 0; |
| 3379 | mirror_port = strtoul(argv[4], &endptr, 10); |
| 3380 | if (errno != 0 || *endptr != '\0' || mirror_port > REG_CFC_MIRROR_PORT_RELMASK) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3381 | printf(HELP_MIRROR_EN); |
| 3382 | return; |
| 3383 | } |
| 3384 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3385 | printf("mirror_en: %d, mirror_port: %d\n", mirror_en, mirror_port); |
| 3386 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3387 | reg = REG_CFC_ADDR; |
| 3388 | reg_read(reg, &value); |
| 3389 | value &= (~REG_CFC_MIRROR_EN_MASK); |
| 3390 | value |= (mirror_en << REG_CFC_MIRROR_EN_OFFT); |
| 3391 | value &= (~REG_CFC_MIRROR_PORT_MASK); |
| 3392 | value |= (mirror_port << REG_CFC_MIRROR_PORT_OFFT); |
| 3393 | |
| 3394 | printf("write reg: %x, value: %x\n", reg, value); |
| 3395 | reg_write(reg, value); |
| 3396 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3397 | } /*end doMirrorEn */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3398 | |
| 3399 | void doMirrorPortBased(int argc, char *argv[]) |
| 3400 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3401 | unsigned char port = 0, port_tx_mir = 0, port_rx_mir = 0, vlan_mis = |
| 3402 | 0, acl_mir = 0, igmp_mir = 0; |
| 3403 | unsigned int value = 0, reg = 0; |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3404 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3405 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3406 | errno = 0; |
| 3407 | port = strtoul(argv[3], &endptr, 10); |
| 3408 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) |
| 3409 | goto error; |
| 3410 | |
| 3411 | errno = 0; |
| 3412 | port_tx_mir = strtoul(argv[4], &endptr, 10); |
| 3413 | if (errno != 0 || *endptr != '\0' || port_tx_mir > 1) |
| 3414 | goto error; |
| 3415 | |
| 3416 | errno = 0; |
| 3417 | port_rx_mir = strtoul(argv[5], &endptr, 10); |
| 3418 | if (errno != 0 || *endptr != '\0' || port_rx_mir > 1) |
| 3419 | goto error; |
| 3420 | |
| 3421 | errno = 0; |
| 3422 | acl_mir = strtoul(argv[6], &endptr, 10); |
| 3423 | if (errno != 0 || *endptr != '\0' || acl_mir > 1) |
| 3424 | goto error; |
| 3425 | |
| 3426 | errno = 0; |
| 3427 | vlan_mis = strtoul(argv[7], &endptr, 10); |
| 3428 | if (errno != 0 || *endptr != '\0' || vlan_mis > 1) |
| 3429 | goto error; |
| 3430 | |
| 3431 | errno = 0; |
| 3432 | igmp_mir = strtoul(argv[8], &endptr, 10); |
| 3433 | if (errno != 0 || *endptr != '\0' || igmp_mir > 1) |
| 3434 | goto error; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3435 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3436 | printf |
| 3437 | ("port:%d, port_tx_mir:%d, port_rx_mir:%d, acl_mir:%d, vlan_mis:%d, igmp_mir:%d\n", |
| 3438 | port, port_tx_mir, port_rx_mir, acl_mir, vlan_mis, igmp_mir); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3439 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3440 | reg = REG_PCR_P0_ADDR + port * 0x100; |
| 3441 | reg_read(reg, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3442 | value &= |
| 3443 | ~(REG_PORT_TX_MIR_MASK | REG_PORT_RX_MIR_MASK | REG_PCR_ACL_MIR_MASK |
| 3444 | | REG_PCR_VLAN_MIS_MASK); |
| 3445 | value |= |
| 3446 | (port_tx_mir << REG_PORT_TX_MIR_OFFT) + |
| 3447 | (port_rx_mir << REG_PORT_RX_MIR_OFFT); |
| 3448 | value |= |
| 3449 | (acl_mir << REG_PCR_ACL_MIR_OFFT) + |
| 3450 | (vlan_mis << REG_PCR_VLAN_MIS_OFFT); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3451 | |
| 3452 | printf("write reg: %x, value: %x\n", reg, value); |
| 3453 | reg_write(reg, value); |
| 3454 | |
| 3455 | reg = REG_PIC_P0_ADDR + port * 0x100; |
| 3456 | reg_read(reg, &value); |
| 3457 | value &= ~(REG_PIC_IGMP_MIR_MASK); |
| 3458 | value |= (igmp_mir << REG_PIC_IGMP_MIR_OFFT); |
| 3459 | |
| 3460 | printf("write reg: %x, value: %x\n", reg, value); |
| 3461 | reg_write(reg, value); |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3462 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3463 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3464 | error: |
| 3465 | printf(HELP_MIRROR_PORTBASED); |
| 3466 | return; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3467 | } /*end doMirrorPortBased */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3468 | |
| 3469 | void doStp(int argc, char *argv[]) |
| 3470 | { |
| 3471 | unsigned char port = 0; |
| 3472 | unsigned char fid = 0; |
| 3473 | unsigned char state = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3474 | unsigned int value = 0; |
| 3475 | unsigned int reg = 0; |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3476 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3477 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3478 | errno = 0; |
| 3479 | port = strtoul(argv[2], &endptr, 10); |
| 3480 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 3481 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 3482 | return; |
| 3483 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3484 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3485 | errno = 0; |
| 3486 | fid = strtoul(argv[3], &endptr, 10); |
| 3487 | if (errno != 0 || *endptr != '\0' || fid > 7) { |
| 3488 | printf(HELP_STP); |
| 3489 | return; |
| 3490 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3491 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3492 | errno = 0; |
| 3493 | state = strtoul(argv[4], &endptr, 10); |
| 3494 | if (errno != 0 || *endptr != '\0' || state > 3) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3495 | printf(HELP_STP); |
| 3496 | return; |
| 3497 | } |
| 3498 | |
developer | 2fdae31 | 2024-06-15 20:36:12 +0800 | [diff] [blame^] | 3499 | printf("port: %d, fid: %d, state: %d\n", port, fid, state); |
| 3500 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3501 | reg = REG_SSC_P0_ADDR + port * 0x100; |
| 3502 | reg_read(reg, &value); |
| 3503 | value &= (~(3 << (fid << 2))); |
| 3504 | value |= ((unsigned int)state << (fid << 2)); |
| 3505 | |
| 3506 | printf("write reg: %x, value: %x\n", reg, value); |
| 3507 | reg_write(reg, value); |
| 3508 | } |
| 3509 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3510 | void _ingress_rate_set(int on_off, int port, int bw) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3511 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3512 | unsigned int reg = 0, value = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3513 | |
| 3514 | reg = 0x1800 + (0x100 * port); |
| 3515 | value = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3516 | /*token-bucket */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3517 | if (on_off == 1) { |
| 3518 | if (chip_name == 0x7530) { |
| 3519 | if (bw > 1000000) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3520 | printf |
| 3521 | ("\n**Charge rate(%d) is larger than line rate(1000000kbps)**\n", |
| 3522 | bw); |
| 3523 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3524 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3525 | value = |
| 3526 | ((bw / 32) << 16) + (1 << 15) + (7 << 8) + |
| 3527 | (1 << 7) + 0x0f; |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 3528 | } else if (chip_name == 0x7531 || chip_name == 0x7988) { |
| 3529 | if ((chip_name == 0x7531) && (bw > 2500000)) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3530 | printf |
| 3531 | ("\n**Charge rate(%d) is larger than line rate(2500000kbps)**\n", |
| 3532 | bw); |
| 3533 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3534 | } |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 3535 | |
| 3536 | if ((chip_name == 0x7988) && (bw > 4000000)) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3537 | printf |
| 3538 | ("\n**Charge rate(%d) is larger than line rate(4000000kbps)**\n", |
| 3539 | bw); |
| 3540 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3541 | } |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 3542 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3543 | if (bw / 32 >= 65536) //supoort 2.5G case |
| 3544 | value = |
| 3545 | ((bw / 32) << 16) + (1 << 15) + (1 << 14) + |
| 3546 | (1 << 12) + (7 << 8) + 0xf; |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 3547 | else |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3548 | value = |
| 3549 | ((bw / 32) << 16) + (1 << 15) + (1 << 14) + |
| 3550 | (7 << 8) + 0xf; |
| 3551 | } else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3552 | printf("unknow chip\n"); |
| 3553 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3554 | #if leaky_bucket |
| 3555 | reg_read(reg, &value); |
| 3556 | value &= 0xffff0000; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3557 | if (on_off == 1) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3558 | value |= on_off << 15; |
| 3559 | //7530 same as 7531 |
| 3560 | if (bw < 100) { |
| 3561 | value |= (0x0 << 8); |
| 3562 | value |= bw; |
| 3563 | } else if (bw < 1000) { |
| 3564 | value |= (0x1 << 8); |
| 3565 | value |= bw / 10; |
| 3566 | } else if (bw < 10000) { |
| 3567 | value |= (0x2 << 8); |
| 3568 | value |= bw / 100; |
| 3569 | } else if (bw < 100000) { |
| 3570 | value |= (0x3 << 8); |
| 3571 | value |= bw / 1000; |
| 3572 | } else { |
| 3573 | value |= (0x4 << 8); |
| 3574 | value |= bw / 10000; |
| 3575 | } |
| 3576 | } |
| 3577 | #endif |
| 3578 | reg_write(reg, value); |
| 3579 | reg = 0x1FFC; |
| 3580 | reg_read(reg, &value); |
| 3581 | value = 0x110104; |
| 3582 | reg_write(reg, value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3583 | |
| 3584 | if (on_off) |
| 3585 | printf("switch port=%d, bw=%d\n", port, bw); |
| 3586 | else |
| 3587 | printf("switch port=%d ingress rate limit off\n", port); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3588 | } |
| 3589 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3590 | void ingress_rate_set(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3591 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3592 | int on_off = 0, port = 0, bw = 0; |
developer | 997ed6b | 2024-03-26 14:03:42 +0800 | [diff] [blame] | 3593 | char *endptr; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3594 | |
developer | 997ed6b | 2024-03-26 14:03:42 +0800 | [diff] [blame] | 3595 | /* clear errno before conversion to detect overflow */ |
| 3596 | errno = 0; |
| 3597 | port = strtoul(argv[3], &endptr, 0); |
| 3598 | |
| 3599 | if (errno == ERANGE) { |
| 3600 | printf("Conversion error, value out of range\n"); |
| 3601 | return; |
| 3602 | } |
| 3603 | if (*endptr != '\0') { |
| 3604 | printf("Conversion error, no digits were found\n"); |
| 3605 | return; |
| 3606 | } |
| 3607 | |
| 3608 | if (port < 0 || port > 6) { |
| 3609 | printf("Wrong port range, should be within 0-6\n"); |
| 3610 | return; |
| 3611 | } |
| 3612 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3613 | if (argv[2][1] == 'n') { |
developer | 997ed6b | 2024-03-26 14:03:42 +0800 | [diff] [blame] | 3614 | errno = 0; |
| 3615 | bw = strtoul(argv[4], &endptr, 0); |
| 3616 | if (errno == ERANGE) { |
| 3617 | printf("Conversion error, value out of range\n"); |
| 3618 | return; |
| 3619 | } |
| 3620 | if (*endptr != '\0') { |
| 3621 | printf("Conversion error, no digits were found\n"); |
| 3622 | return; |
| 3623 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3624 | on_off = 1; |
| 3625 | } else if (argv[2][1] == 'f') { |
| 3626 | if (argc != 4) |
| 3627 | return; |
| 3628 | on_off = 0; |
| 3629 | } |
| 3630 | |
| 3631 | _ingress_rate_set(on_off, port, bw); |
| 3632 | } |
| 3633 | |
| 3634 | void _egress_rate_set(int on_off, int port, int bw) |
| 3635 | { |
| 3636 | unsigned int value = 0, reg = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3637 | |
| 3638 | reg = 0x1040 + (0x100 * port); |
| 3639 | value = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3640 | /*token-bucket */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3641 | if (on_off == 1) { |
| 3642 | if (chip_name == 0x7530) { |
| 3643 | if (bw < 0 || bw > 1000000) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3644 | printf |
| 3645 | ("\n**Charge rate(%d) is larger than line rate(1000000kbps)**\n", |
| 3646 | bw); |
| 3647 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3648 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3649 | value = |
| 3650 | ((bw / 32) << 16) + (1 << 15) + (7 << 8) + |
| 3651 | (1 << 7) + 0xf; |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 3652 | } else if (chip_name == 0x7531 || chip_name == 0x7988) { |
| 3653 | if ((chip_name == 0x7531) && (bw < 0 || bw > 2500000)) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3654 | printf |
| 3655 | ("\n**Charge rate(%d) is larger than line rate(2500000kbps)**\n", |
| 3656 | bw); |
| 3657 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3658 | } |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 3659 | if ((chip_name == 0x7988) && (bw < 0 || bw > 4000000)) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3660 | printf |
| 3661 | ("\n**Charge rate(%d) is larger than line rate(4000000kbps)**\n", |
| 3662 | bw); |
| 3663 | return; |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 3664 | } |
| 3665 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3666 | if (bw / 32 >= 65536) //support 2.5G cases |
| 3667 | value = |
| 3668 | ((bw / 32) << 16) + (1 << 15) + (1 << 14) + |
| 3669 | (1 << 12) + (7 << 8) + 0xf; |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 3670 | else |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3671 | value = |
| 3672 | ((bw / 32) << 16) + (1 << 15) + (1 << 14) + |
| 3673 | (7 << 8) + 0xf; |
| 3674 | } else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3675 | printf("unknow chip\n"); |
| 3676 | } |
| 3677 | reg_write(reg, value); |
| 3678 | reg = 0x10E0; |
| 3679 | reg_read(reg, &value); |
| 3680 | value &= 0x18; |
| 3681 | reg_write(reg, value); |
| 3682 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3683 | if (on_off) |
| 3684 | printf("switch port=%d, bw=%d\n", port, bw); |
| 3685 | else |
| 3686 | printf("switch port=%d egress rate limit off\n", port); |
| 3687 | } |
| 3688 | |
| 3689 | void egress_rate_set(int argc, char *argv[]) |
| 3690 | { |
| 3691 | unsigned int value = 0, reg = 0; |
| 3692 | int on_off = 0, port = 0, bw = 0; |
developer | 997ed6b | 2024-03-26 14:03:42 +0800 | [diff] [blame] | 3693 | char *endptr; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3694 | |
developer | 997ed6b | 2024-03-26 14:03:42 +0800 | [diff] [blame] | 3695 | /* clear errno before conversion to detect overflow */ |
| 3696 | errno = 0; |
| 3697 | port = strtoul(argv[3], &endptr, 0); |
| 3698 | if (errno == ERANGE) { |
| 3699 | printf("Conversion error, value out of range\n"); |
| 3700 | return; |
| 3701 | } |
| 3702 | if (*endptr != '\0') { |
| 3703 | printf("Conversion error, no digits were found\n"); |
| 3704 | return; |
| 3705 | } |
| 3706 | if (port < 0 || port > 6) { |
| 3707 | printf("Wrong port range, should be within 0-6\n"); |
| 3708 | return; |
| 3709 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3710 | if (argv[2][1] == 'n') { |
developer | 997ed6b | 2024-03-26 14:03:42 +0800 | [diff] [blame] | 3711 | errno = 0; |
| 3712 | bw = strtoul(argv[4], &endptr, 0); |
| 3713 | if (errno == ERANGE) { |
| 3714 | printf("Conversion error, value out of range\n"); |
| 3715 | return; |
| 3716 | } |
| 3717 | if (*endptr != '\0') { |
| 3718 | printf("Conversion error, no digits were found\n"); |
| 3719 | return; |
| 3720 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3721 | on_off = 1; |
| 3722 | } else if (argv[2][1] == 'f') { |
| 3723 | if (argc != 4) |
| 3724 | return; |
| 3725 | on_off = 0; |
| 3726 | } |
| 3727 | |
| 3728 | _egress_rate_set(on_off, port, bw); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3729 | } |
| 3730 | |
| 3731 | void rate_control(int argc, char *argv[]) |
| 3732 | { |
| 3733 | unsigned char dir = 0; |
| 3734 | unsigned char port = 0; |
| 3735 | unsigned int rate = 0; |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3736 | char *endptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3737 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3738 | errno = 0; |
| 3739 | dir = strtoul(argv[2], &endptr, 10); |
| 3740 | if (errno != 0 || *endptr != '\0' || dir > 1) { |
| 3741 | printf("Error: wrong port member, should be 0:egress, 1:ingress\n"); |
| 3742 | return; |
| 3743 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3744 | |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3745 | errno = 0; |
| 3746 | port = strtoul(argv[3], &endptr, 10); |
| 3747 | if (errno != 0 || *endptr != '\0' || port > MAX_PORT) { |
| 3748 | printf("Error: wrong port member, should be within 0~%d\n", MAX_PORT); |
| 3749 | return; |
| 3750 | } |
| 3751 | |
| 3752 | errno = 0; |
| 3753 | rate = strtoul(argv[4], &endptr, 10); |
| 3754 | if (errno != 0 || *endptr != '\0') { |
| 3755 | printf("Error: wrong traffic rate, unit is kbps\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3756 | return; |
developer | 3a780bf | 2024-06-15 20:34:27 +0800 | [diff] [blame] | 3757 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3758 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3759 | if (dir == 1) //ingress |
| 3760 | _ingress_rate_set(1, port, rate); |
| 3761 | else if (dir == 0) //egress |
| 3762 | _egress_rate_set(1, port, rate); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3763 | } |
| 3764 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3765 | void collision_pool_enable(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3766 | { |
| 3767 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3768 | unsigned char enable = 0; |
| 3769 | unsigned int value = 0, reg = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3770 | |
| 3771 | enable = atoi(argv[3]); |
| 3772 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3773 | printf("collision pool enable: %d \n", enable); |
| 3774 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3775 | /*Check the input parameters is right or not. */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3776 | if (enable > 1) { |
| 3777 | printf(HELP_COLLISION_POOL_EN); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3778 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3779 | } |
| 3780 | |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 3781 | if (chip_name == 0x7531 || chip_name == 0x7988) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3782 | reg = REG_CPGC_ADDR; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3783 | if (enable == 1) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3784 | /* active reset */ |
| 3785 | reg_read(reg, &value); |
| 3786 | value &= (~REG_CPCG_COL_RST_N_MASK); |
| 3787 | reg_write(reg, value); |
| 3788 | |
| 3789 | /* enanble clock */ |
| 3790 | reg_read(reg, &value); |
| 3791 | value &= (~REG_CPCG_COL_CLK_EN_MASK); |
| 3792 | value |= (1 << REG_CPCG_COL_CLK_EN_OFFT); |
| 3793 | reg_write(reg, value); |
| 3794 | |
| 3795 | /* inactive reset */ |
| 3796 | reg_read(reg, &value); |
| 3797 | value &= (~REG_CPCG_COL_RST_N_MASK); |
| 3798 | value |= (1 << REG_CPCG_COL_RST_N_OFFT); |
| 3799 | reg_write(reg, value); |
| 3800 | |
| 3801 | /* enable collision pool */ |
| 3802 | reg_read(reg, &value); |
| 3803 | value &= (~REG_CPCG_COL_EN_MASK); |
| 3804 | value |= (1 << REG_CPCG_COL_EN_OFFT); |
| 3805 | reg_write(reg, value); |
| 3806 | |
| 3807 | reg_read(reg, &value); |
| 3808 | printf("write reg: %x, value: %x\n", reg, value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3809 | } else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3810 | |
| 3811 | /* disable collision pool */ |
| 3812 | reg_read(reg, &value); |
| 3813 | value &= (~REG_CPCG_COL_EN_MASK); |
| 3814 | reg_write(reg, value); |
| 3815 | |
| 3816 | /* active reset */ |
| 3817 | reg_read(reg, &value); |
| 3818 | value &= (~REG_CPCG_COL_RST_N_MASK); |
| 3819 | reg_write(reg, value); |
| 3820 | |
| 3821 | /* inactive reset */ |
| 3822 | reg_read(reg, &value); |
| 3823 | value &= (~REG_CPCG_COL_RST_N_MASK); |
| 3824 | value |= (1 << REG_CPCG_COL_RST_N_OFFT); |
| 3825 | reg_write(reg, value); |
| 3826 | |
| 3827 | /* disable clock */ |
| 3828 | reg_read(reg, &value); |
| 3829 | value &= (~REG_CPCG_COL_CLK_EN_MASK); |
| 3830 | reg_write(reg, value); |
| 3831 | |
| 3832 | reg_read(reg, &value); |
| 3833 | printf("write reg: %x, value: %x\n", reg, value); |
| 3834 | |
| 3835 | } |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3836 | } else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3837 | printf("\nCommand not support by this chip.\n"); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3838 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3839 | } |
| 3840 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3841 | void collision_pool_mac_dump(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3842 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3843 | unsigned int value = 0, reg = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3844 | |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 3845 | if (chip_name == 0x7531 || chip_name == 0x7988) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3846 | reg = REG_CPGC_ADDR; |
| 3847 | reg_read(reg, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3848 | if (value & REG_CPCG_COL_EN_MASK) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3849 | table_dump_internal(COLLISION_TABLE); |
| 3850 | else |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3851 | printf |
| 3852 | ("\ncollision pool is disabled, please enable it before use this command.\n"); |
| 3853 | } else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3854 | printf("\nCommand not support by this chip.\n"); |
| 3855 | } |
| 3856 | } |
| 3857 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3858 | void collision_pool_dip_dump(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3859 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3860 | unsigned int value = 0, reg = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3861 | |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 3862 | if (chip_name == 0x7531 || chip_name == 0x7988) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3863 | reg = REG_CPGC_ADDR; |
| 3864 | reg_read(reg, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3865 | if (value & REG_CPCG_COL_EN_MASK) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3866 | dip_dump_internal(COLLISION_TABLE); |
| 3867 | else |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3868 | printf |
| 3869 | ("\ncollision pool is disabled, please enable it before use this command.\n"); |
| 3870 | } else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3871 | printf("\nCommand not support by this chip.\n"); |
| 3872 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3873 | } |
| 3874 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3875 | void collision_pool_sip_dump(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3876 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3877 | unsigned int value = 0, reg = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3878 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3879 | if (chip_name == 0x7531 || chip_name == 0x7988) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3880 | reg = REG_CPGC_ADDR; |
| 3881 | reg_read(reg, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3882 | if (value & REG_CPCG_COL_EN_MASK) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3883 | sip_dump_internal(COLLISION_TABLE); |
| 3884 | else |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3885 | printf |
| 3886 | ("\ncollision pool is disabled, please enable it before use this command.\n"); |
| 3887 | } else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3888 | printf("\nCommand not support by this chip.\n"); |
| 3889 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3890 | } |
| 3891 | |
| 3892 | void pfc_get_rx_counter(int argc, char *argv[]) |
| 3893 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3894 | int port = 0; |
| 3895 | unsigned int value = 0, reg = 0; |
| 3896 | unsigned int user_pri = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3897 | |
| 3898 | port = strtoul(argv[3], NULL, 0); |
| 3899 | if (port < 0 || 6 < port) { |
| 3900 | printf("wrong port range, should be within 0~6\n"); |
| 3901 | return; |
| 3902 | } |
| 3903 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3904 | if (chip_name == 0x7531 || chip_name == 0x7988) { |
| 3905 | reg = PFC_RX_COUNTER_L(port); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3906 | reg_read(reg, &value); |
| 3907 | user_pri = value & 0xff; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3908 | printf("\n port %d rx pfc (up=0)pause on counter is %d.\n", |
| 3909 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3910 | user_pri = (value & 0xff00) >> 8; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3911 | printf("\n port %d rx pfc (up=1)pause on counter is %d.\n", |
| 3912 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3913 | user_pri = (value & 0xff0000) >> 16; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3914 | printf("\n port %d rx pfc (up=2)pause on counter is %d.\n", |
| 3915 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3916 | user_pri = (value & 0xff000000) >> 24; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3917 | printf("\n port %d rx pfc (up=3)pause on counter is %d.\n", |
| 3918 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3919 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3920 | reg = PFC_RX_COUNTER_H(port); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3921 | reg_read(reg, &value); |
| 3922 | user_pri = value & 0xff; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3923 | printf("\n port %d rx pfc (up=4)pause on counter is %d.\n", |
| 3924 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3925 | user_pri = (value & 0xff00) >> 8; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3926 | printf("\n port %d rx pfc (up=5)pause on counter is %d.\n", |
| 3927 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3928 | user_pri = (value & 0xff0000) >> 16; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3929 | printf("\n port %d rx pfc (up=6)pause on counter is %d.\n", |
| 3930 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3931 | user_pri = (value & 0xff000000) >> 24; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3932 | printf("\n port %d rx pfc (up=7)pause on counter is %d.\n", |
| 3933 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3934 | |
| 3935 | /* for rx counter could be updated successfully */ |
| 3936 | reg_read(PMSR_P(port), &value); |
| 3937 | reg_read(PMSR_P(port), &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3938 | } else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3939 | printf("\nCommand not support by this chip.\n"); |
| 3940 | } |
| 3941 | |
| 3942 | } |
| 3943 | |
| 3944 | void pfc_get_tx_counter(int argc, char *argv[]) |
| 3945 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3946 | int port = 0; |
| 3947 | unsigned int value = 0, reg = 0; |
| 3948 | unsigned int user_pri = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3949 | |
| 3950 | port = strtoul(argv[3], NULL, 0); |
| 3951 | if (port < 0 || 6 < port) { |
| 3952 | printf("wrong port range, should be within 0~6\n"); |
| 3953 | return; |
| 3954 | } |
| 3955 | |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 3956 | if (chip_name == 0x7531 || chip_name == 0x7988) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3957 | reg = PFC_TX_COUNTER_L(port); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3958 | reg_read(reg, &value); |
| 3959 | user_pri = value & 0xff; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3960 | printf("\n port %d tx pfc (up=0)pause on counter is %d.\n", |
| 3961 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3962 | user_pri = (value & 0xff00) >> 8; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3963 | printf("\n port %d tx pfc (up=1)pause on counter is %d.\n", |
| 3964 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3965 | user_pri = (value & 0xff0000) >> 16; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3966 | printf("\n port %d tx pfc (up=2)pause on counter is %d.\n", |
| 3967 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3968 | user_pri = (value & 0xff000000) >> 24; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3969 | printf("\n port %d tx pfc (up=3)pause on counter is %d.\n", |
| 3970 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3971 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3972 | reg = PFC_TX_COUNTER_H(port); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3973 | reg_read(reg, &value); |
| 3974 | user_pri = value & 0xff; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3975 | printf("\n port %d tx pfc (up=4)pause on counter is %d.\n", |
| 3976 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3977 | user_pri = (value & 0xff00) >> 8; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3978 | printf("\n port %d tx pfc (up=5)pause on counter is %d.\n", |
| 3979 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3980 | user_pri = (value & 0xff0000) >> 16; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3981 | printf("\n port %d tx pfc (up=6)pause on counter is %d.\n", |
| 3982 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3983 | user_pri = (value & 0xff000000) >> 24; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3984 | printf("\n port %d tx pfc (up=7)pause on counter is %d.\n", |
| 3985 | port, user_pri); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3986 | |
| 3987 | /* for tx counter could be updated successfully */ |
| 3988 | reg_read(PMSR_P(port), &value); |
| 3989 | reg_read(PMSR_P(port), &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3990 | } else { |
| 3991 | printf("\nCommand not support by this chip.\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3992 | } |
| 3993 | } |
| 3994 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3995 | void read_output_queue_counters(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3996 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 3997 | unsigned int port = 0; |
| 3998 | unsigned int value = 0, output_queue = 0; |
| 3999 | unsigned int base = 0x220; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4000 | |
| 4001 | for (port = 0; port < 7; port++) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4002 | reg_write(0x7038, base + (port * 4)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4003 | reg_read(0x7034, &value); |
| 4004 | output_queue = value & 0xff; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4005 | printf("\n port %d output queue 0 counter is %d.\n", port, |
| 4006 | output_queue); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4007 | output_queue = (value & 0xff00) >> 8; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4008 | printf("\n port %d output queue 1 counter is %d.\n", port, |
| 4009 | output_queue); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4010 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4011 | reg_write(0x7038, base + (port * 4) + 1); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4012 | reg_read(0x7034, &value); |
| 4013 | output_queue = value & 0xff; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4014 | printf("\n port %d output queue 2 counter is %d.\n", port, |
| 4015 | output_queue); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4016 | output_queue = (value & 0xff00) >> 8; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4017 | printf("\n port %d output queue 3 counter is %d.\n", port, |
| 4018 | output_queue); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4019 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4020 | reg_write(0x7038, base + (port * 4) + 2); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4021 | reg_read(0x7034, &value); |
| 4022 | output_queue = value & 0xff; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4023 | printf("\n port %d output queue 4 counter is %d.\n", port, |
| 4024 | output_queue); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4025 | output_queue = (value & 0xff00) >> 8; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4026 | printf("\n port %d output queue 5 counter is %d.\n", port, |
| 4027 | output_queue); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4028 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4029 | reg_write(0x7038, base + (port * 4) + 3); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4030 | reg_read(0x7034, &value); |
| 4031 | output_queue = value & 0xff; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4032 | printf("\n port %d output queue 6 counter is %d.\n", port, |
| 4033 | output_queue); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4034 | output_queue = (value & 0xff00) >> 8; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4035 | printf("\n port %d output queue 7 counter is %d.\n", port, |
| 4036 | output_queue); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4037 | } |
| 4038 | } |
| 4039 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4040 | void read_free_page_counters(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4041 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4042 | unsigned int value = 0; |
| 4043 | unsigned int free_page = 0, free_page_last_read = 0; |
| 4044 | unsigned int fc_free_blk_lothd = 0, fc_free_blk_hithd = 0; |
| 4045 | unsigned int fc_port_blk_thd = 0, fc_port_blk_hi_thd = 0; |
| 4046 | unsigned int queue[8] = { 0 }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4047 | |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 4048 | if (chip_name == 0x7531 || chip_name == 0x7988) { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4049 | /* get system free page link counter */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4050 | reg_read(0x1fc0, &value); |
| 4051 | free_page = value & 0xFFF; |
| 4052 | free_page_last_read = (value & 0xFFF0000) >> 16; |
| 4053 | |
| 4054 | /* get system flow control waterwark */ |
| 4055 | reg_read(0x1fe0, &value); |
| 4056 | fc_free_blk_lothd = value & 0x3FF; |
| 4057 | fc_free_blk_hithd = (value & 0x3FF0000) >> 16; |
| 4058 | |
| 4059 | /* get port flow control waterwark */ |
| 4060 | reg_read(0x1fe4, &value); |
| 4061 | fc_port_blk_thd = value & 0x3FF; |
| 4062 | fc_port_blk_hi_thd = (value & 0x3FF0000) >> 16; |
| 4063 | |
| 4064 | /* get queue flow control waterwark */ |
| 4065 | reg_read(0x1fe8, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4066 | queue[0] = value & 0x3F; |
| 4067 | queue[1] = (value & 0x3F00) >> 8; |
| 4068 | queue[2] = (value & 0x3F0000) >> 16; |
| 4069 | queue[3] = (value & 0x3F000000) >> 24; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4070 | reg_read(0x1fec, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4071 | queue[4] = value & 0x3F; |
| 4072 | queue[5] = (value & 0x3F00) >> 8; |
| 4073 | queue[6] = (value & 0x3F0000) >> 16; |
| 4074 | queue[7] = (value & 0x3F000000) >> 24; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4075 | } else { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4076 | /* get system free page link counter */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4077 | reg_read(0x1fc0, &value); |
| 4078 | free_page = value & 0x3FF; |
| 4079 | free_page_last_read = (value & 0x3FF0000) >> 16; |
| 4080 | |
| 4081 | /* get system flow control waterwark */ |
| 4082 | reg_read(0x1fe0, &value); |
| 4083 | fc_free_blk_lothd = value & 0xFF; |
| 4084 | fc_free_blk_hithd = (value & 0xFF00) >> 8; |
| 4085 | |
| 4086 | /* get port flow control waterwark */ |
| 4087 | reg_read(0x1fe0, &value); |
| 4088 | fc_port_blk_thd = (value & 0xFF0000) >> 16; |
| 4089 | reg_read(0x1ff4, &value); |
| 4090 | fc_port_blk_hi_thd = (value & 0xFF00) >> 8; |
| 4091 | |
| 4092 | /* get queue flow control waterwark */ |
| 4093 | reg_read(0x1fe4, &value); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4094 | queue[0] = value & 0xF; |
| 4095 | queue[1] = (value & 0xF0) >> 4; |
| 4096 | queue[2] = (value & 0xF00) >> 8; |
| 4097 | queue[3] = (value & 0xF000) >> 12; |
| 4098 | queue[4] = (value & 0xF0000) >> 16; |
| 4099 | queue[5] = (value & 0xF00000) >> 20; |
| 4100 | queue[6] = (value & 0xF000000) >> 24; |
| 4101 | queue[7] = (value & 0xF0000000) >> 28; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4102 | } |
| 4103 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4104 | printf("<===Free Page=======Current=======Last Read access=====>\n"); |
| 4105 | printf("\n"); |
| 4106 | printf(" page counter %u %u\n ", |
| 4107 | free_page, free_page_last_read); |
| 4108 | printf("\n "); |
| 4109 | printf("=========================================================\n"); |
| 4110 | printf("<===Type=======High threshold======Low threshold=========\n"); |
| 4111 | printf("\n "); |
| 4112 | printf(" system: %u %u\n", |
| 4113 | fc_free_blk_hithd * 2, fc_free_blk_lothd * 2); |
| 4114 | printf(" port: %u %u\n", |
| 4115 | fc_port_blk_hi_thd * 2, fc_port_blk_thd * 2); |
| 4116 | printf(" queue 0: %u NA\n", |
| 4117 | queue[0]); |
| 4118 | printf(" queue 1: %u NA\n", |
| 4119 | queue[1]); |
| 4120 | printf(" queue 2: %u NA\n", |
| 4121 | queue[2]); |
| 4122 | printf(" queue 3: %u NA\n", |
| 4123 | queue[3]); |
| 4124 | printf(" queue 4: %u NA\n", |
| 4125 | queue[4]); |
| 4126 | printf(" queue 5: %u NA\n", |
| 4127 | queue[5]); |
| 4128 | printf(" queue 6: %u NA\n", |
| 4129 | queue[6]); |
| 4130 | printf(" queue 7: %u NA\n", |
| 4131 | queue[7]); |
| 4132 | printf("=========================================================\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4133 | } |
| 4134 | |
| 4135 | void eee_enable(int argc, char *argv[]) |
| 4136 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4137 | unsigned long enable = 0; |
| 4138 | unsigned int value = 0; |
| 4139 | unsigned int eee_cap = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4140 | unsigned int eee_en_bitmap = 0; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4141 | unsigned long port_map = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4142 | long port_num = -1; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4143 | int p = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4144 | |
| 4145 | if (argc < 3) |
| 4146 | goto error; |
| 4147 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4148 | /* Check the input parameters is right or not. */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4149 | if (!strncmp(argv[2], "enable", 7)) |
| 4150 | enable = 1; |
| 4151 | else if (!strncmp(argv[2], "disable", 8)) |
| 4152 | enable = 0; |
| 4153 | else |
| 4154 | goto error; |
| 4155 | |
| 4156 | if (argc > 3) { |
| 4157 | if (strlen(argv[3]) == 1) { |
| 4158 | port_num = strtol(argv[3], (char **)NULL, 10); |
| 4159 | if (port_num < 0 || port_num > MAX_PHY_PORT - 1) { |
| 4160 | printf("Illegal port index and port:0~4\n"); |
| 4161 | goto error; |
| 4162 | } |
| 4163 | port_map = 1 << port_num; |
| 4164 | } else if (strlen(argv[3]) == 5) { |
| 4165 | port_map = 0; |
| 4166 | for (p = 0; p < MAX_PHY_PORT; p++) { |
| 4167 | if (argv[3][p] != '0' && argv[3][p] != '1') { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4168 | printf |
| 4169 | ("portmap format error, should be combination of 0 or 1\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4170 | goto error; |
| 4171 | } |
| 4172 | port_map |= ((argv[3][p] - '0') << p); |
| 4173 | } |
| 4174 | } else { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4175 | printf |
| 4176 | ("port_no or portmap format error, should be length of 1 or 5\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4177 | goto error; |
| 4178 | } |
| 4179 | } else { |
| 4180 | port_map = 0x1f; |
| 4181 | } |
| 4182 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4183 | eee_cap = (enable) ? 6 : 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4184 | for (p = 0; p < MAX_PHY_PORT; p++) { |
| 4185 | /* port_map describe p0p1p2p3p4 from left to rignt */ |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4186 | if (!!(port_map & (1 << p))) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4187 | mii_mgr_c45_write(p, 0x7, 0x3c, eee_cap); |
| 4188 | |
| 4189 | mii_mgr_c45_read(p, 0x7, 0x3c, &value); |
| 4190 | /* mt7531: Always readback eee_cap = 0 when global EEE switch |
| 4191 | * is turned off. |
| 4192 | */ |
| 4193 | if (value | eee_cap) |
| 4194 | eee_en_bitmap |= (1 << (MAX_PHY_PORT - 1 - p)); |
| 4195 | } |
| 4196 | |
| 4197 | /* Turn on/off global EEE switch */ |
developer | 8c3871b | 2022-07-01 14:07:53 +0800 | [diff] [blame] | 4198 | if (chip_name == 0x7531 || chip_name == 0x7988) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4199 | mii_mgr_c45_read(0, 0x1f, 0x403, &value); |
| 4200 | if (eee_en_bitmap) |
| 4201 | value |= (1 << 6); |
| 4202 | else |
| 4203 | value &= ~(1 << 6); |
| 4204 | mii_mgr_c45_write(0, 0x1f, 0x403, value); |
| 4205 | } else { |
| 4206 | printf("\nCommand not support by this chip.\n"); |
| 4207 | } |
| 4208 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4209 | printf("EEE(802.3az) %s", (enable) ? "enable" : "disable"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4210 | if (argc == 4) { |
| 4211 | if (port_num >= 0) |
| 4212 | printf(" port%ld", port_num); |
| 4213 | else |
| 4214 | printf(" port_map: %s", argv[3]); |
| 4215 | } else { |
| 4216 | printf(" all ports"); |
| 4217 | } |
| 4218 | printf("\n"); |
| 4219 | |
| 4220 | return; |
| 4221 | error: |
| 4222 | printf(HELP_EEE_EN); |
| 4223 | return; |
| 4224 | } |
| 4225 | |
| 4226 | void eee_dump(int argc, char *argv[]) |
| 4227 | { |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4228 | unsigned int cap = 0, lp_cap = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4229 | long port = -1; |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4230 | int p = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4231 | |
| 4232 | if (argc > 3) { |
| 4233 | if (strlen(argv[3]) > 1) { |
| 4234 | printf("port# format error, should be of length 1\n"); |
| 4235 | return; |
| 4236 | } |
| 4237 | |
| 4238 | port = strtol(argv[3], (char **)NULL, 0); |
| 4239 | if (port < 0 || port > MAX_PHY_PORT) { |
| 4240 | printf("port# format error, should be 0 to %d\n", |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4241 | MAX_PHY_PORT); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4242 | return; |
| 4243 | } |
| 4244 | } |
| 4245 | |
| 4246 | for (p = 0; p < MAX_PHY_PORT; p++) { |
| 4247 | if (port >= 0 && p != port) |
| 4248 | continue; |
| 4249 | |
| 4250 | mii_mgr_c45_read(p, 0x7, 0x3c, &cap); |
| 4251 | mii_mgr_c45_read(p, 0x7, 0x3d, &lp_cap); |
| 4252 | printf("port%d EEE cap=0x%02x, link partner EEE cap=0x%02x", |
| 4253 | p, cap, lp_cap); |
| 4254 | |
| 4255 | if (port >= 0 && p == port) { |
| 4256 | mii_mgr_c45_read(p, 0x3, 0x1, &cap); |
| 4257 | printf(", st=0x%03x", cap); |
| 4258 | } |
| 4259 | printf("\n"); |
| 4260 | } |
| 4261 | } |
| 4262 | |
| 4263 | void dump_each_port(unsigned int base) |
| 4264 | { |
| 4265 | unsigned int pkt_cnt = 0; |
| 4266 | int i = 0; |
| 4267 | |
| 4268 | for (i = 0; i < 7; i++) { |
developer | 0dea340 | 2022-10-14 13:41:11 +0800 | [diff] [blame] | 4269 | if (chip_name == 0x7988) { |
| 4270 | if ((base == 0x402C) && (i == 6)) |
| 4271 | base = 0x408C; |
| 4272 | else if ((base == 0x408C) && (i == 6)) |
| 4273 | base = 0x402C; |
| 4274 | else |
| 4275 | ; |
| 4276 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4277 | reg_read((base) + (i * 0x100), &pkt_cnt); |
| 4278 | printf("%8u ", pkt_cnt); |
| 4279 | } |
| 4280 | printf("\n"); |
| 4281 | } |
| 4282 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4283 | void read_mib_counters(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4284 | { |
| 4285 | printf("===================== %8s %8s %8s %8s %8s %8s %8s\n", |
| 4286 | "Port0", "Port1", "Port2", "Port3", "Port4", "Port5", "Port6"); |
| 4287 | printf("Tx Drop Packet :"); |
| 4288 | dump_each_port(0x4000); |
| 4289 | printf("Tx CRC Error :"); |
| 4290 | dump_each_port(0x4004); |
| 4291 | printf("Tx Unicast Packet :"); |
| 4292 | dump_each_port(0x4008); |
| 4293 | printf("Tx Multicast Packet :"); |
| 4294 | dump_each_port(0x400C); |
| 4295 | printf("Tx Broadcast Packet :"); |
| 4296 | dump_each_port(0x4010); |
| 4297 | printf("Tx Collision Event :"); |
| 4298 | dump_each_port(0x4014); |
| 4299 | printf("Tx Pause Packet :"); |
| 4300 | dump_each_port(0x402C); |
| 4301 | printf("Rx Drop Packet :"); |
| 4302 | dump_each_port(0x4060); |
| 4303 | printf("Rx Filtering Packet :"); |
| 4304 | dump_each_port(0x4064); |
| 4305 | printf("Rx Unicast Packet :"); |
| 4306 | dump_each_port(0x4068); |
| 4307 | printf("Rx Multicast Packet :"); |
| 4308 | dump_each_port(0x406C); |
| 4309 | printf("Rx Broadcast Packet :"); |
| 4310 | dump_each_port(0x4070); |
| 4311 | printf("Rx Alignment Error :"); |
| 4312 | dump_each_port(0x4074); |
| 4313 | printf("Rx CRC Error :"); |
| 4314 | dump_each_port(0x4078); |
| 4315 | printf("Rx Undersize Error :"); |
| 4316 | dump_each_port(0x407C); |
| 4317 | printf("Rx Fragment Error :"); |
| 4318 | dump_each_port(0x4080); |
| 4319 | printf("Rx Oversize Error :"); |
| 4320 | dump_each_port(0x4084); |
| 4321 | printf("Rx Jabber Error :"); |
| 4322 | dump_each_port(0x4088); |
| 4323 | printf("Rx Pause Packet :"); |
| 4324 | dump_each_port(0x408C); |
| 4325 | } |
| 4326 | |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4327 | void clear_mib_counters(int argc, char *argv[]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4328 | { |
| 4329 | reg_write(0x4fe0, 0xf0); |
developer | be40a9e | 2024-03-07 21:44:26 +0800 | [diff] [blame] | 4330 | read_mib_counters(argc, argv); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4331 | reg_write(0x4fe0, 0x800000f0); |
| 4332 | } |
| 4333 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4334 | void exit_free() |
| 4335 | { |
| 4336 | free(attres); |
| 4337 | attres = NULL; |
| 4338 | switch_ioctl_fini(); |
| 4339 | mt753x_netlink_free(); |
| 4340 | } |