developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 1 | From 966aa1887615c19ceb9d7675cd46c9c550847128 Mon Sep 17 00:00:00 2001 |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 2 | From: Lian Chen <lian.chen@mediatek.com> |
| 3 | Date: Mon, 7 Nov 2022 14:47:44 +0800 |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 4 | Subject: [PATCH 3011/3011] mt76: HW ATF support for mt7986 |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 5 | |
| 6 | Signed-off-by: Lian Chen <lian.chen@mediatek.com> |
| 7 | --- |
| 8 | mt76_connac_mcu.h | 2 + |
| 9 | mt7915/debugfs.c | 405 +++++++++++++++++++++++++++++++++++++++++++ |
| 10 | mt7915/init.c | 39 +++++ |
| 11 | mt7915/main.c | 16 ++ |
| 12 | mt7915/mcu.c | 165 ++++++++++++++++++ |
| 13 | mt7915/mt7915.h | 68 ++++++++ |
| 14 | mt7915/mtk_debugfs.c | 133 +++++++++++++- |
| 15 | 7 files changed, 827 insertions(+), 1 deletion(-) |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 16 | mode change 100644 => 100755 mt7915/init.c |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 17 | |
| 18 | diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 19 | index a368b65b..2cb498f3 100644 |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 20 | --- a/mt76_connac_mcu.h |
| 21 | +++ b/mt76_connac_mcu.h |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 22 | @@ -1122,6 +1122,7 @@ enum { |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 23 | MCU_EXT_CMD_THERMAL_CTRL = 0x2c, |
| 24 | MCU_EXT_CMD_WTBL_UPDATE = 0x32, |
| 25 | MCU_EXT_CMD_SET_DRR_CTRL = 0x36, |
| 26 | + MCU_EXT_CMD_SET_FEATURE_CTRL = 0x38, |
| 27 | MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, |
| 28 | MCU_EXT_CMD_ATE_CTRL = 0x3d, |
| 29 | MCU_EXT_CMD_PROTECT_CTRL = 0x3e, |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 30 | @@ -1131,6 +1132,7 @@ enum { |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 31 | MCU_EXT_CMD_MUAR_UPDATE = 0x48, |
| 32 | MCU_EXT_CMD_BCN_OFFLOAD = 0x49, |
| 33 | MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, |
| 34 | + MCU_EXT_CMD_AT_PROC_MODULE = 0x4b, |
| 35 | MCU_EXT_CMD_SET_RX_PATH = 0x4e, |
| 36 | MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f, |
| 37 | MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, |
| 38 | diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 39 | index 21407030..85468cd2 100644 |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 40 | --- a/mt7915/debugfs.c |
| 41 | +++ b/mt7915/debugfs.c |
| 42 | @@ -12,6 +12,10 @@ |
| 43 | #define FW_BIN_LOG_MAGIC_V2 0x44d9c99a |
| 44 | #endif |
| 45 | |
| 46 | +#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] |
| 47 | +#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" |
| 48 | + |
| 49 | + |
| 50 | /** global debugfs **/ |
| 51 | |
| 52 | struct hw_queue_map { |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 53 | @@ -211,6 +215,406 @@ static const struct file_operations mt7915_sys_recovery_ops = { |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 54 | .llseek = default_llseek, |
| 55 | }; |
| 56 | |
| 57 | +static ssize_t mt7915_vow_get(struct file *file, char __user *user_buf, |
| 58 | + size_t count, loff_t *ppos) |
| 59 | +{ |
| 60 | + char *buff; |
| 61 | + int desc = 0; |
| 62 | + ssize_t ret; |
| 63 | + static const size_t bufsz = 1000; |
| 64 | + |
| 65 | + buff = kmalloc(bufsz, GFP_KERNEL); |
| 66 | + if (!buff) |
| 67 | + return -ENOMEM; |
| 68 | + |
| 69 | + desc += scnprintf(buff + desc, bufsz - desc, |
| 70 | + "======== Control =============\n" |
| 71 | + "vow_atf_en=<0/1> 0:disable, 1:enable\n" |
| 72 | + "vow_watf_en=<0/1> 0:disable, 1:enable\n" |
| 73 | + "vow_watf_quantum=<level>-<quantum> unit 256us\n" |
| 74 | + "======== Station table =============\n" |
| 75 | + "vow_sta_dwrr_quantum_id=<wlanidx>-<WMM AC>-<Qid>\n" |
| 76 | + "vow_dwrr_max_wait_time=<time> 256us\n" |
| 77 | + "======== Debug =============\n" |
| 78 | + "vow_show_en=<0/1> 0:dieable, 1:enable\n" |
| 79 | + "vow_show_sta=<STA num>\n" |
| 80 | + "show_vow_info\n" |
| 81 | + "show_vow_sta_conf=<STA num> 0:all\n"); |
| 82 | + ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc); |
| 83 | + kfree(buff); |
| 84 | + return ret; |
| 85 | +} |
| 86 | + |
| 87 | +static int mt7915_set_vow_sta_dwrr_quantum_id(struct mt7915_dev *dev, |
| 88 | + u32 wcid_id, |
| 89 | + u32 ac, u32 val) |
| 90 | +{ |
| 91 | + struct mt7915_sta *msta; |
| 92 | + struct mt76_wcid *wcid; |
| 93 | + int ret; |
| 94 | + |
| 95 | + wcid = rcu_dereference(dev->mt76.wcid[wcid_id]); |
| 96 | + if ((!wcid) || (!wcid->sta)) { |
| 97 | + dev_err(dev->mt76.dev, "%s: error station.\n", __func__); |
| 98 | + return 0; |
| 99 | + } |
| 100 | + |
| 101 | + msta = container_of(wcid, struct mt7915_sta, wcid); |
| 102 | + |
| 103 | + msta->vow_sta_cfg.dwrr_quantum[ac] = val; |
| 104 | + |
| 105 | + ret = mt7915_mcu_set_vow_drr_ctrl(dev, msta, VOW_DRR_STA_AC0_QUA_ID + ac); |
| 106 | + dev_info(dev->mt76.dev, "%s: set sta %d, ac %d, quantum id %u.\n", |
| 107 | + __func__, wcid_id, ac, val); |
| 108 | + |
| 109 | + return ret; |
| 110 | +} |
| 111 | + |
| 112 | +static int mt7915_set_vow_atf_en(struct mt7915_dev *dev, u32 val) |
| 113 | +{ |
| 114 | + int ret; |
| 115 | + |
| 116 | + dev->vow_cfg.vow_atf_en = !!val; |
| 117 | + dev->vow_cfg.sta_max_wait_time = val ? 0x40 : 0x1; |
| 118 | + ret = mt7915_mcu_set_vow_feature_ctrl(dev); |
| 119 | + dev_info(dev->mt76.dev, "%s: set vow_atf_en %u.\n", |
| 120 | + __func__, val); |
| 121 | + |
| 122 | + ret = mt7915_mcu_set_vow_drr_ctrl(dev, NULL, |
| 123 | + VOW_DRR_AIRTIME_DEFICIT_BOUND); |
| 124 | + dev_info(dev->mt76.dev, "%s: set vow_dwrr_max_wait_time %u.\n", |
| 125 | + __func__, dev->vow_cfg.sta_max_wait_time); |
| 126 | + |
| 127 | + return ret; |
| 128 | +} |
| 129 | + |
| 130 | +static int mt7915_set_vow_dwrr_max_wait_time(struct mt7915_dev *dev, |
| 131 | + u32 val) |
| 132 | +{ |
| 133 | + int ret; |
| 134 | + |
| 135 | + dev->vow_cfg.sta_max_wait_time = val; |
| 136 | + ret = mt7915_mcu_set_vow_drr_ctrl(dev, NULL, |
| 137 | + VOW_DRR_AIRTIME_DEFICIT_BOUND); |
| 138 | + dev_info(dev->mt76.dev, "%s: set vow_dwrr_max_wait_time %u.\n", |
| 139 | + __func__, val); |
| 140 | + |
| 141 | + return ret; |
| 142 | +} |
| 143 | + |
| 144 | +static int mt7915_set_vow_watf_en(struct mt7915_dev *dev, u32 val) |
| 145 | +{ |
| 146 | + int ret; |
| 147 | + |
| 148 | + dev->vow_cfg.vow_watf_en = !!val; |
| 149 | + ret = mt7915_mcu_set_vow_feature_ctrl(dev); |
| 150 | + dev_info(dev->mt76.dev, "%s: set vow_watf_en %u.\n", __func__, val); |
| 151 | + |
| 152 | + return ret; |
| 153 | +} |
| 154 | + |
| 155 | +static int mt7915_set_vow_watf_quantum(struct mt7915_dev *dev, |
| 156 | + u32 id, u32 val) |
| 157 | +{ |
| 158 | + int ret; |
| 159 | + |
| 160 | + dev->vow_cfg.vow_sta_dwrr_quantum[id] = val; |
| 161 | + ret = mt7915_mcu_set_vow_drr_ctrl(dev, NULL, |
| 162 | + VOW_DRR_AIRTIME_QUANTUM_L0 + id); |
| 163 | + dev_info(dev->mt76.dev, "%s: set quantum id %u, val %d.\n", |
| 164 | + __func__, id, val); |
| 165 | + |
| 166 | + return ret; |
| 167 | +} |
| 168 | + |
| 169 | +extern int mt7915_vow_pleinfo_read(struct mt7915_dev *dev); |
| 170 | +static void mt7915_show_station_tx_airtime(struct work_struct *work){ |
| 171 | + struct mt7915_dev *dev = container_of(work, struct mt7915_dev, |
| 172 | + vow_work.work); |
| 173 | + static u32 vow_last_tx_time[MT7916_WTBL_SIZE]; |
| 174 | + struct ieee80211_sta *ieee80211_sta; |
| 175 | + struct mt7915_sta *msta; |
| 176 | + struct mt76_wcid *wcid; |
| 177 | + int idx = 0; |
| 178 | + int i = 0; |
| 179 | + u32 addr; |
| 180 | + int tx_airtime_sum = 0; |
| 181 | + int tx_add_airtime = 0; |
| 182 | + |
| 183 | + if (!dev->vow_cfg.vow_show_en) |
| 184 | + return; |
| 185 | + |
| 186 | + rcu_read_lock(); |
| 187 | + for (idx = 1; (idx < dev->vow_cfg.vow_show_sta) && |
| 188 | + (idx < MT7915_WTBL_STA); idx++) { |
| 189 | + if (idx >= ARRAY_SIZE(dev->mt76.wcid)) |
| 190 | + return; |
| 191 | + |
| 192 | + wcid = rcu_dereference(dev->mt76.wcid[idx]); |
| 193 | + if (!wcid || !wcid->sta) |
| 194 | + continue; |
| 195 | + |
| 196 | + msta = container_of(wcid, struct mt7915_sta, wcid); |
| 197 | + addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20); |
| 198 | + tx_airtime_sum = 0; |
| 199 | + |
| 200 | + for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
| 201 | + tx_airtime_sum += mt76_rr(dev, addr); |
| 202 | + addr += 8; |
| 203 | + } |
| 204 | + tx_add_airtime = tx_airtime_sum - vow_last_tx_time[idx]; |
| 205 | + vow_last_tx_time[idx] = tx_airtime_sum; |
| 206 | + |
| 207 | + ieee80211_sta = container_of((void *)msta, struct ieee80211_sta, |
| 208 | + drv_priv); |
| 209 | + |
| 210 | + dev_info(dev->mt76.dev, "sta%u:" MACSTR " tx -> %u)\n", |
| 211 | + idx, MAC2STR(ieee80211_sta->addr), tx_add_airtime); |
| 212 | + } |
| 213 | + mt7915_vow_pleinfo_read(dev); |
| 214 | + ieee80211_queue_delayed_work(mt76_hw(dev), &dev->vow_work, 1 * HZ); |
| 215 | + rcu_read_unlock(); |
| 216 | + return; |
| 217 | +} |
| 218 | + |
| 219 | + |
| 220 | +static int mt7915_set_vow_show_en(struct mt7915_dev *dev, u32 val) |
| 221 | +{ |
| 222 | + if (!!dev->vow_cfg.vow_show_en == !!val) |
| 223 | + return 0; |
| 224 | + dev->vow_cfg.vow_show_en = val; |
| 225 | + mt7915_mcu_set_vow_feature_ctrl(dev); |
| 226 | + if (dev->vow_cfg.vow_show_en) { |
| 227 | + INIT_DELAYED_WORK(&dev->vow_work, mt7915_show_station_tx_airtime); |
| 228 | + ieee80211_queue_delayed_work(mt76_hw(dev), &dev->vow_work, 1 * HZ); |
| 229 | + } |
| 230 | + else { |
| 231 | + cancel_delayed_work_sync(&dev->vow_work); |
| 232 | + } |
| 233 | + return 0; |
| 234 | +} |
| 235 | + |
| 236 | +static int mt7915_set_vow_show_sta(struct mt7915_dev *dev, u32 val) |
| 237 | +{ |
| 238 | + dev->vow_cfg.vow_show_sta = val; |
| 239 | + dev_info(dev->mt76.dev, "%s: show station up to %d.\n", |
| 240 | + __func__, dev->vow_cfg.vow_show_sta); |
| 241 | + return 0; |
| 242 | +} |
| 243 | +static int mt7915_set_show_vow_info(struct mt7915_dev *dev) |
| 244 | +{ |
| 245 | + dev_info(dev->mt76.dev, "====== VOW Control Information ======\n"); |
| 246 | + dev_info(dev->mt76.dev, "ATF Enbale: %d\n", |
| 247 | + dev->vow_cfg.vow_atf_en); |
| 248 | + dev_info(dev->mt76.dev, "WATF Enable: %d\n", |
| 249 | + dev->vow_cfg.vow_watf_en); |
| 250 | + dev_info(dev->mt76.dev, "refill_period: %d\n", |
| 251 | + dev->vow_cfg.refill_period); |
| 252 | + dev_info(dev->mt76.dev, "===== VOW Max Deficit Information =====\n"); |
| 253 | + dev_info(dev->mt76.dev, "VOW Max Deficit(unit 256us): %d\n", |
| 254 | + dev->vow_cfg.sta_max_wait_time); |
| 255 | + dev_info(dev->mt76.dev, "===== VOW Quantum Information =====\n"); |
| 256 | + dev_info(dev->mt76.dev, "Quantum ID 0 value(unit 256us): %d\n", |
| 257 | + dev->vow_cfg.vow_sta_dwrr_quantum[0]); |
| 258 | + dev_info(dev->mt76.dev, "Quantum ID 1 value(unit 256us): %d\n", |
| 259 | + dev->vow_cfg.vow_sta_dwrr_quantum[1]); |
| 260 | + dev_info(dev->mt76.dev, "Quantum ID 2 value(unit 256us): %d\n", |
| 261 | + dev->vow_cfg.vow_sta_dwrr_quantum[2]); |
| 262 | + dev_info(dev->mt76.dev, "Quantum ID 3 value(unit 256us): %d\n", |
| 263 | + dev->vow_cfg.vow_sta_dwrr_quantum[3]); |
| 264 | + return 0; |
| 265 | +} |
| 266 | + |
| 267 | +static int mt7915_show_vow_sta_conf(struct mt7915_dev *dev, u32 val) |
| 268 | +{ |
| 269 | + struct ieee80211_sta *ieee80211_sta; |
| 270 | + struct mt7915_sta *msta; |
| 271 | + struct mt76_wcid *wcid; |
| 272 | + u32 i; |
| 273 | + u8 q; |
| 274 | + |
| 275 | + if (val > 0 && val < MT7915_WTBL_STA) { |
| 276 | + wcid = rcu_dereference(dev->mt76.wcid[val]); |
| 277 | + if (!wcid || !wcid->sta) |
| 278 | + return 0; |
| 279 | + msta = container_of(wcid, struct mt7915_sta, wcid); |
| 280 | + ieee80211_sta = container_of((void *)msta, struct ieee80211_sta, |
| 281 | + drv_priv); |
| 282 | + dev_info(dev->mt76.dev, "%s: ****** sta%d: "MACSTR"******\n", |
| 283 | + __func__, val, MAC2STR(ieee80211_sta->addr)); |
| 284 | + q = msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_VO]; |
| 285 | + dev_info(dev->mt76.dev, "Ac0 --> %uus(%u)\n", |
| 286 | + (dev->vow_cfg.vow_sta_dwrr_quantum[q] << 8), q); |
| 287 | + q = msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_VI]; |
| 288 | + dev_info(dev->mt76.dev, "Ac1 --> %uus(%u)\n", |
| 289 | + (dev->vow_cfg.vow_sta_dwrr_quantum[q] << 8), q); |
| 290 | + q = msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_BE]; |
| 291 | + dev_info(dev->mt76.dev, "Ac2 --> %uus(%u)\n", |
| 292 | + (dev->vow_cfg.vow_sta_dwrr_quantum[q] << 8), q); |
| 293 | + q = msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_BK]; |
| 294 | + dev_info(dev->mt76.dev, "Ac3 --> %uus(%u)\n", |
| 295 | + (dev->vow_cfg.vow_sta_dwrr_quantum[q] << 8), q); |
| 296 | + } |
| 297 | + else{ |
| 298 | + for (i = 1; i < MT7915_WTBL_STA; i++) { |
| 299 | + wcid = rcu_dereference(dev->mt76.wcid[i]); |
| 300 | + if (!wcid || !wcid->sta) |
| 301 | + continue; |
| 302 | + msta = container_of(wcid, struct mt7915_sta, wcid); |
| 303 | + ieee80211_sta = container_of((void *)msta, struct ieee80211_sta, |
| 304 | + drv_priv); |
| 305 | + dev_info(dev->mt76.dev, "%s: ****** sta%d: "MACSTR"******\n", |
| 306 | + __func__, i, MAC2STR(ieee80211_sta->addr)); |
| 307 | + q = msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_VO]; |
| 308 | + dev_info(dev->mt76.dev, "Ac0 --> %uus(%u)\n", |
| 309 | + (dev->vow_cfg.vow_sta_dwrr_quantum[q] << 8), q); |
| 310 | + q = msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_VI]; |
| 311 | + dev_info(dev->mt76.dev, "Ac1 --> %uus(%u)\n", |
| 312 | + (dev->vow_cfg.vow_sta_dwrr_quantum[q] << 8), q); |
| 313 | + q = msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_BE]; |
| 314 | + dev_info(dev->mt76.dev, "Ac2 --> %uus(%u)\n", |
| 315 | + (dev->vow_cfg.vow_sta_dwrr_quantum[q] << 8), q); |
| 316 | + q = msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_BK]; |
| 317 | + dev_info(dev->mt76.dev, "Ac3 --> %uus(%u)\n", |
| 318 | + (dev->vow_cfg.vow_sta_dwrr_quantum[q] << 8), q); |
| 319 | + } |
| 320 | + } |
| 321 | + return 0; |
| 322 | +} |
| 323 | + |
| 324 | +static ssize_t |
| 325 | +mt7915_vow_set(struct file *file, const char __user *user_buf, |
| 326 | + size_t count, loff_t *ppos) |
| 327 | +{ |
| 328 | + struct mt7915_phy *phy = file->private_data; |
| 329 | + struct mt7915_dev *dev = phy->dev; |
| 330 | + u32 rv, param1, param2, param3; |
| 331 | + char buf[128]; |
| 332 | + int ret = 0; |
| 333 | + |
| 334 | + if (count >= sizeof(buf)) |
| 335 | + return -EINVAL; |
| 336 | + |
| 337 | + if (copy_from_user(buf, user_buf, count)) |
| 338 | + return -EFAULT; |
| 339 | + |
| 340 | + if (count && buf[count - 1] == '\n') |
| 341 | + buf[count - 1] = '\0'; |
| 342 | + else |
| 343 | + buf[count] = '\0'; |
| 344 | + |
| 345 | + if (!strncmp(buf, "vow_sta_dwrr_quantum_id", |
| 346 | + strlen("vow_sta_dwrr_quantum_id"))) |
| 347 | + { |
| 348 | + rv = sscanf(buf, "vow_sta_dwrr_quantum_id=%d-%d-%d", |
| 349 | + ¶m1, ¶m2, ¶m3); |
| 350 | + if ((rv > 2) && (param2 < IEEE80211_NUM_ACS) && |
| 351 | + (param3 < VOW_WATF_LEVEL_NUM)) { |
| 352 | + ret = mt7915_set_vow_sta_dwrr_quantum_id(dev, param1, |
| 353 | + param2, param3); |
| 354 | + } |
| 355 | + else { |
| 356 | + goto out; |
| 357 | + } |
| 358 | + } |
| 359 | + else if (!strncmp(buf, "vow_atf_en", strlen("vow_atf_en"))) |
| 360 | + { |
| 361 | + rv = sscanf(buf, "vow_atf_en=%d", ¶m1); |
| 362 | + if (rv > 0) { |
| 363 | + ret = mt7915_set_vow_atf_en(dev, param1); |
| 364 | + } |
| 365 | + else { |
| 366 | + goto out; |
| 367 | + } |
| 368 | + } |
| 369 | + else if (!strncmp(buf, "vow_dwrr_max_wait_time", |
| 370 | + strlen("vow_dwrr_max_wait_time"))) |
| 371 | + { |
| 372 | + rv = sscanf(buf, "vow_dwrr_max_wait_time=%d", ¶m1); |
| 373 | + if (rv > 0) { |
| 374 | + ret = mt7915_set_vow_dwrr_max_wait_time(dev, param1); |
| 375 | + } |
| 376 | + else { |
| 377 | + goto out; |
| 378 | + } |
| 379 | + } |
| 380 | + else if (!strncmp(buf, "vow_watf_en", strlen("vow_watf_en"))) |
| 381 | + { |
| 382 | + rv = sscanf(buf, "vow_watf_en=%d", ¶m1); |
| 383 | + if (rv > 0) { |
| 384 | + ret = mt7915_set_vow_watf_en(dev, param1); |
| 385 | + } |
| 386 | + else { |
| 387 | + goto out; |
| 388 | + } |
| 389 | + } |
| 390 | + else if (!strncmp(buf, "vow_watf_quantum", |
| 391 | + strlen("vow_watf_quantum"))) |
| 392 | + { |
| 393 | + rv = sscanf(buf, "vow_watf_quantum=%d-%d", |
| 394 | + ¶m1, ¶m2); |
| 395 | + if ((dev->vow_cfg.vow_watf_en) && (rv > 1) && |
| 396 | + (param1 < VOW_WATF_LEVEL_NUM)) { |
| 397 | + ret = mt7915_set_vow_watf_quantum(dev, param1, param2); |
| 398 | + } |
| 399 | + else { |
| 400 | + goto out; |
| 401 | + } |
| 402 | + } |
| 403 | + else if (!strncmp(buf, "vow_show_en", strlen("vow_show_en"))) |
| 404 | + { |
| 405 | + rv = sscanf(buf, "vow_show_en=%d", ¶m1); |
| 406 | + if (rv > 0) { |
| 407 | + ret = mt7915_set_vow_show_en(dev, param1); |
| 408 | + } |
| 409 | + else { |
| 410 | + goto out; |
| 411 | + } |
| 412 | + } |
| 413 | + else if (!strncmp(buf, "vow_show_sta", strlen("vow_show_sta"))) |
| 414 | + { |
| 415 | + rv = sscanf(buf, "vow_show_sta=%d", ¶m1); |
| 416 | + if ((rv > 0)&& (param1 < MT7915_WTBL_STA)) { |
| 417 | + ret = mt7915_set_vow_show_sta(dev, param1); |
| 418 | + } |
| 419 | + else { |
| 420 | + goto out; |
| 421 | + } |
| 422 | + } |
| 423 | + else if (!strncmp(buf, "show_vow_info", strlen("show_vow_info"))) |
| 424 | + { |
| 425 | + if (rv == 0) { |
| 426 | + ret = mt7915_set_show_vow_info(dev); |
| 427 | + } |
| 428 | + else { |
| 429 | + dev_err(dev->mt76.dev, "show_vow_info\n"); |
| 430 | + goto out; |
| 431 | + } |
| 432 | + } |
| 433 | + else if (!strncmp(buf, "show_vow_sta_conf", strlen("show_vow_sta_conf"))) |
| 434 | + { |
| 435 | + rv = sscanf(buf, "show_vow_sta_conf=%d", ¶m1); |
| 436 | + if ((rv > 0) && (param1 < MT7915_WTBL_STA)) { |
| 437 | + ret = mt7915_show_vow_sta_conf(dev, param1); |
| 438 | + } |
| 439 | + else { |
| 440 | + goto out; |
| 441 | + } |
| 442 | + } |
| 443 | + |
| 444 | + if (ret) |
| 445 | + return ret; |
| 446 | +out: |
| 447 | + return count; |
| 448 | +} |
| 449 | + |
| 450 | +static const struct file_operations mt7915_vow_ops = { |
| 451 | + .write = mt7915_vow_set, |
| 452 | + .read = mt7915_vow_get, |
| 453 | + .open = simple_open, |
| 454 | + .llseek = default_llseek, |
| 455 | +}; |
| 456 | + |
| 457 | static int |
| 458 | mt7915_radar_trigger(void *data, u64 val) |
| 459 | { |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 460 | @@ -1107,6 +1511,7 @@ int mt7915_init_debugfs(struct mt7915_phy *phy) |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 461 | debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir, |
| 462 | mt7915_twt_stats); |
| 463 | debugfs_create_file("rf_regval", 0600, dir, dev, &fops_rf_regval); |
| 464 | + debugfs_create_file("vow", 0600, dir, phy, &mt7915_vow_ops); |
| 465 | |
| 466 | if (!dev->dbdc_support || phy->band_idx) { |
| 467 | debugfs_create_u32("dfs_hw_pattern", 0400, dir, |
| 468 | diff --git a/mt7915/init.c b/mt7915/init.c |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 469 | old mode 100644 |
| 470 | new mode 100755 |
| 471 | index 039a5b01..5a7fdb51 |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 472 | --- a/mt7915/init.c |
| 473 | +++ b/mt7915/init.c |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 474 | @@ -473,10 +473,46 @@ mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) |
| 475 | mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 476 | } |
| 477 | |
| 478 | +void mt7915_vow_init(struct mt7915_dev *dev) |
| 479 | +{ |
| 480 | + struct mt7915_vow_cfg *vow_cfg = &dev->vow_cfg; |
| 481 | + bool ret; |
| 482 | + int i; |
| 483 | + |
| 484 | + if (!(is_mt7915(&dev->mt76))) |
| 485 | + vow_cfg->vow_feature |= VOW_FEATURE_BWCG; |
| 486 | + |
| 487 | + vow_cfg->vow_atf_en = 0x1; |
| 488 | + vow_cfg->sta_max_wait_time = 0x40; |
| 489 | + vow_cfg->refill_period = 0x5; |
| 490 | + |
| 491 | + vow_cfg->vow_sta_dwrr_quantum[0] = 0x06; |
| 492 | + vow_cfg->vow_sta_dwrr_quantum[1] = 0x0c; |
| 493 | + vow_cfg->vow_sta_dwrr_quantum[2] = 0x10; |
| 494 | + vow_cfg->vow_sta_dwrr_quantum[3] = 0x14; |
| 495 | + vow_cfg->vow_sta_dwrr_quantum[4] = 0x18; |
| 496 | + vow_cfg->vow_sta_dwrr_quantum[5] = 0x1c; |
| 497 | + vow_cfg->vow_sta_dwrr_quantum[6] = 0x20; |
| 498 | + vow_cfg->vow_sta_dwrr_quantum[7] = 0x24; |
| 499 | + |
| 500 | + ret = mt7915_mcu_set_vow_drr_ctrl(dev, NULL, |
| 501 | + VOW_DRR_AIRTIME_DEFICIT_BOUND); |
| 502 | + ret = mt7915_mcu_set_vow_drr_ctrl(dev, NULL, |
| 503 | + VOW_DRR_AIRTIME_QUANTUM_ALL); |
| 504 | + |
| 505 | + for(i = 0; i < 4; i++) |
| 506 | + ret = mt7915_mcu_set_vow_drr_ctrl(dev, NULL, |
| 507 | + VOW_DRR_AIRTIME_QUANTUM_L0 + i); |
| 508 | + |
| 509 | + ret = mt7915_mcu_set_vow_feature_ctrl(dev); |
| 510 | + return; |
| 511 | +} |
| 512 | + |
| 513 | void mt7915_mac_init(struct mt7915_dev *dev) |
| 514 | { |
| 515 | int i; |
| 516 | u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; |
| 517 | + struct wiphy *wiphy = dev->phy.mt76->hw->wiphy; |
| 518 | |
| 519 | /* config pse qid6 wfdma port selection */ |
| 520 | if (!is_mt7915(&dev->mt76) && dev->hif2) |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 521 | @@ -501,6 +537,9 @@ void mt7915_mac_init(struct mt7915_dev *dev) |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 522 | i = dev->mt76.led_pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; |
| 523 | mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); |
| 524 | } |
| 525 | + |
| 526 | + if (mt7915_is_atf_defult_on(wiphy, dev)) |
| 527 | + mt7915_vow_init(dev); |
| 528 | } |
| 529 | |
| 530 | int mt7915_txbf_init(struct mt7915_dev *dev) |
| 531 | diff --git a/mt7915/main.c b/mt7915/main.c |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 532 | index 4ac5259d..6c910cf5 100644 |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 533 | --- a/mt7915/main.c |
| 534 | +++ b/mt7915/main.c |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 535 | @@ -195,6 +195,7 @@ static int mt7915_add_interface(struct ieee80211_hw *hw, |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 536 | { |
| 537 | struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; |
| 538 | struct mt7915_dev *dev = mt7915_hw_dev(hw); |
| 539 | + struct wiphy *wiphy = dev->phy.mt76->hw->wiphy; |
| 540 | struct mt7915_phy *phy = mt7915_hw_phy(hw); |
| 541 | struct mt76_txq *mtxq; |
| 542 | bool ext_phy = phy != &dev->phy; |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 543 | @@ -264,6 +265,10 @@ static int mt7915_add_interface(struct ieee80211_hw *hw, |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 544 | mt7915_mcu_add_sta(dev, vif, NULL, true); |
| 545 | rcu_assign_pointer(dev->mt76.wcid[idx], &mvif->sta.wcid); |
| 546 | |
| 547 | + if (mt7915_is_atf_defult_on(wiphy, dev)) { |
| 548 | + mt7915_mcu_set_vow_band(dev, mvif); |
| 549 | + } |
| 550 | + |
| 551 | out: |
| 552 | mutex_unlock(&dev->mt76.mutex); |
| 553 | |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 554 | @@ -685,6 +690,7 @@ int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 555 | struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; |
| 556 | struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; |
| 557 | bool ext_phy = mvif->phy != &dev->phy; |
| 558 | + struct wiphy *wiphy = dev->phy.mt76->hw->wiphy; |
| 559 | #ifdef CONFIG_MTK_VENDOR |
| 560 | struct mt7915_phy *phy; |
| 561 | #endif |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 562 | @@ -739,6 +745,16 @@ int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 563 | mt7915_mcu_set_mimo(phy, 0); |
| 564 | } |
| 565 | #endif |
| 566 | + if (mt7915_is_atf_defult_on(wiphy, dev)) { |
| 567 | + msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_VO] = 2; |
| 568 | + msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_VI] = 2; |
| 569 | + msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_BE] = 1; |
| 570 | + msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_BK] = 0; |
| 571 | + mt7915_mcu_set_vow_drr_ctrl(dev, msta, VOW_DRR_STA_BSS_GROUP); |
| 572 | + mt7915_mcu_set_vow_drr_ctrl(dev, msta, VOW_DRR_STA_PAUSE_SETTING); |
| 573 | + mt7915_mcu_set_vow_drr_ctrl(dev, msta, VOW_DRR_STA_ALL); |
| 574 | + } |
| 575 | + |
| 576 | return 0; |
| 577 | } |
| 578 | |
| 579 | diff --git a/mt7915/mcu.c b/mt7915/mcu.c |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 580 | index ad2d6a39..4728d849 100644 |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 581 | --- a/mt7915/mcu.c |
| 582 | +++ b/mt7915/mcu.c |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 583 | @@ -3323,6 +3323,171 @@ int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band) |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 584 | &req, sizeof(req), false); |
| 585 | } |
| 586 | |
| 587 | +int mt7915_mcu_set_vow_drr_ctrl(struct mt7915_dev *dev, |
| 588 | + struct mt7915_sta *msta, |
| 589 | + u32 subcmd) |
| 590 | +{ |
| 591 | + u32 setting = 0; |
| 592 | + u32 i; |
| 593 | + |
| 594 | + struct { |
| 595 | + __le32 action; |
| 596 | + u8 wlan_idx_lo; |
| 597 | + u8 status; |
| 598 | + u8 wlan_idx_hi; |
| 599 | + u8 rsv0[5]; |
| 600 | + union { |
| 601 | + __le32 com_value; |
| 602 | + struct { |
| 603 | + u8 air_time_quantum[VOW_MAX_STA_DWRR_NUM]; |
| 604 | + }air_time_quantum_all; |
| 605 | + }air_time_ctrl; |
| 606 | + } __packed req = { |
| 607 | + .action = cpu_to_le32(subcmd), |
| 608 | + .wlan_idx_lo = msta ? to_wcid_lo(msta->wcid.idx) : to_wcid_lo(0x0), |
| 609 | + .wlan_idx_hi = msta ? to_wcid_hi(msta->wcid.idx) : to_wcid_hi(0x0), |
| 610 | + }; |
| 611 | + |
| 612 | + switch (subcmd) { |
| 613 | + case VOW_DRR_STA_ALL:{ |
| 614 | + setting |= 0x00; |
| 615 | + setting |= msta->vif->mt76.idx; |
| 616 | + setting |= msta->vow_sta_cfg.ac_change_rule << 4; |
| 617 | + setting |= (msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_VO] << 8); |
| 618 | + setting |= (msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_VI] << 12); |
| 619 | + setting |= (msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_BE] << 16); |
| 620 | + setting |= (msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_BK] << 20); |
| 621 | + if (dev->vow_cfg.vow_feature & VOW_FEATURE_BWCG) |
| 622 | + setting |= ((UMAC_BWC_GROUP_MIN) << 24); |
| 623 | + req.air_time_ctrl.com_value = cpu_to_le32(setting); |
| 624 | + break; |
| 625 | + } |
| 626 | + |
| 627 | + case VOW_DRR_STA_BSS_GROUP: |
| 628 | + req.air_time_ctrl.com_value = cpu_to_le32(0x0); |
| 629 | + break; |
| 630 | + |
| 631 | + case VOW_DRR_STA_PAUSE_SETTING: |
| 632 | + req.air_time_ctrl.com_value = cpu_to_le32(msta->vow_sta_cfg.paused); |
| 633 | + break; |
| 634 | + |
| 635 | + case VOW_DRR_STA_AC0_QUA_ID: |
| 636 | + req.air_time_ctrl.com_value = |
| 637 | + cpu_to_le32(msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_VO]); |
| 638 | + break; |
| 639 | + |
| 640 | + case VOW_DRR_STA_AC1_QUA_ID: |
| 641 | + req.air_time_ctrl.com_value = |
| 642 | + cpu_to_le32(msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_VI]); |
| 643 | + break; |
| 644 | + |
| 645 | + case VOW_DRR_STA_AC2_QUA_ID: |
| 646 | + req.air_time_ctrl.com_value = |
| 647 | + cpu_to_le32(msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_BE]); |
| 648 | + break; |
| 649 | + |
| 650 | + case VOW_DRR_STA_AC3_QUA_ID: |
| 651 | + req.air_time_ctrl.com_value = |
| 652 | + cpu_to_le32(msta->vow_sta_cfg.dwrr_quantum[IEEE80211_AC_BK]); |
| 653 | + break; |
| 654 | + |
| 655 | + case VOW_DRR_AIRTIME_DEFICIT_BOUND: |
| 656 | + req.air_time_ctrl.com_value = |
| 657 | + cpu_to_le32(dev->vow_cfg.sta_max_wait_time); |
| 658 | + break; |
| 659 | + |
| 660 | + case VOW_DRR_AIRTIME_QUANTUM_L0: |
| 661 | + case VOW_DRR_AIRTIME_QUANTUM_L1: |
| 662 | + case VOW_DRR_AIRTIME_QUANTUM_L2: |
| 663 | + case VOW_DRR_AIRTIME_QUANTUM_L3: |
| 664 | + case VOW_DRR_AIRTIME_QUANTUM_L4: |
| 665 | + case VOW_DRR_AIRTIME_QUANTUM_L5: |
| 666 | + case VOW_DRR_AIRTIME_QUANTUM_L6: |
| 667 | + case VOW_DRR_AIRTIME_QUANTUM_L7: |
| 668 | + req.air_time_ctrl.com_value = |
| 669 | + cpu_to_le32(dev->vow_cfg.vow_sta_dwrr_quantum[subcmd - |
| 670 | + VOW_DRR_AIRTIME_QUANTUM_L0]); |
| 671 | + break; |
| 672 | + |
| 673 | + case VOW_DRR_AIRTIME_QUANTUM_ALL: { |
| 674 | + for (i = 0; i < VOW_MAX_STA_DWRR_NUM; i++) { |
| 675 | + req.air_time_ctrl.air_time_quantum_all.air_time_quantum[i] = |
| 676 | + dev->vow_cfg.vow_sta_dwrr_quantum[i]; |
| 677 | + } |
| 678 | + break; |
| 679 | + } |
| 680 | + |
| 681 | + default: |
| 682 | + break; |
| 683 | + } |
| 684 | + |
| 685 | + return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_DRR_CTRL), |
| 686 | + &req, sizeof(req), false); |
| 687 | +} |
| 688 | + |
| 689 | +int mt7915_mcu_set_vow_feature_ctrl(struct mt7915_dev *dev) |
| 690 | +{ |
| 691 | + u16 value = 0; |
| 692 | + u32 sch_value = 0; |
| 693 | + |
| 694 | + struct vow_feature_ctrl { |
| 695 | + __le16 bss_flag; |
| 696 | + __le16 vow_ctrl_flag; |
| 697 | + __le16 bss_value[9]; |
| 698 | + __le16 vow_ctrl_val; |
| 699 | + __le16 time_token_value[2]; |
| 700 | + __le16 length_token_value[2]; |
| 701 | + __le32 tx_ctrl; |
| 702 | + __le32 sch_ctrl; |
| 703 | + } __packed req = { |
| 704 | + .bss_flag = cpu_to_le16(0xffff), |
| 705 | + .vow_ctrl_flag = cpu_to_le16(0xf231), |
| 706 | + .bss_value[0] = cpu_to_le16(0xffff), |
| 707 | + .bss_value[2] = cpu_to_le16(0xffff), |
| 708 | + .bss_value[8] = cpu_to_le16(0xffff), |
| 709 | + .time_token_value[0] = cpu_to_le16(0xffff), |
| 710 | + }; |
| 711 | + |
| 712 | + value |= dev->vow_cfg.refill_period; |
| 713 | + value |= 1 << 4; |
| 714 | + value |= 1 << 5; |
| 715 | + value |= dev->vow_cfg.vow_watf_en << 9; |
| 716 | + value |= 1 << 12; |
| 717 | + value |= dev->vow_cfg.vow_atf_en << 13; |
| 718 | + value |= 1 << 14; |
| 719 | + req.vow_ctrl_val = value; |
| 720 | + if (dev->vow_cfg.vow_atf_en) |
| 721 | + req.tx_ctrl = cpu_to_le32(0x6bf69e1f); |
| 722 | + sch_value |= 1 << 6; |
| 723 | + sch_value |= (((dev->vow_cfg.vow_show_en == 0) ? 0 : |
| 724 | + (dev->vow_cfg.vow_show_en - 1 )) << 4); |
| 725 | + req.sch_ctrl = sch_value; |
| 726 | + |
| 727 | + return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_FEATURE_CTRL), |
| 728 | + &req, sizeof(req), false); |
| 729 | +} |
| 730 | + |
| 731 | +int mt7915_mcu_set_vow_band(struct mt7915_dev *dev, struct mt7915_vif *mvif) |
| 732 | +{ |
| 733 | + struct module_ctrl { |
| 734 | + __le16 action; |
| 735 | + __le16 sub_action; |
| 736 | + __le32 rsv1[5]; |
| 737 | + u8 rsv2[72]; |
| 738 | + u8 group_idx; |
| 739 | + u8 band_idx; |
| 740 | + u8 rsv3[2]; |
| 741 | + } __packed req = { |
| 742 | + .action = cpu_to_le16(0x1), |
| 743 | + .sub_action = cpu_to_le16(0x4), |
| 744 | + .group_idx = mvif->mt76.band_idx * 4 + mvif->mt76.omac_idx % 4, |
| 745 | + .band_idx = mvif->mt76.band_idx, |
| 746 | + }; |
| 747 | + |
| 748 | + return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(AT_PROC_MODULE), |
| 749 | + &req, sizeof(req), false); |
| 750 | +} |
| 751 | + |
| 752 | int mt7915_mcu_set_txbf(struct mt7915_dev *dev, u8 action) |
| 753 | { |
| 754 | struct { |
| 755 | diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 756 | index d93c394c..e5e861b8 100644 |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 757 | --- a/mt7915/mt7915.h |
| 758 | +++ b/mt7915/mt7915.h |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 759 | @@ -131,6 +131,58 @@ struct mt7915_twt_flow { |
| 760 | |
| 761 | DECLARE_EWMA(avg_signal, 10, 8) |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 762 | |
| 763 | +#define VOW_MAX_STA_DWRR_NUM 8 |
| 764 | +#define VOW_WATF_LEVEL_NUM 4 |
| 765 | +#define VOW_FEATURE_BWCG BIT(3) |
| 766 | +#define UMAC_BWC_GROUP_MIN 40 |
| 767 | + |
| 768 | + |
| 769 | +enum ext_cmd_vow_drr_ctrl { |
| 770 | + /* Type 1 */ |
| 771 | + VOW_DRR_STA_ALL = 0x00, |
| 772 | + VOW_DRR_STA_BSS_GROUP = 0x01, |
| 773 | + VOW_DRR_STA_AC0_QUA_ID = 0x03, |
| 774 | + VOW_DRR_STA_AC1_QUA_ID = 0x04, |
| 775 | + VOW_DRR_STA_AC2_QUA_ID = 0x05, |
| 776 | + VOW_DRR_STA_AC3_QUA_ID = 0x06, |
| 777 | + |
| 778 | + /* Type 2 */ |
| 779 | + VOW_DRR_AIRTIME_DEFICIT_BOUND = 0x10, |
| 780 | + |
| 781 | + /* Type 3 */ |
| 782 | + VOW_DRR_AIRTIME_QUANTUM_L0 = 0x20, |
| 783 | + VOW_DRR_AIRTIME_QUANTUM_L1 = 0x21, |
| 784 | + VOW_DRR_AIRTIME_QUANTUM_L2 = 0x22, |
| 785 | + VOW_DRR_AIRTIME_QUANTUM_L3 = 0x23, |
| 786 | + VOW_DRR_AIRTIME_QUANTUM_L4 = 0x24, |
| 787 | + VOW_DRR_AIRTIME_QUANTUM_L5 = 0x25, |
| 788 | + VOW_DRR_AIRTIME_QUANTUM_L6 = 0x26, |
| 789 | + VOW_DRR_AIRTIME_QUANTUM_L7 = 0x27, |
| 790 | + VOW_DRR_AIRTIME_QUANTUM_ALL = 0x28, |
| 791 | + VOW_DRR_STA_PAUSE_SETTING = 0x30, |
| 792 | +}; |
| 793 | + |
| 794 | +struct mt7915_vow_sta_cfg{ |
| 795 | + u8 dwrr_quantum[IEEE80211_NUM_ACS]; |
| 796 | + u8 ac_change_rule; |
| 797 | + bool paused; |
| 798 | +}; |
| 799 | + |
| 800 | +struct mt7915_vow_cfg{ |
| 801 | + /*ATF setting */ |
| 802 | + u32 vow_feature; |
| 803 | + bool vow_atf_en; |
| 804 | + u8 refill_period; |
| 805 | + u8 sta_max_wait_time; |
| 806 | + u8 vow_sta_dwrr_quantum[VOW_MAX_STA_DWRR_NUM]; |
| 807 | + u8 vow_show_en; |
| 808 | + u32 vow_show_sta; |
| 809 | + |
| 810 | + /*WATF setting */ |
| 811 | + bool vow_watf_en; |
| 812 | +}; |
| 813 | + |
| 814 | + |
| 815 | struct mt7915_sta { |
| 816 | struct mt76_wcid wcid; /* must be first */ |
| 817 | |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 818 | @@ -152,6 +204,7 @@ struct mt7915_sta { |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 819 | u8 flowid_mask; |
| 820 | struct mt7915_twt_flow flow[MT7915_MAX_STA_TWT_AGRT]; |
| 821 | } twt; |
| 822 | + struct mt7915_vow_sta_cfg vow_sta_cfg; |
| 823 | }; |
| 824 | |
| 825 | struct mt7915_vif_cap { |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 826 | @@ -466,6 +519,8 @@ struct mt7915_dev { |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 827 | } dbg; |
| 828 | const struct mt7915_dbg_reg_desc *dbg_reg; |
| 829 | #endif |
| 830 | + struct delayed_work vow_work; |
| 831 | + struct mt7915_vow_cfg vow_cfg; |
| 832 | }; |
| 833 | |
| 834 | enum { |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 835 | @@ -498,6 +553,15 @@ enum mt7915_rdd_cmd { |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 836 | RDD_IRQ_OFF, |
| 837 | }; |
| 838 | |
| 839 | +static inline bool |
| 840 | +mt7915_is_atf_defult_on(struct wiphy *wiphy, struct mt7915_dev *dev) |
| 841 | +{ |
| 842 | + return ((!wiphy_ext_feature_isset(wiphy, |
| 843 | + NL80211_EXT_FEATURE_AIRTIME_FAIRNESS)) || |
| 844 | + mtk_wed_device_active(&dev->mt76.mmio.wed)); |
| 845 | +} |
| 846 | + |
| 847 | + |
| 848 | static inline struct mt7915_phy * |
| 849 | mt7915_hw_phy(struct ieee80211_hw *hw) |
| 850 | { |
developer | 356ecec | 2022-11-14 10:25:04 +0800 | [diff] [blame^] | 851 | @@ -629,6 +693,10 @@ int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable, |
developer | c978ea1 | 2022-11-09 15:58:31 +0800 | [diff] [blame] | 852 | int mt7915_mcu_set_test_param(struct mt7915_dev *dev, u8 param, bool test_mode, |
| 853 | u8 en); |
| 854 | int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band); |
| 855 | +int mt7915_mcu_set_vow_drr_ctrl(struct mt7915_dev *dev, struct mt7915_sta *msta, |
| 856 | + u32 subcmd); |
| 857 | +int mt7915_mcu_set_vow_feature_ctrl(struct mt7915_dev *dev); |
| 858 | +int mt7915_mcu_set_vow_band(struct mt7915_dev *dev, struct mt7915_vif *mvif); |
| 859 | int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable); |
| 860 | int mt7915_mcu_set_txpower_sku(struct mt7915_phy *phy); |
| 861 | int mt7915_mcu_get_txpower_sku(struct mt7915_phy *phy, s8 *txpower, int len); |
| 862 | diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c |
| 863 | index 41bd0ff1..12251d91 100644 |
| 864 | --- a/mt7915/mtk_debugfs.c |
| 865 | +++ b/mt7915/mtk_debugfs.c |
| 866 | @@ -1300,7 +1300,6 @@ static EMPTY_QUEUE_INFO_T ple_txcmd_queue_empty_info[] = { |
| 867 | }; |
| 868 | |
| 869 | |
| 870 | - |
| 871 | static char* sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"}; |
| 872 | static u32 chip_show_sta_acq_info(struct seq_file *s, struct mt7915_dev *dev, u32 *ple_stat, |
| 873 | u32 *sta_pause, u32 *dis_sta_map, |
| 874 | @@ -1454,6 +1453,138 @@ static void chip_get_sta_pause(struct mt7915_dev *dev, u32 *sta_pause) |
| 875 | } |
| 876 | } |
| 877 | |
| 878 | +u32 vow_chip_show_sta_acq_info(struct mt7915_dev *dev, u32 *ple_stat, |
| 879 | + u32 *sta_pause, u32 *dis_sta_map, |
| 880 | + u32 dumptxd) |
| 881 | +{ |
| 882 | + int i, j; |
| 883 | + u32 total_nonempty_cnt = 0; |
| 884 | + u32 ac_num = 9, all_ac_num; |
| 885 | + static char* sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"}; |
| 886 | + if (!is_mt7915(&dev->mt76)) |
| 887 | + ac_num = 17; |
| 888 | + |
| 889 | + all_ac_num = ac_num * 4; |
| 890 | + |
| 891 | + for (j = 0; j < all_ac_num; j++) { /* show AC Q info */ |
| 892 | + for (i = 0; i < 32; i++) { |
| 893 | + if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) { |
| 894 | + u32 hfid, tfid, pktcnt, ac_n = j / ac_num, ctrl = 0; |
| 895 | + u32 sta_num = i + (j % ac_num) * 32, fl_que_ctrl[3] = {0}; |
| 896 | + u32 wmmidx = 0; |
| 897 | + struct mt7915_sta *msta; |
| 898 | + struct mt76_wcid *wcid; |
| 899 | + struct ieee80211_sta *sta = NULL; |
| 900 | + |
| 901 | + wcid = rcu_dereference(dev->mt76.wcid[sta_num]); |
| 902 | + sta = wcid_to_sta(wcid); |
| 903 | + if (!sta) { |
| 904 | + printk("ERROR!! no found STA wcid=%d\n", sta_num); |
| 905 | + continue; |
| 906 | + } |
| 907 | + msta = container_of(wcid, struct mt7915_sta, wcid); |
| 908 | + wmmidx = msta->vif->mt76.wmm_idx; |
| 909 | + |
| 910 | + dev_info(dev->mt76.dev, "\tSTA%d AC%d: ", sta_num, ac_n); |
| 911 | + |
| 912 | + fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK; |
| 913 | + fl_que_ctrl[0] |= (ENUM_UMAC_LMAC_PORT_2 << |
| 914 | + MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT); |
| 915 | + fl_que_ctrl[0] |= (ac_n << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT); |
| 916 | + fl_que_ctrl[0] |= sta_num; |
| 917 | + mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]); |
| 918 | + fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2); |
| 919 | + fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3); |
| 920 | + hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, |
| 921 | + fl_que_ctrl[1]); |
| 922 | + tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, |
| 923 | + fl_que_ctrl[1]); |
| 924 | + pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, |
| 925 | + fl_que_ctrl[2]); |
| 926 | + dev_info(dev->mt76.dev, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x", |
| 927 | + tfid, hfid, pktcnt); |
| 928 | + |
| 929 | + if (((sta_pause[j % 6] & 0x1 << i) >> i) == 1) |
| 930 | + ctrl = 2; |
| 931 | + |
| 932 | + if (((dis_sta_map[j % 6] & 0x1 << i) >> i) == 1) |
| 933 | + ctrl = 1; |
| 934 | + |
| 935 | + dev_info(dev->mt76.dev, " ctrl = %s", sta_ctrl_reg[ctrl]); |
| 936 | + dev_info(dev->mt76.dev, " (wmmidx=%d)\n", wmmidx); |
| 937 | + |
| 938 | + total_nonempty_cnt++; |
| 939 | + } |
| 940 | + } |
| 941 | + } |
| 942 | + |
| 943 | + return total_nonempty_cnt; |
| 944 | +} |
| 945 | + |
| 946 | +int mt7915_vow_pleinfo_read(struct mt7915_dev *dev) |
| 947 | +{ |
| 948 | + u32 ple_stat[70] = {0}, pg_flow_ctrl[8] = {0}; |
| 949 | + u32 ple_txcmd_stat; |
| 950 | + u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0}; |
| 951 | + int i; |
| 952 | + |
| 953 | + chip_get_ple_acq_stat(dev, ple_stat); |
| 954 | + ple_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_TXCMD_Q_EMPTY); |
| 955 | + pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PLE_FREEPG_CNT); |
| 956 | + pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FREEPG_HEAD_TAIL); |
| 957 | + pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_GROUP); |
| 958 | + pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PLE_HIF_PG_INFO); |
| 959 | + pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PLE_PG_CPU_GROUP); |
| 960 | + pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PLE_CPU_PG_INFO); |
| 961 | + pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_TXCMD_GROUP); |
| 962 | + pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PLE_HIF_TXCMD_PG_INFO); |
| 963 | + chip_get_dis_sta_map(dev, dis_sta_map); |
| 964 | + chip_get_sta_pause(dev, sta_pause); |
| 965 | + |
| 966 | + dev_info(dev->mt76.dev, "PLE Configuration Info:\n"); |
| 967 | + |
| 968 | + for (i = 0; i < 32; i++) { |
| 969 | + if (((ple_stat[0] & (0x1 << i)) >> i) == 0) { |
| 970 | + u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0}; |
| 971 | + |
| 972 | + if (ple_queue_empty_info[i].QueueName != NULL) { |
| 973 | + fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK; |
| 974 | + fl_que_ctrl[0] |= (ple_queue_empty_info[i].Portid << |
| 975 | + MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT); |
| 976 | + fl_que_ctrl[0] |= (ple_queue_empty_info[i].Queueid << |
| 977 | + MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT); |
| 978 | + } else |
| 979 | + continue; |
| 980 | + |
| 981 | + if (ple_queue_empty_info[i].Queueid >= |
| 982 | + ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 && |
| 983 | + ple_queue_empty_info[i].Queueid <= |
| 984 | + ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0) |
| 985 | + /* band0 set TGID 0, bit31 = 0 */ |
| 986 | + mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x0); |
| 987 | + else if (ple_queue_empty_info[i].Queueid >= |
| 988 | + ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 && |
| 989 | + ple_queue_empty_info[i].Queueid <= |
| 990 | + ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1) |
| 991 | + /* band1 set TGID 1, bit31 = 1 */ |
| 992 | + mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x80000000); |
| 993 | + |
| 994 | + mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]); |
| 995 | + fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2); |
| 996 | + fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3); |
| 997 | + hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, |
| 998 | + fl_que_ctrl[1]); |
| 999 | + tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, |
| 1000 | + fl_que_ctrl[1]); |
| 1001 | + pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, |
| 1002 | + fl_que_ctrl[2]); |
| 1003 | + } |
| 1004 | + } |
| 1005 | + |
| 1006 | + vow_chip_show_sta_acq_info(dev, ple_stat, sta_pause, dis_sta_map, 0); |
| 1007 | + |
| 1008 | + return 0; |
| 1009 | +} |
| 1010 | static int mt7915_pleinfo_read(struct seq_file *s, void *data) |
| 1011 | { |
| 1012 | struct mt7915_dev *dev = dev_get_drvdata(s->private); |
| 1013 | -- |
| 1014 | 2.18.0 |
| 1015 | |