diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 2dbf968..3155324 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -2728,7 +2728,10 @@
 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
 
 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
-		/* PSE config input/output queue threshold */
+		/* PSE Free Queue Flow Control  */
+		mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);
+
+		/* PSE config input queue threshold */
 		mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1));
 		mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2));
 		mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3));
@@ -2738,6 +2741,7 @@
 		mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7));
 		mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8));
 
+		/* PSE config output queue threshold */
 		mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1));
 		mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2));
 		mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3));
@@ -2746,6 +2750,14 @@
 		mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6));
 		mtk_w32(eth, 0x00060006, PSE_OQ_TH(7));
 		mtk_w32(eth, 0x00060006, PSE_OQ_TH(8));
+
+		/* GDM and CDM Threshold */
+		mtk_w32(eth, 0x00000004, MTK_GDM2_THRES);
+                mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES);
+                mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES);
+                mtk_w32(eth, 0x00000004, MTK_CDME0_THRES);
+                mtk_w32(eth, 0x00000004, MTK_CDME1_THRES);
+                mtk_w32(eth, 0x00000004, MTK_CDMM_THRES);
 	}
 
 	return 0;
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index d02b248..8f152ab 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -108,12 +108,24 @@
 /* FE global misc reg*/
 #define MTK_FE_GLO_MISC         0x124
 
+/* PSE Free Queue Flow Control  */
+#define PSE_FQFC_CFG1		0x100
+#define PSE_FQFC_CFG2		0x104
+
 /* PSE Input Queue Reservation Register*/
 #define PSE_IQ_REV(x)		(0x140 + ((x - 1) * 0x4))
 
 /* PSE Output Queue Threshold Register*/
 #define PSE_OQ_TH(x)		(0x160 + ((x - 1) * 0x4))
 
+/* GDM and CDM Threshold */
+#define MTK_GDM2_THRES		0x1530
+#define MTK_CDMW0_THRES		0x164c
+#define MTK_CDMW1_THRES		0x1650
+#define MTK_CDME0_THRES		0x1654
+#define MTK_CDME1_THRES		0x1658
+#define MTK_CDMM_THRES		0x165c
+
 #define MTK_PDMA_V2		BIT(4)
 
 #if defined(CONFIG_MEDIATEK_NETSYS_V2)