[][kernel][mt7988][pwm][remove pwm CCF clocks from always-on list]
[Description]
Remove pwm CCF clocks from always-on list in mt7988-clkitg.dtsi,
This make sure that pwm driver can work correctlly with mt7988 CCF
framework, and don't need extra clock setting from bootloader and clock
drivers.
[Release-log]
N/A
Change-Id: I471e331bff0f054b8e21ad2420da4d407cea2f20
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6717601
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi
index 48ed6c0..c4831a3 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988-clkitg.dtsi
@@ -110,7 +110,7 @@
<&topckgen CK_TOP_SPIM_MST_SEL>,
<&topckgen CK_TOP_NFI1X_SEL>,
<&topckgen CK_TOP_SPINFI_SEL>,
- <&topckgen CK_TOP_PWM_SEL>,
+ <&system_clk>,
<&topckgen CK_TOP_I2C_SEL>,
<&topckgen CK_TOP_PCIE_MBIST_250M_SEL>,
<&system_clk>,
@@ -169,11 +169,11 @@
<&topckgen CK_TOP_ETH_MII_SEL>,
<&topckgen CK_TOP_CK_NPU_SEL_CM_TOPS_SEL>,
<&infracfg CK_INFRA_CK_F26M>,
- <&infracfg CK_INFRA_PWM_O>,
<&system_clk>,
<&system_clk>,
<&system_clk>,
<&system_clk>,
+ <&system_clk>,
<&infracfg CK_INFRA_133M_HCK>,
<&infracfg CK_INFRA_133M_PHCK>,
<&infracfg CK_INFRA_66M_PHCK>,
@@ -215,16 +215,16 @@
<&infracfg CK_INFRA_USB_SYS_O>,
<&infracfg CK_INFRA_USB_SYS_O_P1>,
<&infracfg_ao CK_INFRA_66M_GPT_BCK>,
- <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
- <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK8>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
<&infracfg_ao CK_INFRA_133M_CQDMA_BCK>,
<&infracfg_ao CK_INFRA_66M_AUD_SLV_BCK>,
<&infracfg_ao CK_INFRA_AUD_26M>,
@@ -304,15 +304,15 @@
<&infracfg_ao CK_INFRA_MUX_SPI0_SEL>,
<&infracfg_ao CK_INFRA_MUX_SPI1_SEL>,
<&infracfg_ao CK_INFRA_MUX_SPI2_SEL>,
- <&infracfg_ao CK_INFRA_PWM_SEL>,
- <&infracfg_ao CK_INFRA_PWM_CK1_SEL>,
- <&infracfg_ao CK_INFRA_PWM_CK2_SEL>,
- <&infracfg_ao CK_INFRA_PWM_CK3_SEL>,
- <&infracfg_ao CK_INFRA_PWM_CK4_SEL>,
- <&infracfg_ao CK_INFRA_PWM_CK5_SEL>,
- <&infracfg_ao CK_INFRA_PWM_CK6_SEL>,
- <&infracfg_ao CK_INFRA_PWM_CK7_SEL>,
- <&infracfg_ao CK_INFRA_PWM_CK8_SEL>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
+ <&system_clk>,
<&system_clk>,
<&system_clk>,
<&system_clk>,