diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.c
index 04e6b4e..b27c679 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.c
@@ -832,8 +832,7 @@
 	u32 val;
 
 	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-		if (!gsw->direct_access)
-			mt7531_phy_100m_eye_diag_setting(gsw, i);
+		mt7531_phy_100m_eye_diag_setting(gsw, i);
 
 		/* Enable HW auto downshift */
 		gsw->mii_write(gsw, i, 0x1f, 0x1);
@@ -857,14 +856,12 @@
 		val |= PHY_LINKDOWN_POWER_SAVING_EN;
 		gsw->mii_write(gsw, i, PHY_EXT_REG_17, val);
 
-		if (!gsw->direct_access) {
-			val = gsw->mmd_read(gsw, i, PHY_DEV1E,
-					    PHY_DEV1E_REG_0C6);
-			val &= ~PHY_POWER_SAVING_M;
-			val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
-			gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6,
-				       val);
-		}
+		val = gsw->mmd_read(gsw, i, PHY_DEV1E,
+				    PHY_DEV1E_REG_0C6);
+		val &= ~PHY_POWER_SAVING_M;
+		val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
+		gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6,
+			       val);
 
 		/* Timing Recovery for GbE slave mode */
 		mt753x_tr_write(gsw, i, PMA_CH, PMA_NOD, PMA_01, 0x6fb90a);
@@ -898,8 +895,7 @@
 	gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_273, 0x3000);
 
 	/* Adjust RX Echo path filter */
-	if (!gsw->direct_access)
-		gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_0FE, 0x2);
+	gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_0FE, 0x2);
 
 	/* Adjust RX HVGA bias current */
 	gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_41, 0x3333);
@@ -1071,12 +1067,6 @@
 	gsw->mmd_read = mt753x_mmd_read;
 	gsw->mmd_write = mt753x_mmd_write;
 
-	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-		val = gsw->mii_read(gsw, i, MII_BMCR);
-		val |= BMCR_ISOLATE;
-		gsw->mii_write(gsw, i, MII_BMCR, val);
-	}
-
 	speed = MAC_SPD_1000;
 	pmcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
 		MAC_MODE | MAC_TX_EN | MAC_RX_EN | BKOFF_EN |
@@ -1103,12 +1093,6 @@
 	/* Disable AFIFO reset for extra short IPG */
 	mt7531_afifo_reset(gsw, 0);
 
-	/* PHY force slave 1G*/
-	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-		gsw->mii_write(gsw, i, MII_CTRL1000, 0x1200);
-		gsw->mii_write(gsw, i, MII_BMCR, 0x140);
-	}
-
 	return 0;
 }
 
@@ -1129,8 +1113,7 @@
 	val |= POWER_ON_OFF;
 	gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val);
 
-	if (!gsw->direct_access)
-		mt7531_phy_pll_setup(gsw);
+	mt7531_phy_pll_setup(gsw);
 
 	/* Enable Internal PHYs before phy setting */
 	val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403);
@@ -1155,8 +1138,7 @@
 	for (i = 0; i < MT753X_NUM_PHYS; i++)
 		gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_141, 0x0);
 
-	if (!gsw->direct_access)
-		mt7531_internal_phy_calibration(gsw);
+	mt7531_internal_phy_calibration(gsw);
 
 	/* PHY force slave disable, restart AN*/
 	for (i = 0; i < MT753X_NUM_PHYS; i++) {
@@ -1178,7 +1160,6 @@
 	.model = MT7988,
 	.detect = mt7988_sw_detect,
 	.init = mt7988_sw_init,
-	.post_init = mt7531_sw_post_init
 };
 
 MODULE_LICENSE("GPL");