diff --git a/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3006-ethernet-update-ppe-from-mt7622-to-mt7986.patch b/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3006-ethernet-update-ppe-from-mt7622-to-mt7986.patch
new file mode 100755
index 0000000..c0efd12
--- /dev/null
+++ b/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3006-ethernet-update-ppe-from-mt7622-to-mt7986.patch
@@ -0,0 +1,371 @@
+From d86af0076cbf7d99bdb4f28115159643b79ad3fa Mon Sep 17 00:00:00 2001
+From: Sujuan Chen <sujuan.chen@mediatek.com>
+Date: Wed, 18 May 2022 11:08:15 +0800
+Subject: [PATCH 5/8] 9994-ethernet-update-ppe-from-mt7622-to-mt7986
+
+Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c   | 14 +++-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h   |  7 +-
+ drivers/net/ethernet/mediatek/mtk_ppe.c       | 24 ++++---
+ drivers/net/ethernet/mediatek/mtk_ppe.h       | 69 ++++++++++---------
+ .../net/ethernet/mediatek/mtk_ppe_offload.c   |  7 +-
+ drivers/net/ethernet/mediatek/mtk_ppe_regs.h  | 10 +++
+ 6 files changed, 86 insertions(+), 45 deletions(-)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 2121335a1..01fc1e5c0 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1467,16 +1467,27 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
+ 			skb_checksum_none_assert(skb);
+ 		skb->protocol = eth_type_trans(skb, netdev);
+ 
+-		hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
++#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
++			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2;
++#else
++			hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
++#endif
+ 		if (hash != MTK_RXD4_FOE_ENTRY) {
+ 			hash = jhash_1word(hash, 0);
+ 			skb_set_hash(skb, hash, PKT_HASH_TYPE_L4);
+ 		}
+ 
++#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
++		reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON_V2, trxd.rxd5);
++		if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
++			mtk_ppe_check_skb(eth->ppe, skb,
++					  trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2);
++#else
+ 		reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4);
+ 		if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
+ 			mtk_ppe_check_skb(eth->ppe, skb,
+ 					  trxd.rxd4 & MTK_RXD4_FOE_ENTRY);
++#endif
+ 
+ 		if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
+ 			if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
+@@ -3926,13 +3937,14 @@ static const struct mtk_soc_data mt7986_data = {
+ 	.required_clks = MT7986_CLKS_BITMAP,
+ 	.required_pctl = false,
+ 	.has_sram = true,
++	.offload_version = 2,
+	.rss_num = 0,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma_v2),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+ 		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
+ 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+ 		.dma_len_offset = MTK_TX_DMA_BUF_SHIFT_V2,
+ 	},
+ };
+ 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+index b52378bd6..fce1a7172 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -110,7 +110,7 @@
+ #define MTK_GDMA_TCS_EN		BIT(21)
+ #define MTK_GDMA_UCS_EN		BIT(20)
+ #define MTK_GDMA_TO_PDMA	0x0
+-#define MTK_GDMA_TO_PPE		0x4444
++#define MTK_GDMA_TO_PPE		0x3333
+ #define MTK_GDMA_DROP_ALL	0x7777
+ 
+ /* Unicast Filter MAC Address Register - Low */
+@@ -560,6 +560,11 @@
+ #define MTK_RXD4_SRC_PORT	GENMASK(21, 19)
+ #define MTK_RXD4_ALG		GENMASK(31, 22)
+ 
++/* QDMA descriptor rxd4 */
++#define MTK_RXD5_FOE_ENTRY_V2	GENMASK(14, 0)
++#define MTK_RXD5_PPE_CPU_REASON_V2	GENMASK(22, 18)
++#define MTK_RXD5_SRC_PORT_V2	GENMASK(29, 26)
++
+ /* QDMA descriptor rxd4 */
+ #define RX_DMA_L4_VALID		BIT(24)
+ #define RX_DMA_L4_VALID_PDMA	BIT(30)		/* when PDMA is used */
+diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c
+index 3d75c22be..d46e91178 100755
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
+@@ -122,7 +122,7 @@ static u32 mtk_ppe_hash_entry(struct mtk_foe_entry *e)
+ 	hash = (hash >> 24) | ((hash & 0xffffff) << 8);
+ 	hash ^= hv1 ^ hv2 ^ hv3;
+ 	hash ^= hash >> 16;
+-	hash <<= 1;
++	hash <<= 2;
+ 	hash &= MTK_PPE_ENTRIES - 1;
+ 
+ 	return hash;
+@@ -171,8 +171,12 @@ int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,
+ 	      MTK_FOE_IB1_BIND_CACHE;
+ 	entry->ib1 = val;
+
++#if defined(CONFIG_MEDIATEK_NETSYS_V2)
++	val = FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0xf) |
++#else
+ 	val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) |
+ 	      FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0x1f) |
++#endif
+ 	      FIELD_PREP(MTK_FOE_IB2_DEST_PORT, pse_port);
+ 
+ 	if (is_multicast_ether_addr(dest_mac))
+@@ -359,12 +358,19 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,
+ 
+ 	*ib2 &= ~MTK_FOE_IB2_PORT_MG;
+ 	*ib2 |= MTK_FOE_IB2_WDMA_WINFO;
++#if defined(CONFIG_MEDIATEK_NETSYS_V2)
++	*ib2 |=  FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq);
++
++	l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) |
++		    FIELD_PREP(MTK_FOE_WINFO_BSS, bss);
++#else
+ 	if (wdma_idx)
+ 		*ib2 |= MTK_FOE_IB2_WDMA_DEVIDX;
+ 
+ 	l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) |
+ 		    FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) |
+ 		    FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq);
++#endif
+ 
+ 	return 0;
+ }
+@@ -741,6 +738,9 @@ int mtk_ppe_start(struct mtk_ppe *ppe)
+ 	      MTK_PPE_TB_CFG_AGE_TCP |
+ 	      MTK_PPE_TB_CFG_AGE_UDP |
+ 	      MTK_PPE_TB_CFG_AGE_TCP_FIN |
++#if defined(CONFIG_MEDIATEK_NETSYS_V2)
++	      MTK_PPE_TB_CFG_INFO_SEL |
++#endif
+ 	      FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS,
+ 			 MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD) |
+ 	      FIELD_PREP(MTK_PPE_TB_CFG_KEEPALIVE,
+@@ -757,7 +755,8 @@ int mtk_ppe_start(struct mtk_ppe *ppe)
+ 
+ 	mtk_ppe_cache_enable(ppe, true);
+ 
+-	val = MTK_PPE_FLOW_CFG_IP4_TCP_FRAG |
++	val = MTK_PPE_MD_TOAP_BYP_CRSN0 |
++	      MTK_PPE_MD_TOAP_BYP_CRSN1 |
++	      MTK_PPE_MD_TOAP_BYP_CRSN2 |
+-	      MTK_PPE_FLOW_CFG_IP4_UDP_FRAG |
+ 	      MTK_PPE_FLOW_CFG_IP6_3T_ROUTE |
+ 	      MTK_PPE_FLOW_CFG_IP6_5T_ROUTE |
+@@ -765,7 +765,8 @@ int mtk_ppe_start(struct mtk_ppe *ppe)
+ 	      MTK_PPE_FLOW_CFG_IP4_NAT |
+ 	      MTK_PPE_FLOW_CFG_IP4_NAPT |
+ 	      MTK_PPE_FLOW_CFG_IP4_DSLITE |
+-	      MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;
++	      MTK_PPE_FLOW_CFG_IP4_NAT_FRAG |
++	      MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY;
+ 	ppe_w32(ppe, MTK_PPE_FLOW_CFG, val);
+ 
+ 	val = FIELD_PREP(MTK_PPE_UNBIND_AGE_MIN_PACKETS, 1000) |
+@@ -800,6 +801,11 @@ int mtk_ppe_start(struct mtk_ppe *ppe)
+ 
+ 	ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);
+
++#if defined(CONFIG_MEDIATEK_NETSYS_V2)
++	ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
++	ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
++#endif
++
+ 	return 0;
+ }
+ 
+diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h
+index 1f5cf1c9a..a76f4b0ac 100644
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
+@@ -8,7 +8,11 @@
+ #include <linux/bitfield.h>
+ #include <linux/rhashtable.h>
+
++#if defined(CONFIG_MEDIATEK_NETSYS_V2)
++#define MTK_ETH_PPE_BASE		0x2000
++#else
+ #define MTK_ETH_PPE_BASE		0xc00
++#endif
+ 
+ #define MTK_PPE_ENTRIES_SHIFT		3
+ #define MTK_PPE_ENTRIES			(1024 << MTK_PPE_ENTRIES_SHIFT)
+@@ -16,20 +16,40 @@
+ #define MTK_PPE_WAIT_TIMEOUT_US		1000000
+ 
+ #define MTK_FOE_IB1_UNBIND_TIMESTAMP	GENMASK(7, 0)
++#if defined(CONFIG_MEDIATEK_NETSYS_V2)
++#define MTK_FOE_IB1_UNBIND_SRC_PORT	GENMASK(11, 8)
++#define MTK_FOE_IB1_UNBIND_PACKETS	GENMASK(19, 12)
++#define MTK_FOE_IB1_UNBIND_PREBIND	BIT(22)
++#define MTK_FOE_IB1_UNBIND_PACKET_TYPE	GENMASK(27, 23)
++#define MTK_FOE_IB1_BIND_TIMESTAMP	GENMASK(7, 0)
++#define MTK_FOE_IB1_BIND_SRC_PORT	GENMASK(11, 8)
++#define MTK_FOE_IB1_BIND_MC		BIT(12)
++#define MTK_FOE_IB1_BIND_KEEPALIVE	BIT(13)
++#define MTK_FOE_IB1_BIND_VLAN_LAYER	GENMASK(16, 14)
++#define MTK_FOE_IB1_BIND_PPPOE		BIT(17)
++#define MTK_FOE_IB1_BIND_VLAN_TAG	BIT(18)
++#define MTK_FOE_IB1_BIND_PKT_SAMPLE	BIT(19)
++#define MTK_FOE_IB1_BIND_CACHE		BIT(20)
++#define MTK_FOE_IB1_BIND_TUNNEL_DECAP	BIT(21)
++#define MTK_FOE_IB1_BIND_TTL		BIT(22)
++#define MTK_FOE_IB1_PACKET_TYPE		GENMASK(27, 23)
++#else
+ #define MTK_FOE_IB1_UNBIND_PACKETS	GENMASK(23, 8)
+ #define MTK_FOE_IB1_UNBIND_PREBIND	BIT(24)
+ 
+ #define MTK_FOE_IB1_BIND_TIMESTAMP	GENMASK(14, 0)
+ #define MTK_FOE_IB1_BIND_KEEPALIVE	BIT(15)
+ #define MTK_FOE_IB1_BIND_VLAN_LAYER	GENMASK(18, 16)
+ #define MTK_FOE_IB1_BIND_PPPOE		BIT(19)
+ #define MTK_FOE_IB1_BIND_VLAN_TAG	BIT(20)
+ #define MTK_FOE_IB1_BIND_PKT_SAMPLE	BIT(21)
+ #define MTK_FOE_IB1_BIND_CACHE		BIT(22)
+ #define MTK_FOE_IB1_BIND_TUNNEL_DECAP	BIT(23)
+ #define MTK_FOE_IB1_BIND_TTL		BIT(24)
+ 
+ #define MTK_FOE_IB1_PACKET_TYPE		GENMASK(27, 25)
++#endif
++
+ #define MTK_FOE_IB1_STATE		GENMASK(29, 28)
+ #define MTK_FOE_IB1_UDP			BIT(30)
+ #define MTK_FOE_IB1_STATIC		BIT(31)
+@@ -44,24 +47,42 @@ enum {
+ 	MTK_PPE_PKT_TYPE_IPV6_6RD = 7,
+ };
+ 
++#if defined(CONFIG_MEDIATEK_NETSYS_V2)
++#define MTK_FOE_IB2_QID			GENMASK(6, 0)
++#define MTK_FOE_IB2_PORT_MG		BIT(7)
++#define MTK_FOE_IB2_PSE_QOS		BIT(8)
++#define MTK_FOE_IB2_DEST_PORT		GENMASK(12, 9)
++#define MTK_FOE_IB2_MULTICAST		BIT(13)
++#define MTK_FOE_IB2_MIB_CNT		BIT(15)
++#define MTK_FOE_IB2_RX_IDX		GENMASK(18, 17)
++#define MTK_FOE_IB2_WDMA_WINFO		BIT(19)
++#define MTK_FOE_IB2_PORT_AG		GENMASK(23, 20)
++#else
+ #define MTK_FOE_IB2_QID			GENMASK(3, 0)
+ #define MTK_FOE_IB2_PSE_QOS		BIT(4)
+ #define MTK_FOE_IB2_DEST_PORT		GENMASK(7, 5)
+ #define MTK_FOE_IB2_MULTICAST		BIT(8)
+ 
+ #define MTK_FOE_IB2_WDMA_QID2		GENMASK(13, 12)
++#define MTK_FOE_IB2_MIB_CNT		BIT(15)
+ #define MTK_FOE_IB2_WDMA_DEVIDX		BIT(16)
+ #define MTK_FOE_IB2_WDMA_WINFO		BIT(17)
+ 
+ #define MTK_FOE_IB2_PORT_MG		GENMASK(17, 12)
+ 
+ #define MTK_FOE_IB2_PORT_AG		GENMASK(23, 18)
++#endif
+ 
+ #define MTK_FOE_IB2_DSCP		GENMASK(31, 24)
+ 
++#if defined(CONFIG_MEDIATEK_NETSYS_V2)
++#define MTK_FOE_WINFO_BSS		GENMASK(5, 0)
++#define MTK_FOE_WINFO_WCID		GENMASK(15, 6)
++#else
+ #define MTK_FOE_VLAN2_WINFO_BSS		GENMASK(5, 0)
+ #define MTK_FOE_VLAN2_WINFO_WCID	GENMASK(13, 6)
+ #define MTK_FOE_VLAN2_WINFO_RING	GENMASK(15, 14)
++#endif
+ 
+ enum {
+ 	MTK_FOE_STATE_INVALID,
+@@ -83,6 +81,11 @@ struct mtk_foe_mac_info {
+ 
+ 	u16 pppoe_id;
+ 	u16 src_mac_lo;
++
++#if defined(CONFIG_MEDIATEK_NETSYS_V2)
++	u16 minfo;
++	u16 winfo;
++#endif
+ };
+ 
+ /* software-only entry type */
+@@ -200,7 +205,11 @@ struct mtk_foe_entry {
+ 		struct mtk_foe_ipv4_dslite dslite;
+ 		struct mtk_foe_ipv6 ipv6;
+ 		struct mtk_foe_ipv6_6rd ipv6_6rd;
++#if defined(CONFIG_MEDIATEK_NETSYS_V2)
++		u32 data[23];
++#else
+ 		u32 data[19];
++#endif
+ 	};
+ };
+ 
+diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+index d4a012608..5a4201447 100644
+--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+@@ -192,7 +192,15 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe,
+ 	if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) {
+ 		mtk_foe_entry_set_wdma(foe, info.wdma_idx, info.queue, info.bss,
+ 				       info.wcid);
+ 		pse_port = PSE_PPE0_PORT;
++#if defined(CONFIG_MEDIATEK_NETSYS_V2)
++		if (info.wdma_idx == 0)
++			pse_port = PSE_WDMA0_PORT;
++		else if (info.wdma_idx == 1)
++			pse_port = PSE_WDMA1_PORT;
++		else
++			return -EOPNOTSUPP;
++#endif
+ 		*wed_index = info.wdma_idx;
+ 		goto out;
+ 	}
+diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
+index 0c45ea090..d319f1861 100644
+--- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
++++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
+@@ -21,6 +21,9 @@
+ #define MTK_PPE_GLO_CFG_BUSY			BIT(31)
+ 
+ #define MTK_PPE_FLOW_CFG			0x204
++#define MTK_PPE_MD_TOAP_BYP_CRSN0		BIT(1)
++#define MTK_PPE_MD_TOAP_BYP_CRSN1		BIT(2)
++#define MTK_PPE_MD_TOAP_BYP_CRSN2		BIT(3)
+ #define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG		BIT(6)
+ #define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG		BIT(7)
+ #define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE		BIT(8)
+@@ -35,6 +38,8 @@
+ #define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL	BIT(18)
+ #define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY	BIT(19)
+ #define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY	BIT(20)
++#define MTK_PPE_FLOW_CFG_IPV4_MAPE_EN		BIT(21)
++#define MTK_PPE_FLOW_CFG_IPV4_MAPT_EN		BIT(22)
+ 
+ #define MTK_PPE_IP_PROTO_CHK			0x208
+ #define MTK_PPE_IP_PROTO_CHK_IPV4		GENMASK(15, 0)
+@@ -54,6 +59,7 @@
+ #define MTK_PPE_TB_CFG_HASH_MODE		GENMASK(15, 14)
+ #define MTK_PPE_TB_CFG_SCAN_MODE		GENMASK(17, 16)
+ #define MTK_PPE_TB_CFG_HASH_DEBUG		GENMASK(19, 18)
++#define MTK_PPE_TB_CFG_INFO_SEL			BIT(20)
+ 
+ enum {
+ 	MTK_PPE_SCAN_MODE_DISABLED,
+@@ -111,6 +117,8 @@ enum {
+ 
+ #define MTK_PPE_DEFAULT_CPU_PORT		0x248
+ #define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n)	(GENMASK(2, 0) << ((_n) * 4))
++#define MTK_PPE_DEFAULT_CPU_PORT1		0x24C
++#define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n)	(GENMASK(2, 0) << ((_n) * 4))
+ 
+ #define MTK_PPE_MTU_DROP			0x308
+ 
+@@ -141,4 +149,6 @@ enum {
+ #define MTK_PPE_MIB_CACHE_CTL_EN		BIT(0)
+ #define MTK_PPE_MIB_CACHE_CTL_FLUSH		BIT(2)
+ 
++#define MTK_PPE_SBW_CTRL			0x374
++
+ #endif
+-- 
+2.18.0
+