commit ee39bcf8415e71c4a91654caddd8853d56384514
author developer <developer@mediatek.com> Fri Jun 16 08:03:30 2023 +0800
committer developer <developer@mediatek.com> Fri Jun 16 09:24:59 2023 +0800
tree adf6d20ae3b92f93a32c49fda10cb76fd297f3ab
parent ebf63e2eff35cef976204de3c062571acd0a2f07

[][MAC80211][hnat][Revert Flowblock framework patch]

[Description]
Rollback and revert commit of "Sync Flowblock framework to the OpenWRT_trunk_20230525 patch"
Side effect of uplink traffic only with 2~3Gbps

[Release-log]
N/A

Change-Id: I4b1d5a3d543cfafd2f0282ee6ad33329f2fd7c9d
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7637426

autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3004-dts-mt7986-wed-changes.patch

diff --git a/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3004-dts-mt7986-wed-changes.patch b/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3004-dts-mt7986-wed-changes.patch
new file mode 100755
index 0000000..3b965ac
--- /dev/null
+++ b/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3004-dts-mt7986-wed-changes.patch
@@ -0,0 +1,123 @@
+From b83743c16da6fa4da206df3e5a1a9c29485bb613 Mon Sep 17 00:00:00 2001
+From: Bo Jiao <Bo.Jiao@mediatek.com>
+Date: Wed, 22 Jun 2022 16:36:42 +0800
+Subject: [PATCH 3/8] 9992-dts-mt7986-wed-changes
+
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 33 ++++++++---------------
+ arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 33 ++++++++---------------
+ 2 files changed, 22 insertions(+), 44 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+index ba27b95f5..7f78de6b9 100644
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -58,32 +58,20 @@
+ 		};
+ 	};
+ 
+-	wed: wed@15010000 {
+-		compatible = "mediatek,wed";
+-		wed_num = <2>;
+-		/* add this property for wed get the pci slot number. */
+-		pci_slot_map = <0>, <1>;
+-		reg = <0 0x15010000 0 0x1000>,
+-		      <0 0x15011000 0 0x1000>;
++	wed0: wed@15010000 {
++		compatible = "mediatek,mt7986-wed",
++			     "syscon";
++		reg = <0 0x15010000 0 0x1000>;
+ 		interrupt-parent = <&gic>;
+-		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
++		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ 	};
+ 
+-	wed2: wed2@15011000 {
+-		compatible = "mediatek,wed2";
+-		wed_num = <2>;
+-		reg = <0 0x15010000 0 0x1000>,
+-		      <0 0x15011000 0 0x1000>;
++	wed1: wed@15011000 {
++		compatible = "mediatek,mt7986-wed",
++			     "syscon";
++		reg = <0 0x15011000 0 0x1000>;
+ 		interrupt-parent = <&gic>;
+-		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+-	};
+-
+-	wdma: wdma@15104800 {
+-		compatible = "mediatek,wed-wdma";
+-		reg = <0 0x15104800 0 0x400>,
+-		      <0 0x15104c00 0 0x400>;
++		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ 	};
+ 
+ 	ap2woccif: ap2woccif@151A5000 {
+@@ -490,6 +478,7 @@
+ 					 <&topckgen CK_TOP_CB_SGM_325M>;
+                 mediatek,ethsys = <&ethsys>;
+ 		mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
++		mediatek,wed = <&wed0>, <&wed1>;
+                 #reset-cells = <1>;
+                 #address-cells = <1>;
+                 #size-cells = <0>;
+diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
+index 523d585cb..0e5f116a2 100644
+--- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
+@@ -58,32 +58,20 @@
+ 		};
+ 	};
+ 
+-	wed: wed@15010000 {
+-		compatible = "mediatek,wed";
+-		wed_num = <2>;
+-		/* add this property for wed get the pci slot number. */
+-		pci_slot_map = <0>, <1>;
+-		reg = <0 0x15010000 0 0x1000>,
+-		      <0 0x15011000 0 0x1000>;
++	wed0: wed@15010000 {
++		compatible = "mediatek,mt7986-wed",
++			     "syscon";
++		reg = <0 0x15010000 0 0x1000>;
+ 		interrupt-parent = <&gic>;
+-		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
++		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ 	};
+ 
+-	wed2: wed2@15011000 {
+-		compatible = "mediatek,wed2";
+-		wed_num = <2>;
+-		reg = <0 0x15010000 0 0x1000>,
+-		      <0 0x15011000 0 0x1000>;
++	wed1: wed@15011000 {
++		compatible = "mediatek,mt7986-wed",
++			     "syscon";
++		reg = <0 0x15011000 0 0x1000>;
+ 		interrupt-parent = <&gic>;
+-		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+-	};
+-
+-	wdma: wdma@15104800 {
+-		compatible = "mediatek,wed-wdma";
+-		reg = <0 0x15104800 0 0x400>,
+-		      <0 0x15104c00 0 0x400>;
++		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ 	};
+ 
+ 	ap2woccif: ap2woccif@151A5000 {
+@@ -405,6 +393,7 @@
+ 					 <&topckgen CK_TOP_CB_SGM_325M>;
+                 mediatek,ethsys = <&ethsys>;
+ 		mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
++		mediatek,wed = <&wed0>, <&wed1>;
+                 #reset-cells = <1>;
+                 #address-cells = <1>;
+                 #size-cells = <0>;
+-- 
+2.18.0
+