[][Change mt7981 eip97 and audio to enable clock by its own dts node]
[Description]
Change mt7981 eip97 and audio to enable clock by its own dts node
[Release-log]
Pass tcrypt tests for EIP-97 and external loopback for SLIC
Change-Id: I6ff4a46767f0e763245c59ede3cca544f737eb79
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5324274
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi
index dd70a56..ecece3d 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi
@@ -74,11 +74,11 @@
<&infracfg_ao CK_INFRA_PWM1_CK>,
<&infracfg_ao CK_INFRA_PWM2_CK>,
<&infracfg_ao CK_INFRA_CQ_DMA_CK>,
- <&infracfg_ao CK_INFRA_AUD_BUS_CK>,
- <&infracfg_ao CK_INFRA_AUD_26M_CK>,
- <&infracfg_ao CK_INFRA_AUD_L_CK>,
- <&infracfg_ao CK_INFRA_AUD_AUD_CK>,
- <&infracfg_ao CK_INFRA_AUD_EG2_CK>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
<&infracfg_ao CK_INFRA_DRAMC_26M_CK>,
<&infracfg_ao CK_INFRA_DBG_CK>,
<&infracfg_ao CK_INFRA_AP_DMA_CK>,
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-spim-nand-rfb.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-spim-nand-rfb.dts
index 0d68660..81f7f76 100755
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-spim-nand-rfb.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-spim-nand-rfb.dts
@@ -54,6 +54,30 @@
};
};
};
+
+ sound {
+ compatible = "mediatek,mt79xx-si3218x-machine";
+ mediatek,platform = <&afe>;
+ mediatek,ext-codec = <&proslic_spi>;
+ status = "okay";
+ };
+};
+
+&afe {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcm_pins>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_pins>;
+ status = "okay";
+
+ wm8960: wm8960@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ };
};
&uart0 {
@@ -172,7 +196,19 @@
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins>;
- status = "disabled";
+ status = "okay";
+
+ proslic_spi: proslic_spi@0 {
+ compatible = "silabs,proslic_spi";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ spi-cpha = <1>;
+ spi-cpol = <1>;
+ channel_count = <1>;
+ debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
+ reset_gpio = <&pio 15 0>;
+ ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
+ };
};
&pio {
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi
index 2d01b7b..49add10 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi
@@ -274,6 +274,20 @@
};
};
+ crypto: crypto@10320000 {
+ compatible = "inside-secure,safexcel-eip97";
+ reg = <0 0x10320000 0 0x40000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ring0", "ring1", "ring2", "ring3";
+ clocks = <&topckgen CK_TOP_EIP97B>;
+ clock-names = "top_eip97_ck";
+ assigned-clocks = <&topckgen CK_TOP_EIP97B_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
+ };
+
pio: pinctrl@11d00000 {
compatible = "mediatek,mt7981-pinctrl";
reg = <0 0x11d00000 0 0x1000>,
@@ -538,5 +552,30 @@
reg = <0x8dc 0x10>;
};
};
+
+ afe: audio-controller@11210000 {
+ compatible = "mediatek,mt79xx-audio";
+ reg = <0 0x11210000 0 0x9000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg_ao CK_INFRA_AUD_BUS_CK>,
+ <&infracfg_ao CK_INFRA_AUD_26M_CK>,
+ <&infracfg_ao CK_INFRA_AUD_L_CK>,
+ <&infracfg_ao CK_INFRA_AUD_AUD_CK>,
+ <&infracfg_ao CK_INFRA_AUD_EG2_CK>;
+ clock-names = "aud_bus_ck",
+ "aud_26m_ck",
+ "aud_l_ck",
+ "aud_aud_ck",
+ "aud_eg2_ck";
+ assigned-clocks = <&topckgen CK_TOP_AUD_SEL>,
+ <&topckgen CK_TOP_A1SYS_SEL>,
+ <&topckgen CK_TOP_AUD_L_SEL>,
+ <&topckgen CK_TOP_A_TUNER_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+ <&topckgen CK_TOP_CB_CKSQ_40M>,
+ <&topckgen CK_TOP_CB_CKSQ_40M>,
+ <&topckgen CK_TOP_CB_CKSQ_40M>;
+ status = "disabled";
+ };
};
#include "mt7981-clkitg.dtsi"