[][Enable PCIe Gen3 driver for mt7986]
[Description]
Change PCIe node, and enable PCIe Gen3 driver for mt7986.
[Release-log]
N/A
Change-Id: I0c0f39f23ad8fcfef86bb0735418f11587af9e41
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/4706613
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986-clkitg.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986-clkitg.dtsi
index c89e112..dd04a54 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986-clkitg.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986-clkitg.dtsi
@@ -32,7 +32,7 @@
<&infracfg CK_INFRA_PWM>,
<&infracfg CK_INFRA_66M_MCK>,
<&infracfg CK_INFRA_CK_F32K>,
- <&infracfg CK_INFRA_PCIE_CK>,
+ <&clk40m>,
<&infracfg CK_INFRA_PWM_BCK>,
<&infracfg CK_INFRA_PWM_CK1>,
<&infracfg CK_INFRA_PWM_CK2>,
@@ -58,7 +58,7 @@
<&infracfg CK_INFRA_USB_SYS_CK>,
<&infracfg CK_INFRA_USB_CK>,
<&infracfg CK_INFRA_USB_XHCI_CK>,
- <&infracfg CK_INFRA_PCIE_GFMUX_TL_O_PRE>,
+ <&clk40m>,
<&infracfg CK_INFRA_F26M_CK0>,
<&infracfg_ao CK_INFRA_UART0_SEL>,
<&infracfg_ao CK_INFRA_UART1_SEL>,
@@ -68,7 +68,7 @@
<&infracfg_ao CK_INFRA_PWM1_SEL>,
<&infracfg_ao CK_INFRA_PWM2_SEL>,
<&infracfg_ao CK_INFRA_PWM_BSEL>,
- <&infracfg_ao CK_INFRA_PCIE_SEL>,
+ <&clk40m>,
<&infracfg_ao CK_INFRA_GPT_STA>,
<&infracfg_ao CK_INFRA_PWM_HCK>,
<&infracfg_ao CK_INFRA_PWM_STA>,
@@ -110,9 +110,9 @@
<&infracfg_ao CK_INFRA_IUSB_66M_CK>,
<&infracfg_ao CK_INFRA_IUSB_SYS_CK>,
<&infracfg_ao CK_INFRA_IUSB_CK>,
- <&infracfg_ao CK_INFRA_IPCIE_CK>,
- <&infracfg_ao CK_INFRA_IPCIER_CK>,
- <&infracfg_ao CK_INFRA_IPCIEB_CK>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
<&infracfg_ao CK_INFRA_TRNG_CK>,
<&topckgen CK_TOP_CB_M_416M>,
<&topckgen CK_TOP_CB_M_D2>,
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
index 49bb3f5..a590e42 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
@@ -345,6 +345,12 @@
status = "okay";
};
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
+};
+
&pio {
wifi_led_pins: wifi_led-pins-1-2 {
mux {
@@ -367,6 +373,13 @@
};
};
+ pcie0_pins: pcie0-pins-9-10-41 {
+ mux {
+ function = "pcie";
+ groups = "pcie_clk", "pcie_wake", "pcie_pereset";
+ };
+ };
+
jtag_pins: jtag-pins-11-to-14 {
mux {
function = "jtag";
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index 9450a89..0f58c05 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -400,35 +400,34 @@
nvmem-cell-names = "calibration-data";
};
- pcie: pcie@11280000 {
+ pcie0: pcie@11280000 {
compatible = "mediatek,mt7986-pcie";
- device_type = "pci";
reg = <0 0x11280000 0 0x5000>;
- reg-names = "port0";
+ reg-names = "pcie-mac";
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000
0x0 0x20000000 0 0x10000000>;
+ status = "disabled";
- pcie0: pcie@0,0 {
- device_type = "pci";
- reg = <0x0000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
+ clocks = <&infracfg_ao CK_INFRA_PCIE_SEL>,
+ <&infracfg_ao CK_INFRA_IPCIE_CK>,
+ <&infracfg_ao CK_INFRA_IPCIE_PIPE_CK>,
+ <&infracfg_ao CK_INFRA_IPCIER_CK>,
+ <&infracfg_ao CK_INFRA_IPCIEB_CK>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
- <0 0 0 2 &pcie_intc0 1>,
- <0 0 0 3 &pcie_intc0 2>,
- <0 0 0 4 &pcie_intc0 3>;
- pcie_intc0: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
};
};