| Index: linux-5.4.246/drivers/mtd/nand/spi/gigadevice.c |
| =================================================================== |
| --- linux-5.4.246.orig/drivers/mtd/nand/spi/gigadevice.c |
| +++ linux-5.4.246/drivers/mtd/nand/spi/gigadevice.c |
| @@ -13,7 +13,10 @@ |
| #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4) |
| #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4) |
| |
| -#define GD5FXGQ4UEXXG_REG_STATUS2 0xf0 |
| +#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS (1 << 4) |
| +#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS (3 << 4) |
| + |
| +#define GD5FXGQXXEXXG_REG_STATUS2 0xf0 |
| |
| #define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4) |
| #define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4) |
| @@ -36,6 +39,22 @@ static SPINAND_OP_VARIANTS(read_cache_va |
| SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0)); |
| |
| +static SPINAND_OP_VARIANTS(read_cache_variants_1gq5, |
| + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| + |
| +static SPINAND_OP_VARIANTS(read_cache_variants_2gq5, |
| + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| + |
| static SPINAND_OP_VARIANTS(write_cache_variants, |
| SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), |
| SPINAND_PROG_LOAD(true, 0, NULL, 0)); |
| @@ -102,7 +121,7 @@ static int gd5fxgq4xa_ecc_get_status(str |
| return -EINVAL; |
| } |
| |
| -static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, |
| +static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, |
| struct mtd_oob_region *region) |
| { |
| if (section) |
| @@ -114,7 +133,7 @@ static int gd5fxgq4_variant2_ooblayout_e |
| return 0; |
| } |
| |
| -static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section, |
| +static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section, |
| struct mtd_oob_region *region) |
| { |
| if (section) |
| @@ -127,16 +146,46 @@ static int gd5fxgq4_variant2_ooblayout_f |
| return 0; |
| } |
| |
| -static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = { |
| - .ecc = gd5fxgq4_variant2_ooblayout_ecc, |
| - .free = gd5fxgq4_variant2_ooblayout_free, |
| +/* Valid for Q4/Q5 and Q6 (untested) devices */ |
| +static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = { |
| + .ecc = gd5fxgqx_variant2_ooblayout_ecc, |
| + .free = gd5fxgqx_variant2_ooblayout_free, |
| +}; |
| + |
| +static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section, |
| + struct mtd_oob_region *oobregion) |
| +{ |
| + if (section) |
| + return -ERANGE; |
| + |
| + oobregion->offset = 128; |
| + oobregion->length = 128; |
| + |
| + return 0; |
| +} |
| + |
| +static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section, |
| + struct mtd_oob_region *oobregion) |
| +{ |
| + if (section) |
| + return -ERANGE; |
| + |
| + oobregion->offset = 1; |
| + oobregion->length = 127; |
| + |
| + return 0; |
| +} |
| + |
| +static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = { |
| + .ecc = gd5fxgq4xc_ooblayout_256_ecc, |
| + .free = gd5fxgq4xc_ooblayout_256_free, |
| }; |
| |
| static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, |
| u8 status) |
| { |
| u8 status2; |
| - struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2, |
| + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2, |
| &status2); |
| int ret; |
| |
| @@ -174,6 +223,43 @@ static int gd5fxgq4uexxg_ecc_get_status( |
| return -EINVAL; |
| } |
| |
| +static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand, |
| + u8 status) |
| +{ |
| + u8 status2; |
| + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2, |
| + &status2); |
| + int ret; |
| + |
| + switch (status & STATUS_ECC_MASK) { |
| + case STATUS_ECC_NO_BITFLIPS: |
| + return 0; |
| + |
| + case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS: |
| + /* |
| + * Read status2 register to determine a more fine grained |
| + * bit error status |
| + */ |
| + ret = spi_mem_exec_op(spinand->spimem, &op); |
| + if (ret) |
| + return ret; |
| + |
| + /* |
| + * 1 ... 4 bits are flipped (and corrected) |
| + */ |
| + /* bits sorted this way (1...0): ECCSE1, ECCSE0 */ |
| + return ((status2 & STATUS_ECC_MASK) >> 4) + 1; |
| + |
| + case STATUS_ECC_UNCOR_ERROR: |
| + return -EBADMSG; |
| + |
| + default: |
| + break; |
| + } |
| + |
| + return -EINVAL; |
| +} |
| + |
| static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand, |
| u8 status) |
| { |
| @@ -195,7 +281,8 @@ static int gd5fxgq4ufxxg_ecc_get_status( |
| } |
| |
| static const struct spinand_info gigadevice_spinand_table[] = { |
| - SPINAND_INFO("GD5F1GQ4xA", 0xF1, |
| + SPINAND_INFO("GD5F1GQ4xA", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1), |
| NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| @@ -204,7 +291,8 @@ static const struct spinand_info gigadev |
| SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, |
| gd5fxgq4xa_ecc_get_status)), |
| - SPINAND_INFO("GD5F2GQ4xA", 0xF2, |
| + SPINAND_INFO("GD5F2GQ4xA", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2), |
| NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| @@ -213,7 +301,8 @@ static const struct spinand_info gigadev |
| SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, |
| gd5fxgq4xa_ecc_get_status)), |
| - SPINAND_INFO("GD5F4GQ4xA", 0xF4, |
| + SPINAND_INFO("GD5F4GQ4xA", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4), |
| NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| @@ -222,59 +311,205 @@ static const struct spinand_info gigadev |
| SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, |
| gd5fxgq4xa_ecc_get_status)), |
| - SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, |
| + SPINAND_INFO("GD5F4GQ4RC", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xa4, 0x68), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops, |
| + gd5fxgq4ufxxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GQ4UC", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb4, 0x68), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops, |
| + gd5fxgq4ufxxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GQ4UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GQ4RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1), |
| NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |
| - SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GQ4UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| gd5fxgq4uexxg_ecc_get_status)), |
| - SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148, |
| + SPINAND_INFO("GD5F2GQ4RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GQ4UFxxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48), |
| NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |
| - SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| gd5fxgq4ufxxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GQ5UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GQ5RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GQ5UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GQ5RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GQ6UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GQ6RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GM7UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GM7RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GM7UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GM7RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GM8UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95), |
| + NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GM8RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85), |
| + NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| }; |
| |
| -static int gigadevice_spinand_detect(struct spinand_device *spinand) |
| -{ |
| - u8 *id = spinand->id.data; |
| - u16 did; |
| - int ret; |
| - |
| - /* |
| - * Earlier GDF5-series devices (A,E) return [0][MID][DID] |
| - * Later (F) devices return [MID][DID1][DID2] |
| - */ |
| - |
| - if (id[0] == SPINAND_MFR_GIGADEVICE) |
| - did = (id[1] << 8) + id[2]; |
| - else if (id[0] == 0 && id[1] == SPINAND_MFR_GIGADEVICE) |
| - did = id[2]; |
| - else |
| - return 0; |
| - |
| - ret = spinand_match_and_init(spinand, gigadevice_spinand_table, |
| - ARRAY_SIZE(gigadevice_spinand_table), |
| - did); |
| - if (ret) |
| - return ret; |
| - |
| - return 1; |
| -} |
| - |
| static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { |
| - .detect = gigadevice_spinand_detect, |
| }; |
| |
| const struct spinand_manufacturer gigadevice_spinand_manufacturer = { |
| .id = SPINAND_MFR_GIGADEVICE, |
| .name = "GigaDevice", |
| + .chips = gigadevice_spinand_table, |
| + .nchips = ARRAY_SIZE(gigadevice_spinand_table), |
| .ops = &gigadevice_spinand_manuf_ops, |
| }; |