diff --git a/21.02/files/target/linux/generic/backport-5.4/999-1410-mtd-spinand-gigadevice-Support-for-modify-GD-Serial-NAND-from-v6-4-9.patch b/21.02/files/target/linux/generic/backport-5.4/999-1410-mtd-spinand-gigadevice-Support-for-modify-GD-Serial-NAND-from-v6-4-9.patch
deleted file mode 100644
index 1365854..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-1410-mtd-spinand-gigadevice-Support-for-modify-GD-Serial-NAND-from-v6-4-9.patch
+++ /dev/null
@@ -1,420 +0,0 @@
-Index: linux-5.4.246/drivers/mtd/nand/spi/gigadevice.c
-===================================================================
---- linux-5.4.246.orig/drivers/mtd/nand/spi/gigadevice.c
-+++ linux-5.4.246/drivers/mtd/nand/spi/gigadevice.c
-@@ -13,7 +13,10 @@
- #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS	(1 << 4)
- #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS	(3 << 4)
- 
--#define GD5FXGQ4UEXXG_REG_STATUS2		0xf0
-+#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS	(1 << 4)
-+#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS	(3 << 4)
-+
-+#define GD5FXGQXXEXXG_REG_STATUS2		0xf0
- 
- #define GD5FXGQ4UXFXXG_STATUS_ECC_MASK		(7 << 4)
- #define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS	(0 << 4)
-@@ -36,6 +39,22 @@ static SPINAND_OP_VARIANTS(read_cache_va
- 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
- 
-+static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
-+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
-+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-+
- static SPINAND_OP_VARIANTS(write_cache_variants,
- 		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
- 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
-@@ -102,7 +121,7 @@ static int gd5fxgq4xa_ecc_get_status(str
- 	return -EINVAL;
- }
- 
--static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
-+static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
- 				       struct mtd_oob_region *region)
- {
- 	if (section)
-@@ -114,7 +133,7 @@ static int gd5fxgq4_variant2_ooblayout_e
- 	return 0;
- }
- 
--static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section,
-+static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section,
- 					struct mtd_oob_region *region)
- {
- 	if (section)
-@@ -127,16 +146,46 @@ static int gd5fxgq4_variant2_ooblayout_f
- 	return 0;
- }
- 
--static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = {
--	.ecc = gd5fxgq4_variant2_ooblayout_ecc,
--	.free = gd5fxgq4_variant2_ooblayout_free,
-+/* Valid for Q4/Q5 and Q6 (untested) devices */
-+static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = {
-+	.ecc = gd5fxgqx_variant2_ooblayout_ecc,
-+	.free = gd5fxgqx_variant2_ooblayout_free,
-+};
-+
-+static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,
-+					struct mtd_oob_region *oobregion)
-+{
-+	if (section)
-+		return -ERANGE;
-+
-+	oobregion->offset = 128;
-+	oobregion->length = 128;
-+
-+	return 0;
-+}
-+
-+static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section,
-+					 struct mtd_oob_region *oobregion)
-+{
-+	if (section)
-+		return -ERANGE;
-+
-+	oobregion->offset = 1;
-+	oobregion->length = 127;
-+
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = {
-+	.ecc = gd5fxgq4xc_ooblayout_256_ecc,
-+	.free = gd5fxgq4xc_ooblayout_256_free,
- };
- 
- static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
- 					u8 status)
- {
- 	u8 status2;
--	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2,
-+	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
- 						      &status2);
- 	int ret;
- 
-@@ -174,6 +223,43 @@ static int gd5fxgq4uexxg_ecc_get_status(
- 	return -EINVAL;
- }
- 
-+static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand,
-+					u8 status)
-+{
-+	u8 status2;
-+	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
-+						      &status2);
-+	int ret;
-+
-+	switch (status & STATUS_ECC_MASK) {
-+	case STATUS_ECC_NO_BITFLIPS:
-+		return 0;
-+
-+	case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS:
-+		/*
-+		 * Read status2 register to determine a more fine grained
-+		 * bit error status
-+		 */
-+		ret = spi_mem_exec_op(spinand->spimem, &op);
-+		if (ret)
-+			return ret;
-+
-+		/*
-+		 * 1 ... 4 bits are flipped (and corrected)
-+		 */
-+		/* bits sorted this way (1...0): ECCSE1, ECCSE0 */
-+		return ((status2 & STATUS_ECC_MASK) >> 4) + 1;
-+
-+	case STATUS_ECC_UNCOR_ERROR:
-+		return -EBADMSG;
-+
-+	default:
-+		break;
-+	}
-+
-+	return -EINVAL;
-+}
-+
- static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
- 					u8 status)
- {
-@@ -195,7 +281,8 @@ static int gd5fxgq4ufxxg_ecc_get_status(
- }
- 
- static const struct spinand_info gigadevice_spinand_table[] = {
--	SPINAND_INFO("GD5F1GQ4xA", 0xF1,
-+	SPINAND_INFO("GD5F1GQ4xA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -204,7 +291,8 @@ static const struct spinand_info gigadev
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
- 				     gd5fxgq4xa_ecc_get_status)),
--	SPINAND_INFO("GD5F2GQ4xA", 0xF2,
-+	SPINAND_INFO("GD5F2GQ4xA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2),
- 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -213,7 +301,8 @@ static const struct spinand_info gigadev
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
- 				     gd5fxgq4xa_ecc_get_status)),
--	SPINAND_INFO("GD5F4GQ4xA", 0xF4,
-+	SPINAND_INFO("GD5F4GQ4xA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4),
- 		     NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -222,59 +311,205 @@ static const struct spinand_info gigadev
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
- 				     gd5fxgq4xa_ecc_get_status)),
--	SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
-+	SPINAND_INFO("GD5F4GQ4RC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xa4, 0x68),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
-+				     gd5fxgq4ufxxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F4GQ4UC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb4, 0x68),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
-+				     gd5fxgq4ufxxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GQ4UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GQ4RExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     SPINAND_HAS_QE_BIT,
--		     SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F2GQ4UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
- 				     gd5fxgq4uexxg_ecc_get_status)),
--	SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148,
-+	SPINAND_INFO("GD5F2GQ4RExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GQ4UFxxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     SPINAND_HAS_QE_BIT,
--		     SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
- 				     gd5fxgq4ufxxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GQ5UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq5xexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GQ5RExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq5xexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F2GQ5UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq5xexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F2GQ5RExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq5xexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F4GQ6UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq5xexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F4GQ6RExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq5xexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GM7UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GM7RExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F2GM7UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F2GM7RExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F4GM8UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F4GM8RExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
- };
- 
--static int gigadevice_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	u16 did;
--	int ret;
--
--	/*
--	 * Earlier GDF5-series devices (A,E) return [0][MID][DID]
--	 * Later (F) devices return [MID][DID1][DID2]
--	 */
--
--	if (id[0] == SPINAND_MFR_GIGADEVICE)
--		did = (id[1] << 8) + id[2];
--	else if (id[0] == 0 && id[1] == SPINAND_MFR_GIGADEVICE)
--		did = id[2];
--	else
--		return 0;
--
--	ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
--				     ARRAY_SIZE(gigadevice_spinand_table),
--				     did);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
--	.detect = gigadevice_spinand_detect,
- };
- 
- const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
- 	.id = SPINAND_MFR_GIGADEVICE,
- 	.name = "GigaDevice",
-+	.chips = gigadevice_spinand_table,
-+	.nchips = ARRAY_SIZE(gigadevice_spinand_table),
- 	.ops = &gigadevice_spinand_manuf_ops,
- };
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2310-v5.7-mtd-nand-spi-rework-detect-procedure-for-different-read-id-op.patch b/21.02/files/target/linux/generic/backport-5.4/999-2310-v5.7-mtd-nand-spi-rework-detect-procedure-for-different-read-id-op.patch
deleted file mode 100644
index a8c62fa..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2310-v5.7-mtd-nand-spi-rework-detect-procedure-for-different-read-id-op.patch
+++ /dev/null
@@ -1,647 +0,0 @@
-From 0aeb63ff705a42b9140cad179ebe7f5fc54d285c Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:09 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2310-v5.7-mtd-nand-spi-rework-detect-procedure-for-different-read-id-op.patch]
-
----
- drivers/mtd/nand/spi/core.c       | 86 ++++++++++++++++++++++---------
- drivers/mtd/nand/spi/macronix.c   | 30 +++--------
- drivers/mtd/nand/spi/micron.c     | 26 ++--------
- drivers/mtd/nand/spi/paragon.c    | 28 +++-------
- drivers/mtd/nand/spi/toshiba.c    | 42 +++++----------
- drivers/mtd/nand/spi/winbond.c    | 34 +++---------
- include/linux/mtd/spinand.h       | 66 ++++++++++++++++--------
- 8 files changed, 155 insertions(+), 202 deletions(-)
-
-diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
-index 55e636efc..9f5f95ff7 100644
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -16,6 +16,7 @@
- #include <linux/mtd/spinand.h>
- #include <linux/of.h>
- #include <linux/slab.h>
-+#include <linux/string.h>
- #include <linux/spi/spi.h>
- #include <linux/spi/spi-mem.h>
- 
-@@ -370,10 +371,11 @@ out:
- 	return status & STATUS_BUSY ? -ETIMEDOUT : 0;
- }
- 
--static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
-+static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr,
-+			      u8 ndummy, u8 *buf)
- {
--	struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
--						 SPINAND_MAX_ID_LEN);
-+	struct spi_mem_op op = SPINAND_READID_OP(
-+		naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
- 	int ret;
- 
- 	ret = spi_mem_exec_op(spinand->spimem, &op);
-@@ -760,24 +762,62 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = {
- 	&winbond_spinand_manufacturer,
- };
- 
--static int spinand_manufacturer_detect(struct spinand_device *spinand)
-+static int spinand_manufacturer_match(struct spinand_device *spinand,
-+				      enum spinand_readid_method rdid_method)
- {
-+	u8 *id = spinand->id.data;
- 	unsigned int i;
- 	int ret;
- 
- 	for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
--		ret = spinand_manufacturers[i]->ops->detect(spinand);
--		if (ret > 0) {
--			spinand->manufacturer = spinand_manufacturers[i];
--			return 0;
--		} else if (ret < 0) {
--			return ret;
--		}
--	}
-+		const struct spinand_manufacturer *manufacturer =
-+			spinand_manufacturers[i];
-+
-+		if (id[0] != manufacturer->id)
-+			continue;
- 
-+		ret = spinand_match_and_init(spinand,
-+					     manufacturer->chips,
-+					     manufacturer->nchips,
-+					     rdid_method);
-+		if (ret < 0)
-+			continue;
-+
-+		spinand->manufacturer = manufacturer;
-+		return 0;
-+	}
- 	return -ENOTSUPP;
- }
- 
-+static int spinand_id_detect(struct spinand_device *spinand)
-+{
-+	u8 *id = spinand->id.data;
-+	int ret;
-+
-+	ret = spinand_read_id_op(spinand, 0, 0, id);
-+	if (ret)
-+		return ret;
-+	ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE);
-+	if (!ret)
-+		return 0;
-+
-+	ret = spinand_read_id_op(spinand, 1, 0, id);
-+	if (ret)
-+		return ret;
-+	ret = spinand_manufacturer_match(spinand,
-+					 SPINAND_READID_METHOD_OPCODE_ADDR);
-+	if (!ret)
-+		return 0;
-+
-+	ret = spinand_read_id_op(spinand, 0, 1, id);
-+	if (ret)
-+		return ret;
-+	ret = spinand_manufacturer_match(spinand,
-+					 SPINAND_READID_METHOD_OPCODE_DUMMY);
-+
-+	return ret;
-+}
-+
- static int spinand_manufacturer_init(struct spinand_device *spinand)
- {
- 	if (spinand->manufacturer->ops->init)
-@@ -833,9 +873,9 @@ spinand_select_op_variant(struct spinand_device *spinand,
-  * @spinand: SPI NAND object
-  * @table: SPI NAND device description table
-  * @table_size: size of the device description table
-+ * @rdid_method: read id method to match
-  *
-- * Should be used by SPI NAND manufacturer drivers when they want to find a
-- * match between a device ID retrieved through the READ_ID command and an
-+ * Match between a device ID retrieved through the READ_ID command and an
-  * entry in the SPI NAND description table. If a match is found, the spinand
-  * object will be initialized with information provided by the matching
-  * spinand_info entry.
-@@ -844,8 +884,10 @@ spinand_select_op_variant(struct spinand_device *spinand,
-  */
- int spinand_match_and_init(struct spinand_device *spinand,
- 			   const struct spinand_info *table,
--			   unsigned int table_size, u16 devid)
-+			   unsigned int table_size,
-+			   enum spinand_readid_method rdid_method)
- {
-+	u8 *id = spinand->id.data;
- 	struct nand_device *nand = spinand_to_nand(spinand);
- 	unsigned int i;
- 
-@@ -853,13 +895,17 @@ int spinand_match_and_init(struct spinand_device *spinand,
- 		const struct spinand_info *info = &table[i];
- 		const struct spi_mem_op *op;
- 
--		if (devid != info->devid)
-+		if (rdid_method != info->devid.method)
-+			continue;
-+
-+		if (memcmp(id + 1, info->devid.id, info->devid.len))
- 			continue;
- 
- 		nand->memorg = table[i].memorg;
- 		nand->eccreq = table[i].eccreq;
- 		spinand->eccinfo = table[i].eccinfo;
- 		spinand->flags = table[i].flags;
-+		spinand->id.len = 1 + table[i].devid.len;
- 		spinand->select_target = table[i].select_target;
- 
- 		op = spinand_select_op_variant(spinand,
-@@ -896,13 +942,7 @@ static int spinand_detect(struct spinand_device *spinand)
- 	if (ret)
- 		return ret;
- 
--	ret = spinand_read_id_op(spinand, spinand->id.data);
--	if (ret)
--		return ret;
--
--	spinand->id.len = SPINAND_MAX_ID_LEN;
--
--	ret = spinand_manufacturer_detect(spinand);
-+	ret = spinand_id_detect(spinand);
- 	if (ret) {
- 		dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN,
- 			spinand->id.data);
-diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
-index 21def3f8f..0f900f3aa 100644
---- a/drivers/mtd/nand/spi/macronix.c
-+++ b/drivers/mtd/nand/spi/macronix.c
-@@ -99,7 +99,8 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand,
- }
- 
- static const struct spinand_info macronix_spinand_table[] = {
--	SPINAND_INFO("MX35LF1GE4AB", 0x12,
-+	SPINAND_INFO("MX35LF1GE4AB",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
- 		     NAND_ECCREQ(4, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -108,7 +109,8 @@ static const struct spinand_info macronix_spinand_table[] = {
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
--	SPINAND_INFO("MX35LF2GE4AB", 0x22,
-+	SPINAND_INFO("MX35LF2GE4AB",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
- 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
- 		     NAND_ECCREQ(4, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -118,33 +120,13 @@ static const struct spinand_info macronix_spinand_table[] = {
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
- };
- 
--static int macronix_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * Macronix SPI NAND read ID needs a dummy byte, so the first byte in
--	 * raw_id is garbage.
--	 */
--	if (id[1] != SPINAND_MFR_MACRONIX)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, macronix_spinand_table,
--				     ARRAY_SIZE(macronix_spinand_table),
--				     id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
--	.detect = macronix_spinand_detect,
- };
- 
- const struct spinand_manufacturer macronix_spinand_manufacturer = {
- 	.id = SPINAND_MFR_MACRONIX,
- 	.name = "Macronix",
-+	.chips = macronix_spinand_table,
-+	.nchips = ARRAY_SIZE(macronix_spinand_table),
- 	.ops = &macronix_spinand_manuf_ops,
- };
-diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
-index 7d7b1f7fc..f56f81325 100644
---- a/drivers/mtd/nand/spi/micron.c
-+++ b/drivers/mtd/nand/spi/micron.c
-@@ -91,7 +91,8 @@ static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
- }
- 
- static const struct spinand_info micron_spinand_table[] = {
--	SPINAND_INFO("MT29F2G01ABAGD", 0x24,
-+	SPINAND_INFO("MT29F2G01ABAGD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -102,32 +103,13 @@ static const struct spinand_info micron_spinand_table[] = {
- 				     mt29f2g01abagd_ecc_get_status)),
- };
- 
--static int micron_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * Micron SPI NAND read ID need a dummy byte,
--	 * so the first byte in raw_id is dummy.
--	 */
--	if (id[1] != SPINAND_MFR_MICRON)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, micron_spinand_table,
--				     ARRAY_SIZE(micron_spinand_table), id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
--	.detect = micron_spinand_detect,
- };
- 
- const struct spinand_manufacturer micron_spinand_manufacturer = {
- 	.id = SPINAND_MFR_MICRON,
- 	.name = "Micron",
-+	.chips = micron_spinand_table,
-+	.nchips = ARRAY_SIZE(micron_spinand_table),
- 	.ops = &micron_spinand_manuf_ops,
- };
-diff --git a/drivers/mtd/nand/spi/paragon.c b/drivers/mtd/nand/spi/paragon.c
-index 52307681c..519ade513 100644
---- a/drivers/mtd/nand/spi/paragon.c
-+++ b/drivers/mtd/nand/spi/paragon.c
-@@ -97,7 +97,8 @@ static const struct mtd_ooblayout_ops pn26g0xa_ooblayout = {
- 
- 
- static const struct spinand_info paragon_spinand_table[] = {
--	SPINAND_INFO("PN26G01A", 0xe1,
-+	SPINAND_INFO("PN26G01A",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe1),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 21, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -106,7 +107,8 @@ static const struct spinand_info paragon_spinand_table[] = {
- 		     0,
- 		     SPINAND_ECCINFO(&pn26g0xa_ooblayout,
- 				     pn26g0xa_ecc_get_status)),
--	SPINAND_INFO("PN26G02A", 0xe2,
-+	SPINAND_INFO("PN26G02A",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 41, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -117,31 +119,13 @@ static const struct spinand_info paragon_spinand_table[] = {
- 				     pn26g0xa_ecc_get_status)),
- };
- 
--static int paragon_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/* Read ID returns [0][MID][DID] */
--
--	if (id[1] != SPINAND_MFR_PARAGON)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, paragon_spinand_table,
--				     ARRAY_SIZE(paragon_spinand_table),
--				     id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static const struct spinand_manufacturer_ops paragon_spinand_manuf_ops = {
--	.detect = paragon_spinand_detect,
- };
- 
- const struct spinand_manufacturer paragon_spinand_manufacturer = {
- 	.id = SPINAND_MFR_PARAGON,
- 	.name = "Paragon",
-+	.chips = paragon_spinand_table,
-+	.nchips = ARRAY_SIZE(paragon_spinand_table),
- 	.ops = &paragon_spinand_manuf_ops,
- };
-diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c
-index 1cb3760ff..35da3c6e9 100644
---- a/drivers/mtd/nand/spi/toshiba.c
-+++ b/drivers/mtd/nand/spi/toshiba.c
-@@ -95,7 +95,8 @@ static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand,
- 
- static const struct spinand_info toshiba_spinand_table[] = {
- 	/* 3.3V 1Gb */
--	SPINAND_INFO("TC58CVG0S3", 0xC2,
-+	SPINAND_INFO("TC58CVG0S3",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -105,7 +106,8 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
- 				     tc58cxgxsx_ecc_get_status)),
- 	/* 3.3V 2Gb */
--	SPINAND_INFO("TC58CVG1S3", 0xCB,
-+	SPINAND_INFO("TC58CVG1S3",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -115,7 +117,8 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
- 				     tc58cxgxsx_ecc_get_status)),
- 	/* 3.3V 4Gb */
--	SPINAND_INFO("TC58CVG2S0", 0xCD,
-+	SPINAND_INFO("TC58CVG2S0",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -125,7 +128,8 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
- 				     tc58cxgxsx_ecc_get_status)),
- 	/* 1.8V 1Gb */
--	SPINAND_INFO("TC58CYG0S3", 0xB2,
-+	SPINAND_INFO("TC58CYG0S3",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -135,7 +139,8 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
- 				     tc58cxgxsx_ecc_get_status)),
- 	/* 1.8V 2Gb */
--	SPINAND_INFO("TC58CYG1S3", 0xBB,
-+	SPINAND_INFO("TC58CYG1S3",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -145,7 +150,8 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
- 				     tc58cxgxsx_ecc_get_status)),
- 	/* 1.8V 4Gb */
--	SPINAND_INFO("TC58CYG2S0", 0xBD,
-+	SPINAND_INFO("TC58CYG2S0",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -156,33 +162,13 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 				     tc58cxgxsx_ecc_get_status)),
- };
- 
--static int toshiba_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * Toshiba SPI NAND read ID needs a dummy byte,
--	 * so the first byte in id is garbage.
--	 */
--	if (id[1] != SPINAND_MFR_TOSHIBA)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, toshiba_spinand_table,
--				     ARRAY_SIZE(toshiba_spinand_table),
--				     id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
--	.detect = toshiba_spinand_detect,
- };
- 
- const struct spinand_manufacturer toshiba_spinand_manufacturer = {
- 	.id = SPINAND_MFR_TOSHIBA,
- 	.name = "Toshiba",
-+	.chips = toshiba_spinand_table,
-+	.nchips = ARRAY_SIZE(toshiba_spinand_table),
- 	.ops = &toshiba_spinand_manuf_ops,
- };
-diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
-index a6c17e0ca..766844283 100644
---- a/drivers/mtd/nand/spi/winbond.c
-+++ b/drivers/mtd/nand/spi/winbond.c
-@@ -75,7 +75,8 @@ static int w25m02gv_select_target(struct spinand_device *spinand,
- }
- 
- static const struct spinand_info winbond_spinand_table[] = {
--	SPINAND_INFO("W25M02GV", 0xAB,
-+	SPINAND_INFO("W25M02GV",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2),
- 		     NAND_ECCREQ(1, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -84,7 +85,8 @@ static const struct spinand_info winbond_spinand_table[] = {
- 		     0,
- 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
- 		     SPINAND_SELECT_TARGET(w25m02gv_select_target)),
--	SPINAND_INFO("W25N01GV", 0xAA,
-+	SPINAND_INFO("W25N01GV",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
- 		     NAND_ECCREQ(1, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -94,31 +96,6 @@ static const struct spinand_info winbond_spinand_table[] = {
- 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
- };
- 
--/**
-- * winbond_spinand_detect - initialize device related part in spinand_device
-- * struct if it is a Winbond device.
-- * @spinand: SPI NAND device structure
-- */
--static int winbond_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * Winbond SPI NAND read ID need a dummy byte,
--	 * so the first byte in raw_id is dummy.
--	 */
--	if (id[1] != SPINAND_MFR_WINBOND)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, winbond_spinand_table,
--				     ARRAY_SIZE(winbond_spinand_table), id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static int winbond_spinand_init(struct spinand_device *spinand)
- {
- 	struct nand_device *nand = spinand_to_nand(spinand);
-@@ -138,12 +115,13 @@ static int winbond_spinand_init(struct spinand_device *spinand)
- }
- 
- static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
--	.detect = winbond_spinand_detect,
- 	.init = winbond_spinand_init,
- };
- 
- const struct spinand_manufacturer winbond_spinand_manufacturer = {
- 	.id = SPINAND_MFR_WINBOND,
- 	.name = "Winbond",
-+	.chips = winbond_spinand_table,
-+	.nchips = ARRAY_SIZE(winbond_spinand_table),
- 	.ops = &winbond_spinand_manuf_ops,
- };
-diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
-index 4ea558bd3..f4c4ae871 100644
---- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -32,9 +32,9 @@
- 		   SPI_MEM_OP_NO_DUMMY,					\
- 		   SPI_MEM_OP_NO_DATA)
- 
--#define SPINAND_READID_OP(ndummy, buf, len)				\
-+#define SPINAND_READID_OP(naddr, ndummy, buf, len)			\
- 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1),				\
--		   SPI_MEM_OP_NO_ADDR,					\
-+		   SPI_MEM_OP_ADDR(naddr, 0, 1),			\
- 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
- 		   SPI_MEM_OP_DATA_IN(len, buf, 1))
- 
-@@ -176,37 +176,46 @@ struct spinand_device;
-  * @data: buffer containing the id bytes. Currently 4 bytes large, but can
-  *	  be extended if required
-  * @len: ID length
-- *
-- * struct_spinand_id->data contains all bytes returned after a READ_ID command,
-- * including dummy bytes if the chip does not emit ID bytes right after the
-- * READ_ID command. The responsibility to extract real ID bytes is left to
-- * struct_manufacurer_ops->detect().
-  */
- struct spinand_id {
- 	u8 data[SPINAND_MAX_ID_LEN];
- 	int len;
- };
- 
-+enum spinand_readid_method {
-+	SPINAND_READID_METHOD_OPCODE,
-+	SPINAND_READID_METHOD_OPCODE_ADDR,
-+	SPINAND_READID_METHOD_OPCODE_DUMMY,
-+};
-+
-+/**
-+ * struct spinand_devid - SPI NAND device id structure
-+ * @id: device id of current chip
-+ * @len: number of bytes in device id
-+ * @method: method to read chip id
-+ *	    There are 3 possible variants:
-+ *	    SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
-+ *	    after read_id opcode.
-+ *	    SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
-+ *	    read_id opcode + 1-byte address.
-+ *	    SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
-+ *	    read_id opcode + 1 dummy byte.
-+ */
-+struct spinand_devid {
-+	const u8 *id;
-+	const u8 len;
-+	const enum spinand_readid_method method;
-+};
-+
- /**
-  * struct manufacurer_ops - SPI NAND manufacturer specific operations
-- * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed
-- *	    the core calls the struct_manufacurer_ops->detect() hook of each
-- *	    registered manufacturer until one of them return 1. Note that
-- *	    the first thing to check in this hook is that the manufacturer ID
-- *	    in struct_spinand_device->id matches the manufacturer whose
-- *	    ->detect() hook has been called. Should return 1 if there's a
-- *	    match, 0 if the manufacturer ID does not match and a negative
-- *	    error code otherwise. When true is returned, the core assumes
-- *	    that properties of the NAND chip (spinand->base.memorg and
-- *	    spinand->base.eccreq) have been filled
-  * @init: initialize a SPI NAND device
-  * @cleanup: cleanup a SPI NAND device
-  *
-  * Each SPI NAND manufacturer driver should implement this interface so that
-- * NAND chips coming from this vendor can be detected and initialized properly.
-+ * NAND chips coming from this vendor can be initialized properly.
-  */
- struct spinand_manufacturer_ops {
--	int (*detect)(struct spinand_device *spinand);
- 	int (*init)(struct spinand_device *spinand);
- 	void (*cleanup)(struct spinand_device *spinand);
- };
-@@ -215,11 +224,16 @@ struct spinand_manufacturer_ops {
-  * struct spinand_manufacturer - SPI NAND manufacturer instance
-  * @id: manufacturer ID
-  * @name: manufacturer name
-+ * @devid_len: number of bytes in device ID
-+ * @chips: supported SPI NANDs under current manufacturer
-+ * @nchips: number of SPI NANDs available in chips array
-  * @ops: manufacturer operations
-  */
- struct spinand_manufacturer {
- 	u8 id;
- 	char *name;
-+	const struct spinand_info *chips;
-+	const size_t nchips;
- 	const struct spinand_manufacturer_ops *ops;
- };
- 
-@@ -291,7 +305,7 @@ struct spinand_ecc_info {
-  */
- struct spinand_info {
- 	const char *model;
--	u16 devid;
-+	struct spinand_devid devid;
- 	u32 flags;
- 	struct nand_memory_organization memorg;
- 	struct nand_ecc_req eccreq;
-@@ -305,6 +319,13 @@ struct spinand_info {
- 			     unsigned int target);
- };
- 
-+#define SPINAND_ID(__method, ...)					\
-+	{								\
-+		.id = (const u8[]){ __VA_ARGS__ },			\
-+		.len = sizeof((u8[]){ __VA_ARGS__ }),			\
-+		.method = __method,					\
-+	}
-+
- #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update)		\
- 	{								\
- 		.read_cache = __read,					\
-@@ -451,9 +472,10 @@ static inline void spinand_set_of_node(struct spinand_device *spinand,
- 	nanddev_set_of_node(&spinand->base, np);
- }
- 
--int spinand_match_and_init(struct spinand_device *dev,
-+int spinand_match_and_init(struct spinand_device *spinand,
- 			   const struct spinand_info *table,
--			   unsigned int table_size, u16 devid);
-+			   unsigned int table_size,
-+			   enum spinand_readid_method rdid_method);
- 
- int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
- int spinand_select_target(struct spinand_device *spinand, unsigned int target);
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2312-mtd-spinand-macronix-Add-support-for-MX31LF1GE4BC.patch b/21.02/files/target/linux/generic/backport-5.4/999-2312-mtd-spinand-macronix-Add-support-for-MX31LF1GE4BC.patch
deleted file mode 100644
index d55e946..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2312-mtd-spinand-macronix-Add-support-for-MX31LF1GE4BC.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 9c8aa0697168dac0ad3638dc075c25087d4ee19c Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:10 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2312-mtd-spinand-macronix-Add-support-for-MX31LF1GE4BC.patch]
-
----
- drivers/mtd/nand/spi/macronix.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
-index 0f900f3aa..6e66d8710 100644
---- a/drivers/mtd/nand/spi/macronix.c
-+++ b/drivers/mtd/nand/spi/macronix.c
-@@ -118,6 +118,16 @@ static const struct spinand_info macronix_spinand_table[] = {
- 					      &update_cache_variants),
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
-+	SPINAND_INFO("MX31LF1GE4BC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0 /*SPINAND_HAS_QE_BIT*/,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
- };
- 
- static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2313-mtd-spinand-macronix-Add-support-for-MX31UF1GE4BC.patch b/21.02/files/target/linux/generic/backport-5.4/999-2313-mtd-spinand-macronix-Add-support-for-MX31UF1GE4BC.patch
deleted file mode 100644
index 8dcf798..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2313-mtd-spinand-macronix-Add-support-for-MX31UF1GE4BC.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 34485df92908238e8603d2c9de486e7c41db45fb Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:10 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2313-mtd-spinand-macronix-Add-support-for-MX31UF1GE4BC.patch]
-
----
- drivers/mtd/nand/spi/macronix.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
-index 6e66d8710..4964fe35b 100644
---- a/drivers/mtd/nand/spi/macronix.c
-+++ b/drivers/mtd/nand/spi/macronix.c
-@@ -128,6 +128,16 @@ static const struct spinand_info macronix_spinand_table[] = {
- 		     0 /*SPINAND_HAS_QE_BIT*/,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX31UF1GE4BC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0 /*SPINAND_HAS_QE_BIT*/,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
- };
- 
- static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2314-mtd-spinand-macronix-Add-support-for-MX35LFxGE4AD.patch b/21.02/files/target/linux/generic/backport-5.4/999-2314-mtd-spinand-macronix-Add-support-for-MX35LFxGE4AD.patch
deleted file mode 100644
index eaa9851..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2314-mtd-spinand-macronix-Add-support-for-MX35LFxGE4AD.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 14f6824f11e1167bf2cbbd650cd6a7a2ad856555 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:10 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2314-mtd-spinand-macronix-Add-support-for-MX35LFxGE4AD.patch]
-
----
- drivers/mtd/nand/spi/macronix.c | 20 ++++++++++++++++++++
- 1 file changed, 20 insertions(+)
-
-diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
-index 4964fe35b..16d2acafb 100644
---- a/drivers/mtd/nand/spi/macronix.c
-+++ b/drivers/mtd/nand/spi/macronix.c
-@@ -118,6 +118,26 @@ static const struct spinand_info macronix_spinand_table[] = {
- 					      &update_cache_variants),
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
-+	SPINAND_INFO("MX35LF2GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x26),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35LF4GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37),
-+		     NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
- 	SPINAND_INFO("MX31LF1GE4BC",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2315-mtd-spinand-macronix-Add-support-for-MX35LFxG24AD.patch b/21.02/files/target/linux/generic/backport-5.4/999-2315-mtd-spinand-macronix-Add-support-for-MX35LFxG24AD.patch
deleted file mode 100644
index 41b540c..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2315-mtd-spinand-macronix-Add-support-for-MX35LFxG24AD.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 1de538322f8e3b2586d5b41bdcc0383ecba9ce32 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:10 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2315-mtd-spinand-macronix-Add-support-for-MX35LFxG24AD.patch]
-
----
- drivers/mtd/nand/spi/macronix.c | 27 +++++++++++++++++++++++++++
- 1 file changed, 27 insertions(+)
-
-diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
-index 16d2acafb..e0c71c654 100644
---- a/drivers/mtd/nand/spi/macronix.c
-+++ b/drivers/mtd/nand/spi/macronix.c
-@@ -138,6 +138,33 @@ static const struct spinand_info macronix_spinand_table[] = {
- 		     0,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35LF1G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
-+	SPINAND_INFO("MX35LF2G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
-+	SPINAND_INFO("MX35LF4G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
- 	SPINAND_INFO("MX31LF1GE4BC",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2316-mtd-spinand-macronix-Add-support-for-serial-NAND-flash.patch b/21.02/files/target/linux/generic/backport-5.4/999-2316-mtd-spinand-macronix-Add-support-for-serial-NAND-flash.patch
deleted file mode 100644
index fbcca17..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2316-mtd-spinand-macronix-Add-support-for-serial-NAND-flash.patch
+++ /dev/null
@@ -1,136 +0,0 @@
-From 3b7dc97f2ff2d354c7f624d4d04fd5dd8595c923 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:11 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2316-mtd-spinand-macronix-Add-support-for-serial-NAND-flash.patch]
-
----
- drivers/mtd/nand/spi/macronix.c | 112 ++++++++++++++++++++++++++++++++
- 1 file changed, 112 insertions(+)
-
-diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
-index e0c71c654..ede66b71b 100644
---- a/drivers/mtd/nand/spi/macronix.c
-+++ b/drivers/mtd/nand/spi/macronix.c
-@@ -185,6 +185,118 @@ static const struct spinand_info macronix_spinand_table[] = {
- 		     0 /*SPINAND_HAS_QE_BIT*/,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
-+
-+	SPINAND_INFO("MX35LF2G14AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF4G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF4GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF2G14AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF2G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF2GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF2GE4AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF1G14AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF1G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF1GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF1GE4AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+
- };
- 
- static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2317-mtd-spinand-macronix-Add-Quad-support-for-serial-NAND-flash.patch b/21.02/files/target/linux/generic/backport-5.4/999-2317-mtd-spinand-macronix-Add-Quad-support-for-serial-NAND-flash.patch
deleted file mode 100644
index bcc9df8..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2317-mtd-spinand-macronix-Add-Quad-support-for-serial-NAND-flash.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From ec328d836a28d538c38f67f5467b9319d6a950a3 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:11 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2317-mtd-spinand-macronix-Add-Quad-support-for-serial-NAND-flash.patch]
-
----
- drivers/mtd/nand/spi/macronix.c | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
-index ede66b71b..25319b4f8 100644
---- a/drivers/mtd/nand/spi/macronix.c
-+++ b/drivers/mtd/nand/spi/macronix.c
-@@ -125,7 +125,7 @@ static const struct spinand_info macronix_spinand_table[] = {
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
--		     0,
-+		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
- 	SPINAND_INFO("MX35LF4GE4AD",
-@@ -135,7 +135,7 @@ static const struct spinand_info macronix_spinand_table[] = {
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
--		     0,
-+		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
- 	SPINAND_INFO("MX35LF1G24AD",
-@@ -145,16 +145,16 @@ static const struct spinand_info macronix_spinand_table[] = {
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
--		     0,
-+		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
- 	SPINAND_INFO("MX35LF2G24AD",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
--		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
--		     0,
-+		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
- 	SPINAND_INFO("MX35LF4G24AD",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
-@@ -163,7 +163,7 @@ static const struct spinand_info macronix_spinand_table[] = {
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
--		     0,
-+		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
- 	SPINAND_INFO("MX31LF1GE4BC",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e),
-@@ -172,7 +172,7 @@ static const struct spinand_info macronix_spinand_table[] = {
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
--		     0 /*SPINAND_HAS_QE_BIT*/,
-+		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
- 	SPINAND_INFO("MX31UF1GE4BC",
-@@ -182,7 +182,7 @@ static const struct spinand_info macronix_spinand_table[] = {
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
--		     0 /*SPINAND_HAS_QE_BIT*/,
-+		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
- 
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2318-mtd-spinand-micron-Generalize-the-OOB-layout-structure-and-function-names.patch b/21.02/files/target/linux/generic/backport-5.4/999-2318-mtd-spinand-micron-Generalize-the-OOB-layout-structure-and-function-names.patch
deleted file mode 100644
index 2e888d3..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2318-mtd-spinand-micron-Generalize-the-OOB-layout-structure-and-function-names.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From aebf853ada4f73280d4cf7a1799cb0ebf84f87e1 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:11 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2318-mtd-spinand-micron-Generalize-the-OOB-layout-structure-and-function-names.patch]
-
----
- drivers/mtd/nand/spi/micron.c | 28 ++++++++++++++--------------
- 1 file changed, 14 insertions(+), 14 deletions(-)
-
-diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
-index f56f81325..cc1ee6842 100644
---- a/drivers/mtd/nand/spi/micron.c
-+++ b/drivers/mtd/nand/spi/micron.c
-@@ -34,38 +34,38 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
- 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
- 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
- 
--static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
--					struct mtd_oob_region *region)
-+static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				  struct mtd_oob_region *region)
- {
- 	if (section)
- 		return -ERANGE;
- 
--	region->offset = 64;
--	region->length = 64;
-+	region->offset = mtd->oobsize / 2;
-+	region->length = mtd->oobsize / 2;
- 
- 	return 0;
- }
- 
--static int mt29f2g01abagd_ooblayout_free(struct mtd_info *mtd, int section,
--					 struct mtd_oob_region *region)
-+static int micron_8_ooblayout_free(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *region)
- {
- 	if (section)
- 		return -ERANGE;
- 
- 	/* Reserve 2 bytes for the BBM. */
- 	region->offset = 2;
--	region->length = 62;
-+	region->length = (mtd->oobsize / 2) - 2;
- 
- 	return 0;
- }
- 
--static const struct mtd_ooblayout_ops mt29f2g01abagd_ooblayout = {
--	.ecc = mt29f2g01abagd_ooblayout_ecc,
--	.free = mt29f2g01abagd_ooblayout_free,
-+static const struct mtd_ooblayout_ops micron_8_ooblayout = {
-+	.ecc = micron_8_ooblayout_ecc,
-+	.free = micron_8_ooblayout_free,
- };
- 
--static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
--					 u8 status)
-+static int micron_8_ecc_get_status(struct spinand_device *spinand,
-+				   u8 status)
- {
- 	switch (status & MICRON_STATUS_ECC_MASK) {
- 	case STATUS_ECC_NO_BITFLIPS:
-@@ -99,8 +99,8 @@ static const struct spinand_info micron_spinand_table[] = {
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     0,
--		     SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
--				     mt29f2g01abagd_ecc_get_status)),
-+		     SPINAND_ECCINFO(&micron_8_ooblayout,
-+				     micron_8_ecc_get_status)),
- };
- 
- static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2319-mtd-spinand-micron-Describe-the-SPI-NAND-device-MT29F2G01ABAGD.patch b/21.02/files/target/linux/generic/backport-5.4/999-2319-mtd-spinand-micron-Describe-the-SPI-NAND-device-MT29F2G01ABAGD.patch
deleted file mode 100644
index 3ff682b..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2319-mtd-spinand-micron-Describe-the-SPI-NAND-device-MT29F2G01ABAGD.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 59766b3af8f603e740c38d2cc03c37226c78bb11 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:11 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2319-mtd-spinand-micron-Describe-the-SPI-NAND-device-MT29F2G01ABAGD.patch]
-
----
- drivers/mtd/nand/spi/micron.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
-index cc1ee6842..4727933c8 100644
---- a/drivers/mtd/nand/spi/micron.c
-+++ b/drivers/mtd/nand/spi/micron.c
-@@ -91,6 +91,7 @@ static int micron_8_ecc_get_status(struct spinand_device *spinand,
- }
- 
- static const struct spinand_info micron_spinand_table[] = {
-+	/* M79A 2Gb 3.3V */
- 	SPINAND_INFO("MT29F2G01ABAGD",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2320-mtd-spinand-micron-Add-new-Micron-SPI-NAND-devices.patch b/21.02/files/target/linux/generic/backport-5.4/999-2320-mtd-spinand-micron-Add-new-Micron-SPI-NAND-devices.patch
deleted file mode 100644
index 4c5e911..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2320-mtd-spinand-micron-Add-new-Micron-SPI-NAND-devices.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 66ea40f7c5b196eee609c5e3322aac3a7ac59e03 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:12 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2320-mtd-spinand-micron-Add-new-Micron-SPI-NAND-devices.patch]
-
----
- drivers/mtd/nand/spi/micron.c | 33 +++++++++++++++++++++++++++++++++
- 1 file changed, 33 insertions(+)
-
-diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
-index 4727933c8..26925714a 100644
---- a/drivers/mtd/nand/spi/micron.c
-+++ b/drivers/mtd/nand/spi/micron.c
-@@ -102,6 +102,39 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     0,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
-+	/* M79A 2Gb 1.8V */
-+	SPINAND_INFO("MT29F2G01ABBGD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&micron_8_ooblayout,
-+				     micron_8_ecc_get_status)),
-+	/* M78A 1Gb 3.3V */
-+	SPINAND_INFO("MT29F1G01ABAFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&micron_8_ooblayout,
-+				     micron_8_ecc_get_status)),
-+	/* M78A 1Gb 1.8V */
-+	SPINAND_INFO("MT29F1G01ABAFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&micron_8_ooblayout,
-+				     micron_8_ecc_get_status)),
- };
- 
- static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2321-mtd-spinand-micron-identify-SPI-NAND-device-with-Continuous-Read-mode.patch b/21.02/files/target/linux/generic/backport-5.4/999-2321-mtd-spinand-micron-identify-SPI-NAND-device-with-Continuous-Read-mode.patch
deleted file mode 100644
index ae7ac72..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2321-mtd-spinand-micron-identify-SPI-NAND-device-with-Continuous-Read-mode.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 65c3b878a33bb7edd5413860537fecdff94aaba6 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:12 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2321-mtd-spinand-micron-identify-SPI-NAND-device-with-Continuous-Read-mode.patch]
-
----
- drivers/mtd/nand/spi/micron.c | 16 ++++++++++++++++
- include/linux/mtd/spinand.h   |  1 +
- 2 files changed, 17 insertions(+)
-
-diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
-index 26925714a..956f7710a 100644
---- a/drivers/mtd/nand/spi/micron.c
-+++ b/drivers/mtd/nand/spi/micron.c
-@@ -18,6 +18,8 @@
- #define MICRON_STATUS_ECC_4TO6_BITFLIPS	(3 << 4)
- #define MICRON_STATUS_ECC_7TO8_BITFLIPS	(5 << 4)
- 
-+#define MICRON_CFG_CR			BIT(0)
-+
- static SPINAND_OP_VARIANTS(read_cache_variants,
- 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-@@ -137,7 +139,21 @@ static const struct spinand_info micron_spinand_table[] = {
- 				     micron_8_ecc_get_status)),
- };
- 
-+static int micron_spinand_init(struct spinand_device *spinand)
-+{
-+	/*
-+	 * M70A device series enable Continuous Read feature at Power-up,
-+	 * which is not supported. Disable this bit to avoid any possible
-+	 * failure.
-+	 */
-+	if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT)
-+		return spinand_upd_cfg(spinand, MICRON_CFG_CR, 0);
-+
-+	return 0;
-+}
-+
- static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
-+	.init = micron_spinand_init,
- };
- 
- const struct spinand_manufacturer micron_spinand_manufacturer = {
-diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
-index f4c4ae871..1077c4572 100644
---- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -284,6 +284,7 @@ struct spinand_ecc_info {
- };
- 
- #define SPINAND_HAS_QE_BIT		BIT(0)
-+#define SPINAND_HAS_CR_FEAT_BIT		BIT(1)
- 
- /**
-  * struct spinand_info - Structure used to describe SPI NAND chips
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2322-mtd-spinand-micron-Add-M70A-series-Micron-SPI-NAND-devices.patch b/21.02/files/target/linux/generic/backport-5.4/999-2322-mtd-spinand-micron-Add-M70A-series-Micron-SPI-NAND-devices.patch
deleted file mode 100644
index 426d674..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2322-mtd-spinand-micron-Add-M70A-series-Micron-SPI-NAND-devices.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 5a4cd6ba8f7ae6744ca44f78c761f26e843c0341 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:12 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2322-mtd-spinand-micron-Add-M70A-series-Micron-SPI-NAND-devices.patch]
-
----
- drivers/mtd/nand/spi/micron.c | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
-diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
-index 956f7710a..d6fd63008 100644
---- a/drivers/mtd/nand/spi/micron.c
-+++ b/drivers/mtd/nand/spi/micron.c
-@@ -137,6 +137,28 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     0,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
-+	/* M70A 4Gb 3.3V */
-+	SPINAND_INFO("MT29F4G01ABAFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_CR_FEAT_BIT,
-+		     SPINAND_ECCINFO(&micron_8_ooblayout,
-+				     micron_8_ecc_get_status)),
-+	/* M70A 4Gb 1.8V */
-+	SPINAND_INFO("MT29F4G01ABBFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_CR_FEAT_BIT,
-+		     SPINAND_ECCINFO(&micron_8_ooblayout,
-+				     micron_8_ecc_get_status)),
- };
- 
- static int micron_spinand_init(struct spinand_device *spinand)
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2323-mtd-spinand-micron-Add-new-Micron-SPI-NAND-devices-with-multiple-dies.patch b/21.02/files/target/linux/generic/backport-5.4/999-2323-mtd-spinand-micron-Add-new-Micron-SPI-NAND-devices-with-multiple-dies.patch
deleted file mode 100644
index 2e0a356..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2323-mtd-spinand-micron-Add-new-Micron-SPI-NAND-devices-with-multiple-dies.patch
+++ /dev/null
@@ -1,103 +0,0 @@
-From ac7be09336555cf993d904bd9e42c05d1769288a Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:12 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2323-mtd-spinand-micron-Add-new-Micron-SPI-NAND-devices-with-multiple-dies.patch]
-
----
- drivers/mtd/nand/spi/micron.c | 58 +++++++++++++++++++++++++++++++++++
- 1 file changed, 58 insertions(+)
-
-diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
-index d6fd63008..5d370cfcd 100644
---- a/drivers/mtd/nand/spi/micron.c
-+++ b/drivers/mtd/nand/spi/micron.c
-@@ -20,6 +20,14 @@
- 
- #define MICRON_CFG_CR			BIT(0)
- 
-+/*
-+ * As per datasheet, die selection is done by the 6th bit of Die
-+ * Select Register (Address 0xD0).
-+ */
-+#define MICRON_DIE_SELECT_REG	0xD0
-+
-+#define MICRON_SELECT_DIE(x)	((x) << 6)
-+
- static SPINAND_OP_VARIANTS(read_cache_variants,
- 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-@@ -66,6 +74,20 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = {
- 	.free = micron_8_ooblayout_free,
- };
- 
-+static int micron_select_target(struct spinand_device *spinand,
-+				unsigned int target)
-+{
-+	struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG,
-+						      spinand->scratchbuf);
-+
-+	if (target > 1)
-+		return -EINVAL;
-+
-+	*spinand->scratchbuf = MICRON_SELECT_DIE(target);
-+
-+	return spi_mem_exec_op(spinand->spimem, &op);
-+}
-+
- static int micron_8_ecc_get_status(struct spinand_device *spinand,
- 				   u8 status)
- {
-@@ -137,6 +159,18 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     0,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
-+	/* M79A 4Gb 3.3V */
-+	SPINAND_INFO("MT29F4G01ADAGD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&micron_8_ooblayout,
-+				     micron_8_ecc_get_status),
-+		     SPINAND_SELECT_TARGET(micron_select_target)),
- 	/* M70A 4Gb 3.3V */
- 	SPINAND_INFO("MT29F4G01ABAFD",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
-@@ -159,6 +193,30 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     SPINAND_HAS_CR_FEAT_BIT,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
-+	/* M70A 8Gb 3.3V */
-+	SPINAND_INFO("MT29F8G01ADAFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_CR_FEAT_BIT,
-+		     SPINAND_ECCINFO(&micron_8_ooblayout,
-+				     micron_8_ecc_get_status),
-+		     SPINAND_SELECT_TARGET(micron_select_target)),
-+	/* M70A 8Gb 1.8V */
-+	SPINAND_INFO("MT29F8G01ADBFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_CR_FEAT_BIT,
-+		     SPINAND_ECCINFO(&micron_8_ooblayout,
-+				     micron_8_ecc_get_status),
-+		     SPINAND_SELECT_TARGET(micron_select_target)),
- };
- 
- static int micron_spinand_init(struct spinand_device *spinand)
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2324-mtd-spinand-micron-Use-more-specific-names.patch b/21.02/files/target/linux/generic/backport-5.4/999-2324-mtd-spinand-micron-Use-more-specific-names.patch
deleted file mode 100644
index e397967..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2324-mtd-spinand-micron-Use-more-specific-names.patch
+++ /dev/null
@@ -1,157 +0,0 @@
-From 5abef195abf3faa6f8e22a2e6996316f14c4f21c Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:13 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2324-mtd-spinand-micron-Use-more-specific-names.patch]
-
----
- drivers/mtd/nand/spi/micron.c | 60 +++++++++++++++++------------------
- 1 file changed, 30 insertions(+), 30 deletions(-)
-
-diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
-index 5d370cfcd..afe3ba37d 100644
---- a/drivers/mtd/nand/spi/micron.c
-+++ b/drivers/mtd/nand/spi/micron.c
-@@ -28,7 +28,7 @@
- 
- #define MICRON_SELECT_DIE(x)	((x) << 6)
- 
--static SPINAND_OP_VARIANTS(read_cache_variants,
-+static SPINAND_OP_VARIANTS(quadio_read_cache_variants,
- 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
-@@ -36,11 +36,11 @@ static SPINAND_OP_VARIANTS(read_cache_variants,
- 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
- 
--static SPINAND_OP_VARIANTS(write_cache_variants,
-+static SPINAND_OP_VARIANTS(x4_write_cache_variants,
- 		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
- 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
- 
--static SPINAND_OP_VARIANTS(update_cache_variants,
-+static SPINAND_OP_VARIANTS(x4_update_cache_variants,
- 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
- 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
- 
-@@ -120,9 +120,9 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
- 		     NAND_ECCREQ(8, 512),
--		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
--					      &write_cache_variants,
--					      &update_cache_variants),
-+		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
-+					      &x4_write_cache_variants,
-+					      &x4_update_cache_variants),
- 		     0,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
-@@ -131,9 +131,9 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
- 		     NAND_ECCREQ(8, 512),
--		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
--					      &write_cache_variants,
--					      &update_cache_variants),
-+		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
-+					      &x4_write_cache_variants,
-+					      &x4_update_cache_variants),
- 		     0,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
-@@ -142,9 +142,9 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
--		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
--					      &write_cache_variants,
--					      &update_cache_variants),
-+		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
-+					      &x4_write_cache_variants,
-+					      &x4_update_cache_variants),
- 		     0,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
-@@ -153,9 +153,9 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
--		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
--					      &write_cache_variants,
--					      &update_cache_variants),
-+		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
-+					      &x4_write_cache_variants,
-+					      &x4_update_cache_variants),
- 		     0,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
-@@ -164,9 +164,9 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2),
- 		     NAND_ECCREQ(8, 512),
--		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
--					      &write_cache_variants,
--					      &update_cache_variants),
-+		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
-+					      &x4_write_cache_variants,
-+					      &x4_update_cache_variants),
- 		     0,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status),
-@@ -176,9 +176,9 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
--		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
--					      &write_cache_variants,
--					      &update_cache_variants),
-+		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
-+					      &x4_write_cache_variants,
-+					      &x4_update_cache_variants),
- 		     SPINAND_HAS_CR_FEAT_BIT,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
-@@ -187,9 +187,9 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
--		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
--					      &write_cache_variants,
--					      &update_cache_variants),
-+		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
-+					      &x4_write_cache_variants,
-+					      &x4_update_cache_variants),
- 		     SPINAND_HAS_CR_FEAT_BIT,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
-@@ -198,9 +198,9 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
- 		     NAND_ECCREQ(8, 512),
--		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
--					      &write_cache_variants,
--					      &update_cache_variants),
-+		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
-+					      &x4_write_cache_variants,
-+					      &x4_update_cache_variants),
- 		     SPINAND_HAS_CR_FEAT_BIT,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status),
-@@ -210,9 +210,9 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
- 		     NAND_ECCREQ(8, 512),
--		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
--					      &write_cache_variants,
--					      &update_cache_variants),
-+		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
-+					      &x4_write_cache_variants,
-+					      &x4_update_cache_variants),
- 		     SPINAND_HAS_CR_FEAT_BIT,
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status),
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2325-mtd-spinand-micron-Add-support-for-MT29F2G01AAAED.patch b/21.02/files/target/linux/generic/backport-5.4/999-2325-mtd-spinand-micron-Add-support-for-MT29F2G01AAAED.patch
deleted file mode 100644
index b6914ce..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2325-mtd-spinand-micron-Add-support-for-MT29F2G01AAAED.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-From 5cea72055a3bce2b8b5a1f8cb6d46165eeccd8b9 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:13 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2325-mtd-spinand-micron-Add-support-for-MT29F2G01AAAED.patch]
-
----
- drivers/mtd/nand/spi/micron.c | 64 +++++++++++++++++++++++++++++++++++
- 1 file changed, 64 insertions(+)
-
-diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
-index afe3ba37d..50b7295bc 100644
---- a/drivers/mtd/nand/spi/micron.c
-+++ b/drivers/mtd/nand/spi/micron.c
-@@ -44,6 +44,19 @@ static SPINAND_OP_VARIANTS(x4_update_cache_variants,
- 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
- 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
- 
-+/* Micron  MT29F2G01AAAED Device */
-+static SPINAND_OP_VARIANTS(x4_read_cache_variants,
-+			   SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-+			   SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
-+			   SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
-+			   SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(x1_write_cache_variants,
-+			   SPINAND_PROG_LOAD(true, 0, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(x1_update_cache_variants,
-+			   SPINAND_PROG_LOAD(false, 0, NULL, 0));
-+
- static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section,
- 				  struct mtd_oob_region *region)
- {
-@@ -74,6 +87,47 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = {
- 	.free = micron_8_ooblayout_free,
- };
- 
-+static int micron_4_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				  struct mtd_oob_region *region)
-+{
-+	struct spinand_device *spinand = mtd_to_spinand(mtd);
-+
-+	if (section >= spinand->base.memorg.pagesize /
-+			mtd->ecc_step_size)
-+		return -ERANGE;
-+
-+	region->offset = (section * 16) + 8;
-+	region->length = 8;
-+
-+	return 0;
-+}
-+
-+static int micron_4_ooblayout_free(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *region)
-+{
-+	struct spinand_device *spinand = mtd_to_spinand(mtd);
-+
-+	if (section >= spinand->base.memorg.pagesize /
-+			mtd->ecc_step_size)
-+		return -ERANGE;
-+
-+	if (section) {
-+		region->offset = 16 * section;
-+		region->length = 8;
-+	} else {
-+		/* section 0 has two bytes reserved for the BBM */
-+		region->offset = 2;
-+		region->length = 6;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops micron_4_ooblayout = {
-+	.ecc = micron_4_ooblayout_ecc,
-+	.free = micron_4_ooblayout_free,
-+};
-+
- static int micron_select_target(struct spinand_device *spinand,
- 				unsigned int target)
- {
-@@ -217,6 +271,16 @@ static const struct spinand_info micron_spinand_table[] = {
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status),
- 		     SPINAND_SELECT_TARGET(micron_select_target)),
-+	/* M69A 2Gb 3.3V */
-+	SPINAND_INFO("MT29F2G01AAAED",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9F),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 80, 2, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&x4_read_cache_variants,
-+					      &x1_write_cache_variants,
-+					      &x1_update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&micron_4_ooblayout, NULL)),
- };
- 
- static int micron_spinand_init(struct spinand_device *spinand)
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2326-mtd-spinand-toshiba-Rename-function-name-to-change-suffix-and-prefix-8Gbit.patch b/21.02/files/target/linux/generic/backport-5.4/999-2326-mtd-spinand-toshiba-Rename-function-name-to-change-suffix-and-prefix-8Gbit.patch
deleted file mode 100644
index 74bab62..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2326-mtd-spinand-toshiba-Rename-function-name-to-change-suffix-and-prefix-8Gbit.patch
+++ /dev/null
@@ -1,159 +0,0 @@
-From af4301a675f4fcbaa787f1d3bd07df1c08a093c3 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:13 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2326-mtd-spinand-toshiba-Rename-function-name-to-change-suffix-and-prefix-8Gbit.patch]
-
----
- drivers/mtd/nand/spi/toshiba.c | 65 ++++++++++++++++++++--------------
- 1 file changed, 38 insertions(+), 27 deletions(-)
-
-diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c
-index 35da3c6e9..7ce5997dd 100644
---- a/drivers/mtd/nand/spi/toshiba.c
-+++ b/drivers/mtd/nand/spi/toshiba.c
-@@ -25,8 +25,8 @@ static SPINAND_OP_VARIANTS(write_cache_variants,
- static SPINAND_OP_VARIANTS(update_cache_variants,
- 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
- 
--static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section,
--				     struct mtd_oob_region *region)
-+static int tx58cxgxsxraix_ooblayout_ecc(struct mtd_info *mtd, int section,
-+					struct mtd_oob_region *region)
- {
- 	if (section > 0)
- 		return -ERANGE;
-@@ -37,8 +37,8 @@ static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section,
- 	return 0;
- }
- 
--static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section,
--				      struct mtd_oob_region *region)
-+static int tx58cxgxsxraix_ooblayout_free(struct mtd_info *mtd, int section,
-+					 struct mtd_oob_region *region)
- {
- 	if (section > 0)
- 		return -ERANGE;
-@@ -50,13 +50,13 @@ static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section,
- 	return 0;
- }
- 
--static const struct mtd_ooblayout_ops tc58cxgxsx_ooblayout = {
--	.ecc = tc58cxgxsx_ooblayout_ecc,
--	.free = tc58cxgxsx_ooblayout_free,
-+static const struct mtd_ooblayout_ops tx58cxgxsxraix_ooblayout = {
-+	.ecc = tx58cxgxsxraix_ooblayout_ecc,
-+	.free = tx58cxgxsxraix_ooblayout_free,
- };
- 
--static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand,
--				      u8 status)
-+static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
-+					 u8 status)
- {
- 	struct nand_device *nand = spinand_to_nand(spinand);
- 	u8 mbf = 0;
-@@ -95,7 +95,7 @@ static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand,
- 
- static const struct spinand_info toshiba_spinand_table[] = {
- 	/* 3.3V 1Gb */
--	SPINAND_INFO("TC58CVG0S3",
-+	SPINAND_INFO("TC58CVG0S3HRAIG",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
-@@ -103,10 +103,10 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     0,
--		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
--				     tc58cxgxsx_ecc_get_status)),
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 3.3V 2Gb */
--	SPINAND_INFO("TC58CVG1S3",
-+	SPINAND_INFO("TC58CVG1S3HRAIG",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
-@@ -114,10 +114,10 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     0,
--		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
--				     tc58cxgxsx_ecc_get_status)),
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 3.3V 4Gb */
--	SPINAND_INFO("TC58CVG2S0",
-+	SPINAND_INFO("TC58CVG2S0HRAIG",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
-@@ -125,10 +125,21 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     0,
--		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
--				     tc58cxgxsx_ecc_get_status)),
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
-+	/* 3.3V 4Gb */
-+	SPINAND_INFO("TC58CVG2S0HRAIJ",
-+			SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 1Gb */
--	SPINAND_INFO("TC58CYG0S3",
-+	SPINAND_INFO("TC58CYG0S3HRAIG",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
-@@ -136,10 +147,10 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     0,
--		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
--				     tc58cxgxsx_ecc_get_status)),
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 2Gb */
--	SPINAND_INFO("TC58CYG1S3",
-+	SPINAND_INFO("TC58CYG1S3HRAIG",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
-@@ -147,10 +158,10 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     0,
--		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
--				     tc58cxgxsx_ecc_get_status)),
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 4Gb */
--	SPINAND_INFO("TC58CYG2S0",
-+	SPINAND_INFO("TC58CYG2S0HRAIG",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
-@@ -158,8 +169,8 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     0,
--		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
--				     tc58cxgxsx_ecc_get_status)),
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
- };
- 
- static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/generic/backport-5.4/999-2327-mtd-spinand-toshiba-Support-for-new-Kioxia-Serial-NAND.patch b/21.02/files/target/linux/generic/backport-5.4/999-2327-mtd-spinand-toshiba-Support-for-new-Kioxia-Serial-NAND.patch
deleted file mode 100644
index 12a55cb..0000000
--- a/21.02/files/target/linux/generic/backport-5.4/999-2327-mtd-spinand-toshiba-Support-for-new-Kioxia-Serial-NAND.patch
+++ /dev/null
@@ -1,201 +0,0 @@
-From 1d16ff587875717c950c983af8eaa474d0a855ca Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:13 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2327-mtd-spinand-toshiba-Support-for-new-Kioxia-Serial-NAND.patch]
-
----
- drivers/mtd/nand/spi/toshiba.c | 128 ++++++++++++++++++++++++++++-----
- 1 file changed, 111 insertions(+), 17 deletions(-)
-
-diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c
-index 7ce5997dd..be51a2eaf 100644
---- a/drivers/mtd/nand/spi/toshiba.c
-+++ b/drivers/mtd/nand/spi/toshiba.c
-@@ -19,6 +19,18 @@ static SPINAND_OP_VARIANTS(read_cache_variants,
- 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
- 
-+static SPINAND_OP_VARIANTS(write_cache_x4_variants,
-+		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
-+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(update_cache_x4_variants,
-+		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
-+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
-+
-+/**
-+ * Backward compatibility for 1st generation Serial NAND devices
-+ * which don't support Quad Program Load operation.
-+ */
- static SPINAND_OP_VARIANTS(write_cache_variants,
- 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
- 
-@@ -94,7 +106,7 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
- }
- 
- static const struct spinand_info toshiba_spinand_table[] = {
--	/* 3.3V 1Gb */
-+	/* 3.3V 1Gb (1st generation) */
- 	SPINAND_INFO("TC58CVG0S3HRAIG",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-@@ -105,7 +117,7 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 		     0,
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
--	/* 3.3V 2Gb */
-+	/* 3.3V 2Gb (1st generation) */
- 	SPINAND_INFO("TC58CVG1S3HRAIG",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-@@ -116,7 +128,7 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 		     0,
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
--	/* 3.3V 4Gb */
-+	/* 3.3V 4Gb (1st generation) */
- 	SPINAND_INFO("TC58CVG2S0HRAIG",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-@@ -127,18 +139,7 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 		     0,
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
--	/* 3.3V 4Gb */
--	SPINAND_INFO("TC58CVG2S0HRAIJ",
--			SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED),
--		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
--		     NAND_ECCREQ(8, 512),
--		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
--					      &write_cache_variants,
--					      &update_cache_variants),
--		     0,
--		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
--				     tx58cxgxsxraix_ecc_get_status)),
--	/* 1.8V 1Gb */
-+	/* 1.8V 1Gb (1st generation) */
- 	SPINAND_INFO("TC58CYG0S3HRAIG",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-@@ -149,7 +150,7 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 		     0,
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
--	/* 1.8V 2Gb */
-+	/* 1.8V 2Gb (1st generation) */
- 	SPINAND_INFO("TC58CYG1S3HRAIG",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-@@ -160,7 +161,7 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 		     0,
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
--	/* 1.8V 4Gb */
-+	/* 1.8V 4Gb (1st generation) */
- 	SPINAND_INFO("TC58CYG2S0HRAIG",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-@@ -171,6 +172,99 @@ static const struct spinand_info toshiba_spinand_table[] = {
- 		     0,
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
-+
-+	/*
-+	 * 2nd generation serial nand has HOLD_D which is equivalent to
-+	 * QE_BIT.
-+	 */
-+	/* 3.3V 1Gb (2nd generation) */
-+	SPINAND_INFO("TC58CVG0S3HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_x4_variants,
-+					      &update_cache_x4_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
-+	/* 3.3V 2Gb (2nd generation) */
-+	SPINAND_INFO("TC58CVG1S3HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_x4_variants,
-+					      &update_cache_x4_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
-+	/* 3.3V 4Gb (2nd generation) */
-+	SPINAND_INFO("TC58CVG2S0HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_x4_variants,
-+					      &update_cache_x4_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
-+	/* 3.3V 8Gb (2nd generation) */
-+	SPINAND_INFO("TH58CVG3S0HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
-+		     NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_x4_variants,
-+					      &update_cache_x4_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
-+	/* 1.8V 1Gb (2nd generation) */
-+	SPINAND_INFO("TC58CYG0S3HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_x4_variants,
-+					      &update_cache_x4_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
-+	/* 1.8V 2Gb (2nd generation) */
-+	SPINAND_INFO("TC58CYG1S3HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_x4_variants,
-+					      &update_cache_x4_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
-+	/* 1.8V 4Gb (2nd generation) */
-+	SPINAND_INFO("TC58CYG2S0HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_x4_variants,
-+					      &update_cache_x4_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
-+	/* 1.8V 8Gb (2nd generation) */
-+	SPINAND_INFO("TH58CYG3S0HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
-+		     NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_x4_variants,
-+					      &update_cache_x4_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
-+				     tx58cxgxsxraix_ecc_get_status)),
- };
- 
- static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/mediatek/patches-5.4/999-1401-v5.7-mtd-spinand-backport-winbond-and-base-file.patch b/21.02/files/target/linux/mediatek/patches-5.4/999-1401-v5.7-mtd-spinand-backport-winbond-and-base-file.patch
new file mode 100644
index 0000000..cd096d3
--- /dev/null
+++ b/21.02/files/target/linux/mediatek/patches-5.4/999-1401-v5.7-mtd-spinand-backport-winbond-and-base-file.patch
@@ -0,0 +1,369 @@
+Index: linux-5.4.260/drivers/mtd/nand/spi/core.c
+===================================================================
+--- linux-5.4.260.orig/drivers/mtd/nand/spi/core.c
++++ linux-5.4.260/drivers/mtd/nand/spi/core.c
+@@ -16,6 +16,7 @@
+ #include <linux/mtd/spinand.h>
+ #include <linux/of.h>
+ #include <linux/slab.h>
++#include <linux/string.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/spi-mem.h>
+ 
+@@ -370,10 +371,11 @@ out:
+ 	return status & STATUS_BUSY ? -ETIMEDOUT : 0;
+ }
+ 
+-static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
++static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr,
++			      u8 ndummy, u8 *buf)
+ {
+-	struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
+-						 SPINAND_MAX_ID_LEN);
++	struct spi_mem_op op = SPINAND_READID_OP(
++		naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
+ 	int ret;
+ 
+ 	ret = spi_mem_exec_op(spinand->spimem, &op);
+@@ -760,24 +762,62 @@ static const struct spinand_manufacturer
+ 	&winbond_spinand_manufacturer,
+ };
+ 
+-static int spinand_manufacturer_detect(struct spinand_device *spinand)
++static int spinand_manufacturer_match(struct spinand_device *spinand,
++				      enum spinand_readid_method rdid_method)
+ {
++	u8 *id = spinand->id.data;
+ 	unsigned int i;
+ 	int ret;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
+-		ret = spinand_manufacturers[i]->ops->detect(spinand);
+-		if (ret > 0) {
+-			spinand->manufacturer = spinand_manufacturers[i];
+-			return 0;
+-		} else if (ret < 0) {
+-			return ret;
+-		}
+-	}
++		const struct spinand_manufacturer *manufacturer =
++			spinand_manufacturers[i];
++
++		if (id[0] != manufacturer->id)
++			continue;
+ 
++		ret = spinand_match_and_init(spinand,
++					     manufacturer->chips,
++					     manufacturer->nchips,
++					     rdid_method);
++		if (ret < 0)
++			continue;
++
++		spinand->manufacturer = manufacturer;
++		return 0;
++	}
+ 	return -ENOTSUPP;
+ }
+ 
++static int spinand_id_detect(struct spinand_device *spinand)
++{
++	u8 *id = spinand->id.data;
++	int ret;
++
++	ret = spinand_read_id_op(spinand, 0, 0, id);
++	if (ret)
++		return ret;
++	ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE);
++	if (!ret)
++		return 0;
++
++	ret = spinand_read_id_op(spinand, 1, 0, id);
++	if (ret)
++		return ret;
++	ret = spinand_manufacturer_match(spinand,
++					 SPINAND_READID_METHOD_OPCODE_ADDR);
++	if (!ret)
++		return 0;
++
++	ret = spinand_read_id_op(spinand, 0, 1, id);
++	if (ret)
++		return ret;
++	ret = spinand_manufacturer_match(spinand,
++					 SPINAND_READID_METHOD_OPCODE_DUMMY);
++
++	return ret;
++}
++
+ static int spinand_manufacturer_init(struct spinand_device *spinand)
+ {
+ 	if (spinand->manufacturer->ops->init)
+@@ -833,9 +873,9 @@ spinand_select_op_variant(struct spinand
+  * @spinand: SPI NAND object
+  * @table: SPI NAND device description table
+  * @table_size: size of the device description table
++ * @rdid_method: read id method to match
+  *
+- * Should be used by SPI NAND manufacturer drivers when they want to find a
+- * match between a device ID retrieved through the READ_ID command and an
++ * Match between a device ID retrieved through the READ_ID command and an
+  * entry in the SPI NAND description table. If a match is found, the spinand
+  * object will be initialized with information provided by the matching
+  * spinand_info entry.
+@@ -844,8 +884,10 @@ spinand_select_op_variant(struct spinand
+  */
+ int spinand_match_and_init(struct spinand_device *spinand,
+ 			   const struct spinand_info *table,
+-			   unsigned int table_size, u16 devid)
++			   unsigned int table_size,
++			   enum spinand_readid_method rdid_method)
+ {
++	u8 *id = spinand->id.data;
+ 	struct nand_device *nand = spinand_to_nand(spinand);
+ 	unsigned int i;
+ 
+@@ -853,13 +895,17 @@ int spinand_match_and_init(struct spinan
+ 		const struct spinand_info *info = &table[i];
+ 		const struct spi_mem_op *op;
+ 
+-		if (devid != info->devid)
++		if (rdid_method != info->devid.method)
++			continue;
++
++		if (memcmp(id + 1, info->devid.id, info->devid.len))
+ 			continue;
+ 
+ 		nand->memorg = table[i].memorg;
+ 		nand->eccreq = table[i].eccreq;
+ 		spinand->eccinfo = table[i].eccinfo;
+ 		spinand->flags = table[i].flags;
++		spinand->id.len = 1 + table[i].devid.len;
+ 		spinand->select_target = table[i].select_target;
+ 
+ 		op = spinand_select_op_variant(spinand,
+@@ -896,13 +942,7 @@ static int spinand_detect(struct spinand
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = spinand_read_id_op(spinand, spinand->id.data);
+-	if (ret)
+-		return ret;
+-
+-	spinand->id.len = SPINAND_MAX_ID_LEN;
+-
+-	ret = spinand_manufacturer_detect(spinand);
++	ret = spinand_id_detect(spinand);
+ 	if (ret) {
+ 		dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN,
+ 			spinand->id.data);
+Index: linux-5.4.260/include/linux/mtd/spinand.h
+===================================================================
+--- linux-5.4.260.orig/include/linux/mtd/spinand.h
++++ linux-5.4.260/include/linux/mtd/spinand.h
+@@ -32,9 +32,9 @@
+ 		   SPI_MEM_OP_NO_DUMMY,					\
+ 		   SPI_MEM_OP_NO_DATA)
+ 
+-#define SPINAND_READID_OP(ndummy, buf, len)				\
++#define SPINAND_READID_OP(naddr, ndummy, buf, len)			\
+ 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1),				\
+-		   SPI_MEM_OP_NO_ADDR,					\
++		   SPI_MEM_OP_ADDR(naddr, 0, 1),			\
+ 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
+ 		   SPI_MEM_OP_DATA_IN(len, buf, 1))
+ 
+@@ -176,37 +176,46 @@ struct spinand_device;
+  * @data: buffer containing the id bytes. Currently 4 bytes large, but can
+  *	  be extended if required
+  * @len: ID length
+- *
+- * struct_spinand_id->data contains all bytes returned after a READ_ID command,
+- * including dummy bytes if the chip does not emit ID bytes right after the
+- * READ_ID command. The responsibility to extract real ID bytes is left to
+- * struct_manufacurer_ops->detect().
+  */
+ struct spinand_id {
+ 	u8 data[SPINAND_MAX_ID_LEN];
+ 	int len;
+ };
+ 
++enum spinand_readid_method {
++	SPINAND_READID_METHOD_OPCODE,
++	SPINAND_READID_METHOD_OPCODE_ADDR,
++	SPINAND_READID_METHOD_OPCODE_DUMMY,
++};
++
++/**
++ * struct spinand_devid - SPI NAND device id structure
++ * @id: device id of current chip
++ * @len: number of bytes in device id
++ * @method: method to read chip id
++ *	    There are 3 possible variants:
++ *	    SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
++ *	    after read_id opcode.
++ *	    SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
++ *	    read_id opcode + 1-byte address.
++ *	    SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
++ *	    read_id opcode + 1 dummy byte.
++ */
++struct spinand_devid {
++	const u8 *id;
++	const u8 len;
++	const enum spinand_readid_method method;
++};
++
+ /**
+  * struct manufacurer_ops - SPI NAND manufacturer specific operations
+- * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed
+- *	    the core calls the struct_manufacurer_ops->detect() hook of each
+- *	    registered manufacturer until one of them return 1. Note that
+- *	    the first thing to check in this hook is that the manufacturer ID
+- *	    in struct_spinand_device->id matches the manufacturer whose
+- *	    ->detect() hook has been called. Should return 1 if there's a
+- *	    match, 0 if the manufacturer ID does not match and a negative
+- *	    error code otherwise. When true is returned, the core assumes
+- *	    that properties of the NAND chip (spinand->base.memorg and
+- *	    spinand->base.eccreq) have been filled
+  * @init: initialize a SPI NAND device
+  * @cleanup: cleanup a SPI NAND device
+  *
+  * Each SPI NAND manufacturer driver should implement this interface so that
+- * NAND chips coming from this vendor can be detected and initialized properly.
++ * NAND chips coming from this vendor can be initialized properly.
+  */
+ struct spinand_manufacturer_ops {
+-	int (*detect)(struct spinand_device *spinand);
+ 	int (*init)(struct spinand_device *spinand);
+ 	void (*cleanup)(struct spinand_device *spinand);
+ };
+@@ -215,11 +224,16 @@ struct spinand_manufacturer_ops {
+  * struct spinand_manufacturer - SPI NAND manufacturer instance
+  * @id: manufacturer ID
+  * @name: manufacturer name
++ * @devid_len: number of bytes in device ID
++ * @chips: supported SPI NANDs under current manufacturer
++ * @nchips: number of SPI NANDs available in chips array
+  * @ops: manufacturer operations
+  */
+ struct spinand_manufacturer {
+ 	u8 id;
+ 	char *name;
++	const struct spinand_info *chips;
++	const size_t nchips;
+ 	const struct spinand_manufacturer_ops *ops;
+ };
+ 
+@@ -270,6 +284,7 @@ struct spinand_ecc_info {
+ };
+ 
+ #define SPINAND_HAS_QE_BIT		BIT(0)
++#define SPINAND_HAS_CR_FEAT_BIT		BIT(1)
+ 
+ /**
+  * struct spinand_info - Structure used to describe SPI NAND chips
+@@ -291,7 +306,7 @@ struct spinand_ecc_info {
+  */
+ struct spinand_info {
+ 	const char *model;
+-	u16 devid;
++	struct spinand_devid devid;
+ 	u32 flags;
+ 	struct nand_memory_organization memorg;
+ 	struct nand_ecc_req eccreq;
+@@ -305,6 +320,13 @@ struct spinand_info {
+ 			     unsigned int target);
+ };
+ 
++#define SPINAND_ID(__method, ...)					\
++	{								\
++		.id = (const u8[]){ __VA_ARGS__ },			\
++		.len = sizeof((u8[]){ __VA_ARGS__ }),			\
++		.method = __method,					\
++	}
++
+ #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update)		\
+ 	{								\
+ 		.read_cache = __read,					\
+@@ -451,9 +473,10 @@ static inline void spinand_set_of_node(s
+ 	nanddev_set_of_node(&spinand->base, np);
+ }
+ 
+-int spinand_match_and_init(struct spinand_device *dev,
++int spinand_match_and_init(struct spinand_device *spinand,
+ 			   const struct spinand_info *table,
+-			   unsigned int table_size, u16 devid);
++			   unsigned int table_size,
++			   enum spinand_readid_method rdid_method);
+ 
+ int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
+ int spinand_select_target(struct spinand_device *spinand, unsigned int target);
+Index: linux-5.4.260/drivers/mtd/nand/spi/winbond.c
+===================================================================
+--- linux-5.4.260.orig/drivers/mtd/nand/spi/winbond.c
++++ linux-5.4.260/drivers/mtd/nand/spi/winbond.c
+@@ -75,7 +75,8 @@ static int w25m02gv_select_target(struct
+ }
+ 
+ static const struct spinand_info winbond_spinand_table[] = {
+-	SPINAND_INFO("W25M02GV", 0xAB,
++	SPINAND_INFO("W25M02GV",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab),
+ 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2),
+ 		     NAND_ECCREQ(1, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -84,7 +85,8 @@ static const struct spinand_info winbond
+ 		     0,
+ 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
+ 		     SPINAND_SELECT_TARGET(w25m02gv_select_target)),
+-	SPINAND_INFO("W25N01GV", 0xAA,
++	SPINAND_INFO("W25N01GV",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa),
+ 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ 		     NAND_ECCREQ(1, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -94,31 +96,6 @@ static const struct spinand_info winbond
+ 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
+ };
+ 
+-/**
+- * winbond_spinand_detect - initialize device related part in spinand_device
+- * struct if it is a Winbond device.
+- * @spinand: SPI NAND device structure
+- */
+-static int winbond_spinand_detect(struct spinand_device *spinand)
+-{
+-	u8 *id = spinand->id.data;
+-	int ret;
+-
+-	/*
+-	 * Winbond SPI NAND read ID need a dummy byte,
+-	 * so the first byte in raw_id is dummy.
+-	 */
+-	if (id[1] != SPINAND_MFR_WINBOND)
+-		return 0;
+-
+-	ret = spinand_match_and_init(spinand, winbond_spinand_table,
+-				     ARRAY_SIZE(winbond_spinand_table), id[2]);
+-	if (ret)
+-		return ret;
+-
+-	return 1;
+-}
+-
+ static int winbond_spinand_init(struct spinand_device *spinand)
+ {
+ 	struct nand_device *nand = spinand_to_nand(spinand);
+@@ -138,12 +115,13 @@ static int winbond_spinand_init(struct s
+ }
+ 
+ static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
+-	.detect = winbond_spinand_detect,
+ 	.init = winbond_spinand_init,
+ };
+ 
+ const struct spinand_manufacturer winbond_spinand_manufacturer = {
+ 	.id = SPINAND_MFR_WINBOND,
+ 	.name = "Winbond",
++	.chips = winbond_spinand_table,
++	.nchips = ARRAY_SIZE(winbond_spinand_table),
+ 	.ops = &winbond_spinand_manuf_ops,
+ };
diff --git a/21.02/files/target/linux/mediatek/patches-5.4/999-1402-v6.4-mtd-spinand-backport-series-flash.patch b/21.02/files/target/linux/mediatek/patches-5.4/999-1402-v6.4-mtd-spinand-backport-series-flash.patch
new file mode 100644
index 0000000..df4f9f9
--- /dev/null
+++ b/21.02/files/target/linux/mediatek/patches-5.4/999-1402-v6.4-mtd-spinand-backport-series-flash.patch
@@ -0,0 +1,1333 @@
+Index: linux-5.4.260/drivers/mtd/nand/spi/gigadevice.c
+===================================================================
+--- linux-5.4.260.orig/drivers/mtd/nand/spi/gigadevice.c
++++ linux-5.4.260/drivers/mtd/nand/spi/gigadevice.c
+@@ -13,7 +13,10 @@
+ #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS	(1 << 4)
+ #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS	(3 << 4)
+ 
+-#define GD5FXGQ4UEXXG_REG_STATUS2		0xf0
++#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS	(1 << 4)
++#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS	(3 << 4)
++
++#define GD5FXGQXXEXXG_REG_STATUS2		0xf0
+ 
+ #define GD5FXGQ4UXFXXG_STATUS_ECC_MASK		(7 << 4)
+ #define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS	(0 << 4)
+@@ -36,6 +39,22 @@ static SPINAND_OP_VARIANTS(read_cache_va
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
+ 
++static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
++		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
++
++static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
++		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
++
+ static SPINAND_OP_VARIANTS(write_cache_variants,
+ 		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+@@ -102,7 +121,7 @@ static int gd5fxgq4xa_ecc_get_status(str
+ 	return -EINVAL;
+ }
+ 
+-static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
++static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
+ 				       struct mtd_oob_region *region)
+ {
+ 	if (section)
+@@ -114,7 +133,7 @@ static int gd5fxgq4_variant2_ooblayout_e
+ 	return 0;
+ }
+ 
+-static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section,
++static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section,
+ 					struct mtd_oob_region *region)
+ {
+ 	if (section)
+@@ -127,16 +146,46 @@ static int gd5fxgq4_variant2_ooblayout_f
+ 	return 0;
+ }
+ 
+-static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = {
+-	.ecc = gd5fxgq4_variant2_ooblayout_ecc,
+-	.free = gd5fxgq4_variant2_ooblayout_free,
++/* Valid for Q4/Q5 and Q6 (untested) devices */
++static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = {
++	.ecc = gd5fxgqx_variant2_ooblayout_ecc,
++	.free = gd5fxgqx_variant2_ooblayout_free,
++};
++
++static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,
++					struct mtd_oob_region *oobregion)
++{
++	if (section)
++		return -ERANGE;
++
++	oobregion->offset = 128;
++	oobregion->length = 128;
++
++	return 0;
++}
++
++static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section,
++					 struct mtd_oob_region *oobregion)
++{
++	if (section)
++		return -ERANGE;
++
++	oobregion->offset = 1;
++	oobregion->length = 127;
++
++	return 0;
++}
++
++static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = {
++	.ecc = gd5fxgq4xc_ooblayout_256_ecc,
++	.free = gd5fxgq4xc_ooblayout_256_free,
+ };
+ 
+ static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
+ 					u8 status)
+ {
+ 	u8 status2;
+-	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2,
++	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
+ 						      &status2);
+ 	int ret;
+ 
+@@ -174,6 +223,43 @@ static int gd5fxgq4uexxg_ecc_get_status(
+ 	return -EINVAL;
+ }
+ 
++static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand,
++					u8 status)
++{
++	u8 status2;
++	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
++						      &status2);
++	int ret;
++
++	switch (status & STATUS_ECC_MASK) {
++	case STATUS_ECC_NO_BITFLIPS:
++		return 0;
++
++	case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS:
++		/*
++		 * Read status2 register to determine a more fine grained
++		 * bit error status
++		 */
++		ret = spi_mem_exec_op(spinand->spimem, &op);
++		if (ret)
++			return ret;
++
++		/*
++		 * 1 ... 4 bits are flipped (and corrected)
++		 */
++		/* bits sorted this way (1...0): ECCSE1, ECCSE0 */
++		return ((status2 & STATUS_ECC_MASK) >> 4) + 1;
++
++	case STATUS_ECC_UNCOR_ERROR:
++		return -EBADMSG;
++
++	default:
++		break;
++	}
++
++	return -EINVAL;
++}
++
+ static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
+ 					u8 status)
+ {
+@@ -195,7 +281,8 @@ static int gd5fxgq4ufxxg_ecc_get_status(
+ }
+ 
+ static const struct spinand_info gigadevice_spinand_table[] = {
+-	SPINAND_INFO("GD5F1GQ4xA", 0xF1,
++	SPINAND_INFO("GD5F1GQ4xA",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
+ 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -204,7 +291,8 @@ static const struct spinand_info gigadev
+ 		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
+ 				     gd5fxgq4xa_ecc_get_status)),
+-	SPINAND_INFO("GD5F2GQ4xA", 0xF2,
++	SPINAND_INFO("GD5F2GQ4xA",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2),
+ 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -213,7 +301,8 @@ static const struct spinand_info gigadev
+ 		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
+ 				     gd5fxgq4xa_ecc_get_status)),
+-	SPINAND_INFO("GD5F4GQ4xA", 0xF4,
++	SPINAND_INFO("GD5F4GQ4xA",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4),
+ 		     NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -222,59 +311,205 @@ static const struct spinand_info gigadev
+ 		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
+ 				     gd5fxgq4xa_ecc_get_status)),
+-	SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
++	SPINAND_INFO("GD5F4GQ4RC",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xa4, 0x68),
++		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
++				     gd5fxgq4ufxxg_ecc_get_status)),
++	SPINAND_INFO("GD5F4GQ4UC",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb4, 0x68),
++		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
++				     gd5fxgq4ufxxg_ecc_get_status)),
++	SPINAND_INFO("GD5F1GQ4UExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq4uexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F1GQ4RExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     SPINAND_HAS_QE_BIT,
+-		     SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq4uexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F2GQ4UExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ 				     gd5fxgq4uexxg_ecc_get_status)),
+-	SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148,
++	SPINAND_INFO("GD5F2GQ4RExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq4uexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F1GQ4UFxxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     SPINAND_HAS_QE_BIT,
+-		     SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ 				     gd5fxgq4ufxxg_ecc_get_status)),
++	SPINAND_INFO("GD5F1GQ5UExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq5xexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F1GQ5RExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq5xexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F2GQ5UExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq5xexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F2GQ5RExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq5xexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F4GQ6UExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq5xexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F4GQ6RExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq5xexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F1GM7UExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq4uexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F1GM7RExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq4uexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F2GM7UExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq4uexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F2GM7RExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq4uexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F4GM8UExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),
++		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq4uexxg_ecc_get_status)),
++	SPINAND_INFO("GD5F4GM8RExxG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),
++		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++				     gd5fxgq4uexxg_ecc_get_status)),
+ };
+ 
+-static int gigadevice_spinand_detect(struct spinand_device *spinand)
+-{
+-	u8 *id = spinand->id.data;
+-	u16 did;
+-	int ret;
+-
+-	/*
+-	 * Earlier GDF5-series devices (A,E) return [0][MID][DID]
+-	 * Later (F) devices return [MID][DID1][DID2]
+-	 */
+-
+-	if (id[0] == SPINAND_MFR_GIGADEVICE)
+-		did = (id[1] << 8) + id[2];
+-	else if (id[0] == 0 && id[1] == SPINAND_MFR_GIGADEVICE)
+-		did = id[2];
+-	else
+-		return 0;
+-
+-	ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
+-				     ARRAY_SIZE(gigadevice_spinand_table),
+-				     did);
+-	if (ret)
+-		return ret;
+-
+-	return 1;
+-}
+-
+ static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
+-	.detect = gigadevice_spinand_detect,
+ };
+ 
+ const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
+ 	.id = SPINAND_MFR_GIGADEVICE,
+ 	.name = "GigaDevice",
++	.chips = gigadevice_spinand_table,
++	.nchips = ARRAY_SIZE(gigadevice_spinand_table),
+ 	.ops = &gigadevice_spinand_manuf_ops,
+ };
+Index: linux-5.4.260/drivers/mtd/nand/spi/macronix.c
+===================================================================
+--- linux-5.4.260.orig/drivers/mtd/nand/spi/macronix.c
++++ linux-5.4.260/drivers/mtd/nand/spi/macronix.c
+@@ -99,7 +99,8 @@ static int mx35lf1ge4ab_ecc_get_status(s
+ }
+ 
+ static const struct spinand_info macronix_spinand_table[] = {
+-	SPINAND_INFO("MX35LF1GE4AB", 0x12,
++	SPINAND_INFO("MX35LF1GE4AB",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12),
+ 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ 		     NAND_ECCREQ(4, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -108,7 +109,8 @@ static const struct spinand_info macroni
+ 		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ 				     mx35lf1ge4ab_ecc_get_status)),
+-	SPINAND_INFO("MX35LF2GE4AB", 0x22,
++	SPINAND_INFO("MX35LF2GE4AB",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
+ 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
+ 		     NAND_ECCREQ(4, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -116,51 +118,194 @@ static const struct spinand_info macroni
+ 					      &update_cache_variants),
+ 		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
+-	SPINAND_INFO("MX35LF2GE4AD", 0x26,
++	SPINAND_INFO("MX35LF2GE4AD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x26),
+ 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX35LF4GE4AD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37),
++		     NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX35LF1G24AD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
+-	SPINAND_INFO("MX35LF4GE4AD", 0x37,
+-		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++	SPINAND_INFO("MX35LF2G24AD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
+-};
+-
+-static int macronix_spinand_detect(struct spinand_device *spinand)
+-{
+-	u8 *id = spinand->id.data;
+-	int ret;
+-
+-	/*
+-	 * Macronix SPI NAND read ID needs a dummy byte, so the first byte in
+-	 * raw_id is garbage.
+-	 */
+-	if (id[1] != SPINAND_MFR_MACRONIX)
+-		return 0;
++	SPINAND_INFO("MX35LF4G24AD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
++		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
++	SPINAND_INFO("MX31LF1GE4BC",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e),
++		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX31UF1GE4BC",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e),
++		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
+ 
+-	ret = spinand_match_and_init(spinand, macronix_spinand_table,
+-				     ARRAY_SIZE(macronix_spinand_table),
+-				     id[2]);
+-	if (ret)
+-		return ret;
++	SPINAND_INFO("MX35LF2G14AC",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20),
++		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX35UF4G24AD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5),
++		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX35UF4GE4AD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7),
++		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX35UF2G14AC",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0),
++		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX35UF2G24AD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX35UF2GE4AD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX35UF2GE4AC",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2),
++		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX35UF1G14AC",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90),
++		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX35UF1G24AD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX35UF1GE4AD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
++	SPINAND_INFO("MX35UF1GE4AC",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
++		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
++				     mx35lf1ge4ab_ecc_get_status)),
+ 
+-	return 1;
+-}
++};
+ 
+ static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
+-	.detect = macronix_spinand_detect,
+ };
+ 
+ const struct spinand_manufacturer macronix_spinand_manufacturer = {
+ 	.id = SPINAND_MFR_MACRONIX,
+ 	.name = "Macronix",
++	.chips = macronix_spinand_table,
++	.nchips = ARRAY_SIZE(macronix_spinand_table),
+ 	.ops = &macronix_spinand_manuf_ops,
+ };
+Index: linux-5.4.260/drivers/mtd/nand/spi/micron.c
+===================================================================
+--- linux-5.4.260.orig/drivers/mtd/nand/spi/micron.c
++++ linux-5.4.260/drivers/mtd/nand/spi/micron.c
+@@ -12,13 +12,23 @@
+ 
+ #define SPINAND_MFR_MICRON		0x2c
+ 
+-#define MICRON_STATUS_ECC_MASK		GENMASK(6, 4)
++#define MICRON_STATUS_ECC_MASK		GENMASK(7, 4)
+ #define MICRON_STATUS_ECC_NO_BITFLIPS	(0 << 4)
+ #define MICRON_STATUS_ECC_1TO3_BITFLIPS	(1 << 4)
+ #define MICRON_STATUS_ECC_4TO6_BITFLIPS	(3 << 4)
+ #define MICRON_STATUS_ECC_7TO8_BITFLIPS	(5 << 4)
+ 
+-static SPINAND_OP_VARIANTS(read_cache_variants,
++#define MICRON_CFG_CR			BIT(0)
++
++/*
++ * As per datasheet, die selection is done by the 6th bit of Die
++ * Select Register (Address 0xD0).
++ */
++#define MICRON_DIE_SELECT_REG	0xD0
++
++#define MICRON_SELECT_DIE(x)	((x) << 6)
++
++static SPINAND_OP_VARIANTS(quadio_read_cache_variants,
+ 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ 		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+@@ -26,46 +36,114 @@ static SPINAND_OP_VARIANTS(read_cache_va
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+ 
+-static SPINAND_OP_VARIANTS(write_cache_variants,
++static SPINAND_OP_VARIANTS(x4_write_cache_variants,
+ 		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+ 
+-static SPINAND_OP_VARIANTS(update_cache_variants,
++static SPINAND_OP_VARIANTS(x4_update_cache_variants,
+ 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
+ 
+-static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
+-					struct mtd_oob_region *region)
++/* Micron  MT29F2G01AAAED Device */
++static SPINAND_OP_VARIANTS(x4_read_cache_variants,
++			   SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
++			   SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
++			   SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
++			   SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
++
++static SPINAND_OP_VARIANTS(x1_write_cache_variants,
++			   SPINAND_PROG_LOAD(true, 0, NULL, 0));
++
++static SPINAND_OP_VARIANTS(x1_update_cache_variants,
++			   SPINAND_PROG_LOAD(false, 0, NULL, 0));
++
++static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section,
++				  struct mtd_oob_region *region)
+ {
+ 	if (section)
+ 		return -ERANGE;
+ 
+-	region->offset = 64;
+-	region->length = 64;
++	region->offset = mtd->oobsize / 2;
++	region->length = mtd->oobsize / 2;
+ 
+ 	return 0;
+ }
+ 
+-static int mt29f2g01abagd_ooblayout_free(struct mtd_info *mtd, int section,
+-					 struct mtd_oob_region *region)
++static int micron_8_ooblayout_free(struct mtd_info *mtd, int section,
++				   struct mtd_oob_region *region)
+ {
+ 	if (section)
+ 		return -ERANGE;
+ 
+ 	/* Reserve 2 bytes for the BBM. */
+ 	region->offset = 2;
+-	region->length = 62;
++	region->length = (mtd->oobsize / 2) - 2;
++
++	return 0;
++}
++
++static const struct mtd_ooblayout_ops micron_8_ooblayout = {
++	.ecc = micron_8_ooblayout_ecc,
++	.free = micron_8_ooblayout_free,
++};
++
++static int micron_4_ooblayout_ecc(struct mtd_info *mtd, int section,
++				  struct mtd_oob_region *region)
++{
++	struct spinand_device *spinand = mtd_to_spinand(mtd);
++
++	if (section >= spinand->base.memorg.pagesize /
++			mtd->ecc_step_size)
++		return -ERANGE;
++
++	region->offset = (section * 16) + 8;
++	region->length = 8;
++
++	return 0;
++}
++
++static int micron_4_ooblayout_free(struct mtd_info *mtd, int section,
++				   struct mtd_oob_region *region)
++{
++	struct spinand_device *spinand = mtd_to_spinand(mtd);
++
++	if (section >= spinand->base.memorg.pagesize /
++			mtd->ecc_step_size)
++		return -ERANGE;
++
++	if (section) {
++		region->offset = 16 * section;
++		region->length = 8;
++	} else {
++		/* section 0 has two bytes reserved for the BBM */
++		region->offset = 2;
++		region->length = 6;
++	}
+ 
+ 	return 0;
+ }
+ 
+-static const struct mtd_ooblayout_ops mt29f2g01abagd_ooblayout = {
+-	.ecc = mt29f2g01abagd_ooblayout_ecc,
+-	.free = mt29f2g01abagd_ooblayout_free,
++static const struct mtd_ooblayout_ops micron_4_ooblayout = {
++	.ecc = micron_4_ooblayout_ecc,
++	.free = micron_4_ooblayout_free,
+ };
+ 
+-static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
+-					 u8 status)
++static int micron_select_target(struct spinand_device *spinand,
++				unsigned int target)
++{
++	struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG,
++						      spinand->scratchbuf);
++
++	if (target > 1)
++		return -EINVAL;
++
++	*spinand->scratchbuf = MICRON_SELECT_DIE(target);
++
++	return spi_mem_exec_op(spinand->spimem, &op);
++}
++
++static int micron_8_ecc_get_status(struct spinand_device *spinand,
++				   u8 status)
+ {
+ 	switch (status & MICRON_STATUS_ECC_MASK) {
+ 	case STATUS_ECC_NO_BITFLIPS:
+@@ -91,43 +169,141 @@ static int mt29f2g01abagd_ecc_get_status
+ }
+ 
+ static const struct spinand_info micron_spinand_table[] = {
+-	SPINAND_INFO("MT29F2G01ABAGD", 0x24,
++	/* M79A 2Gb 3.3V */
++	SPINAND_INFO("MT29F2G01ABAGD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+-		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+-					      &write_cache_variants,
+-					      &update_cache_variants),
++		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
++					      &x4_write_cache_variants,
++					      &x4_update_cache_variants),
++		     0,
++		     SPINAND_ECCINFO(&micron_8_ooblayout,
++				     micron_8_ecc_get_status)),
++	/* M79A 2Gb 1.8V */
++	SPINAND_INFO("MT29F2G01ABBGD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
++					      &x4_write_cache_variants,
++					      &x4_update_cache_variants),
++		     0,
++		     SPINAND_ECCINFO(&micron_8_ooblayout,
++				     micron_8_ecc_get_status)),
++	/* M78A 1Gb 3.3V */
++	SPINAND_INFO("MT29F1G01ABAFD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
++					      &x4_write_cache_variants,
++					      &x4_update_cache_variants),
++		     0,
++		     SPINAND_ECCINFO(&micron_8_ooblayout,
++				     micron_8_ecc_get_status)),
++	/* M78A 1Gb 1.8V */
++	SPINAND_INFO("MT29F1G01ABAFD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
++					      &x4_write_cache_variants,
++					      &x4_update_cache_variants),
++		     0,
++		     SPINAND_ECCINFO(&micron_8_ooblayout,
++				     micron_8_ecc_get_status)),
++	/* M79A 4Gb 3.3V */
++	SPINAND_INFO("MT29F4G01ADAGD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
++					      &x4_write_cache_variants,
++					      &x4_update_cache_variants),
++		     0,
++		     SPINAND_ECCINFO(&micron_8_ooblayout,
++				     micron_8_ecc_get_status),
++		     SPINAND_SELECT_TARGET(micron_select_target)),
++	/* M70A 4Gb 3.3V */
++	SPINAND_INFO("MT29F4G01ABAFD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
++		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
++					      &x4_write_cache_variants,
++					      &x4_update_cache_variants),
++		     SPINAND_HAS_CR_FEAT_BIT,
++		     SPINAND_ECCINFO(&micron_8_ooblayout,
++				     micron_8_ecc_get_status)),
++	/* M70A 4Gb 1.8V */
++	SPINAND_INFO("MT29F4G01ABBFD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
++		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
++					      &x4_write_cache_variants,
++					      &x4_update_cache_variants),
++		     SPINAND_HAS_CR_FEAT_BIT,
++		     SPINAND_ECCINFO(&micron_8_ooblayout,
++				     micron_8_ecc_get_status)),
++	/* M70A 8Gb 3.3V */
++	SPINAND_INFO("MT29F8G01ADAFD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
++		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
++					      &x4_write_cache_variants,
++					      &x4_update_cache_variants),
++		     SPINAND_HAS_CR_FEAT_BIT,
++		     SPINAND_ECCINFO(&micron_8_ooblayout,
++				     micron_8_ecc_get_status),
++		     SPINAND_SELECT_TARGET(micron_select_target)),
++	/* M70A 8Gb 1.8V */
++	SPINAND_INFO("MT29F8G01ADBFD",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
++		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
++					      &x4_write_cache_variants,
++					      &x4_update_cache_variants),
++		     SPINAND_HAS_CR_FEAT_BIT,
++		     SPINAND_ECCINFO(&micron_8_ooblayout,
++				     micron_8_ecc_get_status),
++		     SPINAND_SELECT_TARGET(micron_select_target)),
++	/* M69A 2Gb 3.3V */
++	SPINAND_INFO("MT29F2G01AAAED",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9F),
++		     NAND_MEMORG(1, 2048, 64, 64, 2048, 80, 2, 1, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&x4_read_cache_variants,
++					      &x1_write_cache_variants,
++					      &x1_update_cache_variants),
+ 		     0,
+-		     SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
+-				     mt29f2g01abagd_ecc_get_status)),
++		     SPINAND_ECCINFO(&micron_4_ooblayout, NULL)),
+ };
+ 
+-static int micron_spinand_detect(struct spinand_device *spinand)
++static int micron_spinand_init(struct spinand_device *spinand)
+ {
+-	u8 *id = spinand->id.data;
+-	int ret;
+-
+ 	/*
+-	 * Micron SPI NAND read ID need a dummy byte,
+-	 * so the first byte in raw_id is dummy.
++	 * M70A device series enable Continuous Read feature at Power-up,
++	 * which is not supported. Disable this bit to avoid any possible
++	 * failure.
+ 	 */
+-	if (id[1] != SPINAND_MFR_MICRON)
+-		return 0;
+-
+-	ret = spinand_match_and_init(spinand, micron_spinand_table,
+-				     ARRAY_SIZE(micron_spinand_table), id[2]);
+-	if (ret)
+-		return ret;
++	if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT)
++		return spinand_upd_cfg(spinand, MICRON_CFG_CR, 0);
+ 
+-	return 1;
++	return 0;
+ }
+ 
+ static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
+-	.detect = micron_spinand_detect,
++	.init = micron_spinand_init,
+ };
+ 
+ const struct spinand_manufacturer micron_spinand_manufacturer = {
+ 	.id = SPINAND_MFR_MICRON,
+ 	.name = "Micron",
++	.chips = micron_spinand_table,
++	.nchips = ARRAY_SIZE(micron_spinand_table),
+ 	.ops = &micron_spinand_manuf_ops,
+ };
+Index: linux-5.4.260/drivers/mtd/nand/spi/paragon.c
+===================================================================
+--- linux-5.4.260.orig/drivers/mtd/nand/spi/paragon.c
++++ linux-5.4.260/drivers/mtd/nand/spi/paragon.c
+@@ -97,7 +97,8 @@ static const struct mtd_ooblayout_ops pn
+ 
+ 
+ static const struct spinand_info paragon_spinand_table[] = {
+-	SPINAND_INFO("PN26G01A", 0xe1,
++	SPINAND_INFO("PN26G01A",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe1),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 21, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -106,7 +107,8 @@ static const struct spinand_info paragon
+ 		     0,
+ 		     SPINAND_ECCINFO(&pn26g0xa_ooblayout,
+ 				     pn26g0xa_ecc_get_status)),
+-	SPINAND_INFO("PN26G02A", 0xe2,
++	SPINAND_INFO("PN26G02A",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe2),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 41, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -117,31 +119,13 @@ static const struct spinand_info paragon
+ 				     pn26g0xa_ecc_get_status)),
+ };
+ 
+-static int paragon_spinand_detect(struct spinand_device *spinand)
+-{
+-	u8 *id = spinand->id.data;
+-	int ret;
+-
+-	/* Read ID returns [0][MID][DID] */
+-
+-	if (id[1] != SPINAND_MFR_PARAGON)
+-		return 0;
+-
+-	ret = spinand_match_and_init(spinand, paragon_spinand_table,
+-				     ARRAY_SIZE(paragon_spinand_table),
+-				     id[2]);
+-	if (ret)
+-		return ret;
+-
+-	return 1;
+-}
+-
+ static const struct spinand_manufacturer_ops paragon_spinand_manuf_ops = {
+-	.detect = paragon_spinand_detect,
+ };
+ 
+ const struct spinand_manufacturer paragon_spinand_manufacturer = {
+ 	.id = SPINAND_MFR_PARAGON,
+ 	.name = "Paragon",
++	.chips = paragon_spinand_table,
++	.nchips = ARRAY_SIZE(paragon_spinand_table),
+ 	.ops = &paragon_spinand_manuf_ops,
+ };
+Index: linux-5.4.260/drivers/mtd/nand/spi/toshiba.c
+===================================================================
+--- linux-5.4.260.orig/drivers/mtd/nand/spi/toshiba.c
++++ linux-5.4.260/drivers/mtd/nand/spi/toshiba.c
+@@ -10,6 +10,7 @@
+ #include <linux/kernel.h>
+ #include <linux/mtd/spinand.h>
+ 
++/* Kioxia is new name of Toshiba memory. */
+ #define SPINAND_MFR_TOSHIBA		0x98
+ #define TOSH_STATUS_ECC_HAS_BITFLIPS_T	(3 << 4)
+ 
+@@ -19,14 +20,26 @@ static SPINAND_OP_VARIANTS(read_cache_va
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+ 
++static SPINAND_OP_VARIANTS(write_cache_x4_variants,
++		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
++		SPINAND_PROG_LOAD(true, 0, NULL, 0));
++
++static SPINAND_OP_VARIANTS(update_cache_x4_variants,
++		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
++		SPINAND_PROG_LOAD(false, 0, NULL, 0));
++
++/*
++ * Backward compatibility for 1st generation Serial NAND devices
++ * which don't support Quad Program Load operation.
++ */
+ static SPINAND_OP_VARIANTS(write_cache_variants,
+ 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+ 
+ static SPINAND_OP_VARIANTS(update_cache_variants,
+ 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
+ 
+-static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section,
+-				     struct mtd_oob_region *region)
++static int tx58cxgxsxraix_ooblayout_ecc(struct mtd_info *mtd, int section,
++					struct mtd_oob_region *region)
+ {
+ 	if (section > 0)
+ 		return -ERANGE;
+@@ -37,8 +50,8 @@ static int tc58cxgxsx_ooblayout_ecc(stru
+ 	return 0;
+ }
+ 
+-static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section,
+-				      struct mtd_oob_region *region)
++static int tx58cxgxsxraix_ooblayout_free(struct mtd_info *mtd, int section,
++					 struct mtd_oob_region *region)
+ {
+ 	if (section > 0)
+ 		return -ERANGE;
+@@ -50,13 +63,13 @@ static int tc58cxgxsx_ooblayout_free(str
+ 	return 0;
+ }
+ 
+-static const struct mtd_ooblayout_ops tc58cxgxsx_ooblayout = {
+-	.ecc = tc58cxgxsx_ooblayout_ecc,
+-	.free = tc58cxgxsx_ooblayout_free,
++static const struct mtd_ooblayout_ops tx58cxgxsxraix_ooblayout = {
++	.ecc = tx58cxgxsxraix_ooblayout_ecc,
++	.free = tx58cxgxsxraix_ooblayout_free,
+ };
+ 
+-static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand,
+-				      u8 status)
++static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
++					 u8 status)
+ {
+ 	struct nand_device *nand = spinand_to_nand(spinand);
+ 	u8 mbf = 0;
+@@ -94,95 +107,174 @@ static int tc58cxgxsx_ecc_get_status(str
+ }
+ 
+ static const struct spinand_info toshiba_spinand_table[] = {
+-	/* 3.3V 1Gb */
+-	SPINAND_INFO("TC58CVG0S3", 0xC2,
++	/* 3.3V 1Gb (1st generation) */
++	SPINAND_INFO("TC58CVG0S3HRAIG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     0,
+-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+-				     tc58cxgxsx_ecc_get_status)),
+-	/* 3.3V 2Gb */
+-	SPINAND_INFO("TC58CVG1S3", 0xCB,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++	/* 3.3V 2Gb (1st generation) */
++	SPINAND_INFO("TC58CVG1S3HRAIG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     0,
+-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+-				     tc58cxgxsx_ecc_get_status)),
+-	/* 3.3V 4Gb */
+-	SPINAND_INFO("TC58CVG2S0", 0xCD,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++	/* 3.3V 4Gb (1st generation) */
++	SPINAND_INFO("TC58CVG2S0HRAIG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD),
+ 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     0,
+-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+-				     tc58cxgxsx_ecc_get_status)),
+-	/* 1.8V 1Gb */
+-	SPINAND_INFO("TC58CYG0S3", 0xB2,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++	/* 1.8V 1Gb (1st generation) */
++	SPINAND_INFO("TC58CYG0S3HRAIG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     0,
+-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+-				     tc58cxgxsx_ecc_get_status)),
+-	/* 1.8V 2Gb */
+-	SPINAND_INFO("TC58CYG1S3", 0xBB,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++	/* 1.8V 2Gb (1st generation) */
++	SPINAND_INFO("TC58CYG1S3HRAIG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     0,
+-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+-				     tc58cxgxsx_ecc_get_status)),
+-	/* 1.8V 4Gb */
+-	SPINAND_INFO("TC58CYG2S0", 0xBD,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++	/* 1.8V 4Gb (1st generation) */
++	SPINAND_INFO("TC58CYG2S0HRAIG",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD),
+ 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     0,
+-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
+-				     tc58cxgxsx_ecc_get_status)),
+-};
+-
+-static int toshiba_spinand_detect(struct spinand_device *spinand)
+-{
+-	u8 *id = spinand->id.data;
+-	int ret;
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
+ 
+ 	/*
+-	 * Toshiba SPI NAND read ID needs a dummy byte,
+-	 * so the first byte in id is garbage.
++	 * 2nd generation serial nand has HOLD_D which is equivalent to
++	 * QE_BIT.
+ 	 */
+-	if (id[1] != SPINAND_MFR_TOSHIBA)
+-		return 0;
+-
+-	ret = spinand_match_and_init(spinand, toshiba_spinand_table,
+-				     ARRAY_SIZE(toshiba_spinand_table),
+-				     id[2]);
+-	if (ret)
+-		return ret;
+-
+-	return 1;
+-}
++	/* 3.3V 1Gb (2nd generation) */
++	SPINAND_INFO("TC58CVG0S3HRAIJ",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_x4_variants,
++					      &update_cache_x4_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++	/* 3.3V 2Gb (2nd generation) */
++	SPINAND_INFO("TC58CVG1S3HRAIJ",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_x4_variants,
++					      &update_cache_x4_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++	/* 3.3V 4Gb (2nd generation) */
++	SPINAND_INFO("TC58CVG2S0HRAIJ",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED),
++		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_x4_variants,
++					      &update_cache_x4_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++	/* 3.3V 8Gb (2nd generation) */
++	SPINAND_INFO("TH58CVG3S0HRAIJ",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
++		     NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_x4_variants,
++					      &update_cache_x4_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++	/* 1.8V 1Gb (2nd generation) */
++	SPINAND_INFO("TC58CYG0S3HRAIJ",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_x4_variants,
++					      &update_cache_x4_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++	/* 1.8V 2Gb (2nd generation) */
++	SPINAND_INFO("TC58CYG1S3HRAIJ",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_x4_variants,
++					      &update_cache_x4_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++	/* 1.8V 4Gb (2nd generation) */
++	SPINAND_INFO("TC58CYG2S0HRAIJ",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD),
++		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_x4_variants,
++					      &update_cache_x4_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++	/* 1.8V 8Gb (2nd generation) */
++	SPINAND_INFO("TH58CYG3S0HRAIJ",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
++		     NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_x4_variants,
++					      &update_cache_x4_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++				     tx58cxgxsxraix_ecc_get_status)),
++};
+ 
+ static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
+-	.detect = toshiba_spinand_detect,
+ };
+ 
+ const struct spinand_manufacturer toshiba_spinand_manufacturer = {
+ 	.id = SPINAND_MFR_TOSHIBA,
+ 	.name = "Toshiba",
++	.chips = toshiba_spinand_table,
++	.nchips = ARRAY_SIZE(toshiba_spinand_table),
+ 	.ops = &toshiba_spinand_manuf_ops,
+ };
diff --git a/21.02/files/target/linux/mediatek/patches-5.4/999-2330-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-series.patch b/21.02/files/target/linux/mediatek/patches-5.4/999-2330-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-series.patch
index 42467b6..3666b6b 100644
--- a/21.02/files/target/linux/mediatek/patches-5.4/999-2330-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-series.patch
+++ b/21.02/files/target/linux/mediatek/patches-5.4/999-2330-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-series.patch
@@ -1,17 +1,7 @@
-From 2c71a01b9363f44ca077ec0e27b6a06a15617497 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:14 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2330-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-series.patch]
-
----
- drivers/mtd/nand/spi/winbond.c | 129 ++++++++++++++++++++++++++++++++-
- 1 file changed, 127 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
-index 766844283..6473b0367 100644
---- a/drivers/mtd/nand/spi/winbond.c
-+++ b/drivers/mtd/nand/spi/winbond.c
+Index: linux-5.4.260/drivers/mtd/nand/spi/winbond.c
+===================================================================
+--- linux-5.4.260.orig/drivers/mtd/nand/spi/winbond.c
++++ linux-5.4.260/drivers/mtd/nand/spi/winbond.c
 @@ -15,6 +15,23 @@
  
  #define WINBOND_CFG_BUF_READ		BIT(3)
@@ -36,7 +26,7 @@
  static SPINAND_OP_VARIANTS(read_cache_variants,
  		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
  		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-@@ -31,6 +48,29 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
+@@ -31,6 +48,29 @@ static SPINAND_OP_VARIANTS(update_cache_
  		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
  		SPINAND_PROG_LOAD(false, 0, NULL, 0));
  
@@ -66,7 +56,7 @@
  static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
  				  struct mtd_oob_region *region)
  {
-@@ -74,9 +114,61 @@ static int w25m02gv_select_target(struct spinand_device *spinand,
+@@ -74,9 +114,61 @@ static int w25m02gv_select_target(struct
  	return spi_mem_exec_op(spinand->spimem, &op);
  }
  
@@ -129,7 +119,7 @@
  		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2),
  		     NAND_ECCREQ(1, 512),
  		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -85,8 +177,18 @@ static const struct spinand_info winbond_spinand_table[] = {
+@@ -85,8 +177,18 @@ static const struct spinand_info winbond
  		     0,
  		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
  		     SPINAND_SELECT_TARGET(w25m02gv_select_target)),
@@ -149,7 +139,7 @@
  		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
  		     NAND_ECCREQ(1, 512),
  		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -94,6 +196,29 @@ static const struct spinand_info winbond_spinand_table[] = {
+@@ -94,6 +196,29 @@ static const struct spinand_info winbond
  					      &update_cache_variants),
  		     0,
  		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
@@ -179,6 +169,3 @@
  };
  
  static int winbond_spinand_init(struct spinand_device *spinand)
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/mediatek/patches-5.4/999-2331-mtd-spinand-macronix-suppress-mx35lf1ge4ab-warning-log.patch b/21.02/files/target/linux/mediatek/patches-5.4/999-2331-mtd-spinand-macronix-suppress-mx35lf1ge4ab-warning-log.patch
index b19492b..e21b097 100644
--- a/21.02/files/target/linux/mediatek/patches-5.4/999-2331-mtd-spinand-macronix-suppress-mx35lf1ge4ab-warning-log.patch
+++ b/21.02/files/target/linux/mediatek/patches-5.4/999-2331-mtd-spinand-macronix-suppress-mx35lf1ge4ab-warning-log.patch
@@ -1,18 +1,8 @@
-From 6d8d4dc76ac31cfdecef99c72aad6a65f963d4a0 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:14 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2331-mtd-spinand-macronix-suppress-mx35lf1ge4ab-warning-log.patch]
-
----
- drivers/mtd/nand/spi/macronix.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
-index 25319b4f8..d3ae24ecc 100644
---- a/drivers/mtd/nand/spi/macronix.c
-+++ b/drivers/mtd/nand/spi/macronix.c
-@@ -86,7 +86,7 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand,
+Index: linux-5.4.260/drivers/mtd/nand/spi/macronix.c
+===================================================================
+--- linux-5.4.260.orig/drivers/mtd/nand/spi/macronix.c
++++ linux-5.4.260/drivers/mtd/nand/spi/macronix.c
+@@ -86,7 +86,7 @@ static int mx35lf1ge4ab_ecc_get_status(s
  		if (mx35lf1ge4ab_get_eccsr(spinand, &eccsr))
  			return nand->eccreq.strength;
  
@@ -21,6 +11,3 @@
  			return nand->eccreq.strength;
  
  		return eccsr;
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/mediatek/patches-5.4/999-2339-drivers-mtd-spinand-Add-calibration-support-for-spinand.patch b/21.02/files/target/linux/mediatek/patches-5.4/999-2339-drivers-mtd-spinand-Add-calibration-support-for-spinand.patch
index cf785fe..4a36657 100644
--- a/21.02/files/target/linux/mediatek/patches-5.4/999-2339-drivers-mtd-spinand-Add-calibration-support-for-spinand.patch
+++ b/21.02/files/target/linux/mediatek/patches-5.4/999-2339-drivers-mtd-spinand-Add-calibration-support-for-spinand.patch
@@ -1,18 +1,8 @@
-From ddd2951e2f35477a81fb882a976a5a1fe981883d Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:17 +0800
-Subject: [PATCH] 
- [spi-and-storage][999-2339-drivers-mtd-spinand-Add-calibration-support-for-spinand.patch]
-
----
- drivers/mtd/nand/spi/core.c | 58 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 58 insertions(+)
-
-diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
-index 9f5f95ff7..b346c7a8a 100644
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -789,6 +789,60 @@ static int spinand_manufacturer_match(struct spinand_device *spinand,
+Index: linux-5.4.260/drivers/mtd/nand/spi/core.c
+===================================================================
+--- linux-5.4.260.orig/drivers/mtd/nand/spi/core.c
++++ linux-5.4.260/drivers/mtd/nand/spi/core.c
+@@ -789,6 +789,60 @@ static int spinand_manufacturer_match(st
  	return -ENOTSUPP;
  }
  
@@ -73,7 +63,7 @@
  static int spinand_id_detect(struct spinand_device *spinand)
  {
  	u8 *id = spinand->id.data;
-@@ -1004,6 +1058,10 @@ static int spinand_init(struct spinand_device *spinand)
+@@ -1004,6 +1058,10 @@ static int spinand_init(struct spinand_d
  	if (!spinand->scratchbuf)
  		return -ENOMEM;
  
@@ -84,6 +74,3 @@
  	ret = spinand_detect(spinand);
  	if (ret)
  		goto err_free_bufs;
--- 
-2.34.1
-
diff --git a/21.02/files/target/linux/mediatek/patches-5.4/999-2343-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB.patch b/21.02/files/target/linux/mediatek/patches-5.4/999-2343-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB.patch
index acf4775..084073d 100644
--- a/21.02/files/target/linux/mediatek/patches-5.4/999-2343-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB.patch
+++ b/21.02/files/target/linux/mediatek/patches-5.4/999-2343-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB.patch
@@ -1,7 +1,7 @@
-Index: linux-5.4.246/drivers/mtd/nand/spi/gigadevice.c
+Index: linux-5.4.260/drivers/mtd/nand/spi/gigadevice.c
 ===================================================================
---- linux-5.4.246.orig/drivers/mtd/nand/spi/gigadevice.c
-+++ linux-5.4.246/drivers/mtd/nand/spi/gigadevice.c
+--- linux-5.4.260.orig/drivers/mtd/nand/spi/gigadevice.c
++++ linux-5.4.260/drivers/mtd/nand/spi/gigadevice.c
 @@ -281,6 +281,15 @@ static int gd5fxgq4ufxxg_ecc_get_status(
  }