[][openwrt][mt7988][pce][fix coverity defects]
[Description]
Fix PCE coverity defects
[Release-log]
N/A
Change-Id: I5137ce74b7358d74d58031dd9c8b82d446bbc5db
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/8289365
diff --git a/package-21.02/kernel/pce/src/debugfs.c b/package-21.02/kernel/pce/src/debugfs.c
index 6596413..fce9b92 100644
--- a/package-21.02/kernel/pce/src/debugfs.c
+++ b/package-21.02/kernel/pce/src/debugfs.c
@@ -404,7 +404,7 @@
u32 idx = 0;
int ret;
- if (count > sizeof(buf))
+ if (count > sizeof(buf) - 1)
return -ENOMEM;
if (copy_from_user(buf, buffer, count))
@@ -491,7 +491,7 @@
char s_dip[40];
int ret;
- if (count > sizeof(buf))
+ if (count > sizeof(buf) - 1)
return -ENOMEM;
if (copy_from_user(buf, buffer, count))
@@ -501,7 +501,7 @@
memset(&ddesc, 0, sizeof(struct dip_desc));
- ret = sscanf(buf, "%s %s", arg, s_dip);
+ ret = sscanf(buf, "%4s %39s", arg, s_dip);
if (ret != 2)
return -EINVAL;
@@ -551,7 +551,7 @@
seq_printf(s, "default CDRT_IDX: %02u, ", tdesc.cdrt_idx);
seq_printf(s, "default TOPS_ENTRY: %02u\n", tdesc.tops_entry);
} else if (PSE_PORT_PPE_MASK & BIT(i)) {
- ret = mtk_pce_tport_map_ppe_read(i, &map);
+ ret = mtk_pce_tport_map_ppe_read((enum pse_port)i, &map);
if (ret)
return ret;
@@ -627,7 +627,7 @@
int nchar = 0;
int ret;
- if (count > sizeof(buf))
+ if (count > sizeof(buf) - 1)
return -ENOMEM;
if (copy_from_user(buf, buffer, count))
diff --git a/package-21.02/kernel/pce/src/inc/pce/netsys.h b/package-21.02/kernel/pce/src/inc/pce/netsys.h
index f3ecd0e..c5088b8 100644
--- a/package-21.02/kernel/pce/src/inc/pce/netsys.h
+++ b/package-21.02/kernel/pce/src/inc/pce/netsys.h
@@ -43,6 +43,7 @@
/* TPORT setting etc. */
#define TPORT_IDX_MAX (16)
+#define TPORT_IDX_PER_REG (8)
#define TS_CONFIG_MASK (0xE746)
#define PSE_PORT_PPE_MASK (BIT(PSE_PORT_PPE0) \
| BIT(PSE_PORT_PPE1) \
diff --git a/package-21.02/kernel/pce/src/tport_map.c b/package-21.02/kernel/pce/src/tport_map.c
index 0350be6..b0d6d27 100644
--- a/package-21.02/kernel/pce/src/tport_map.c
+++ b/package-21.02/kernel/pce/src/tport_map.c
@@ -88,6 +88,9 @@
u32 tport_idx,
enum pse_port target)
{
+ u32 shift = (tport_idx % TPORT_IDX_PER_REG) * PSE_PER_PORT_BITS;
+ u32 val = (target & PSE_PER_PORT_MASK) << shift;
+ u32 mask = PSE_PER_PORT_MASK << shift;
struct tsc_desc ts_cfg;
int ret = 0;
@@ -96,11 +99,11 @@
return ret;
if (tport_idx < TPORT_IDX_MAX / 2) {
- ts_cfg.tport_map_lower &= (~(0xF << (tport_idx * PSE_PER_PORT_BITS)));
- ts_cfg.tport_map_lower |= (target << (tport_idx * PSE_PER_PORT_BITS));
+ ts_cfg.tport_map_lower &= ~mask;
+ ts_cfg.tport_map_lower |= val;
} else {
- ts_cfg.tport_map_upper &= (~(0xF << (tport_idx * PSE_PER_PORT_BITS)));
- ts_cfg.tport_map_upper |= (target << (tport_idx * PSE_PER_PORT_BITS));
+ ts_cfg.tport_map_upper &= ~mask;
+ ts_cfg.tport_map_upper |= val;
}
ret = mtk_pce_tport_map_ts_config_write(entry, &ts_cfg);
@@ -114,10 +117,9 @@
u32 tport_idx,
enum pse_port target)
{
- u32 mask = (PSE_PER_PORT_MASK
- << ((tport_idx % (TPORT_IDX_MAX / 2)) * PSE_PER_PORT_BITS));
- u32 val = ((target & PSE_PER_PORT_MASK)
- << ((tport_idx % (TPORT_IDX_MAX / 2)) * PSE_PER_PORT_BITS));
+ u32 shift = (tport_idx % TPORT_IDX_PER_REG) * PSE_PER_PORT_BITS;
+ u32 val = (target & PSE_PER_PORT_MASK) << shift;
+ u32 mask = PSE_PER_PORT_MASK << shift;
if (tport_idx < TPORT_IDX_MAX / 2)
mtk_pce_ppe_rmw(ppe, PPE_TPORT_TBL_0, mask, val);
@@ -150,7 +152,8 @@
}
if (TS_CONFIG_MASK & BIT(pse_port))
- ret = mtk_pce_tport_map_update_ts_config(pse_port, tport_idx, target);
+ ret = mtk_pce_tport_map_update_ts_config((enum ts_config_entry)pse_port,
+ tport_idx, target);
else if (PSE_PORT_PPE_MASK & BIT(pse_port))
ret = mtk_pce_tport_map_update_ppe(pse_port, tport_idx, target);
else