commit cfa104bbe74424b2a92ea0f266252f6686d2d226
author developer <developer@mediatek.com> Wed Jan 11 17:40:41 2023 +0800
committer developer <developer@mediatek.com> Fri Jan 13 12:30:02 2023 +0800
tree ef64e2e67efa04ae77d9729dd621aafbeed8ffc5
parent a29111c7b82d760b2d592e4527e111e938a0e498

[][kernel][mt7988][eth][Add USXGMII 5G force mode support]

[Description]
Add USXGMII 5G force mode support.

If without this patch, USXGMII cannot be configured as 5G force mode.

[Release-log]
N/A


Change-Id: I910fba2acede2f1754fb34273141c77d4e870538
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7036929

target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c

diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 147f9b7..6272602 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -351,6 +351,7 @@
 			break;
 		case PHY_INTERFACE_MODE_USXGMII:
 		case PHY_INTERFACE_MODE_10GKR:
+		case PHY_INTERFACE_MODE_5GBASER:
 			if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
 				err = mtk_gmac_usxgmii_path_setup(eth, mac->id);
 				if (err)
@@ -450,14 +451,15 @@
 				   SYSCFG0_SGMII_MASK, val);
 		spin_unlock(&eth->syscfg0_lock);
 	} else if (state->interface == PHY_INTERFACE_MODE_USXGMII ||
-		   state->interface == PHY_INTERFACE_MODE_10GKR) {
+		   state->interface == PHY_INTERFACE_MODE_10GKR ||
+		   state->interface == PHY_INTERFACE_MODE_5GBASER) {
 		sid = mac->id;
 
 		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
 		    sid != MTK_GMAC1_ID) {
 			if (phylink_autoneg_inband(mode))
 				err = mtk_usxgmii_setup_mode_force(eth->xgmii, sid,
-								   SPEED_10000);
+								   state);
 			else
 				err = mtk_usxgmii_setup_mode_an(eth->xgmii, sid,
 								SPEED_10000);
@@ -778,6 +780,8 @@
 			phylink_set(mask, 1000baseT_Full);
 			phylink_set(mask, 1000baseX_Full);
 			phylink_set(mask, 2500baseX_Full);
+			phylink_set(mask, 2500baseT_Full);
+			phylink_set(mask, 5000baseT_Full);
 		}
 		if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
 			phylink_set(mask, 1000baseT_Full);