| commit | ccffa94c5c597ac2dac3678b6eac0f18f4b82514 | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Wed Sep 22 15:57:01 2021 +0800 |
| committer | developer <developer@mediatek.com> | Mon Sep 27 17:37:09 2021 +0800 |
| tree | a336058e29e088cf0575f404d8b79f1b4623bacb | |
| parent | 731b98f53c7f48d4574eefc0937e6e02d74b0429 [diff] [blame] |
[][MT7986 develop][Fix i2c clock divider setting] [Description] Fix Panther i2c clock setting The default frequency of Panther i2c should be 100khz, But the oscilloscope display is actually 300Khz This patch fixes the Panther i2c clock divider settings, and make it 100khz by default [Release-log] N/A Change-Id: Ie839cd2d390dd7c6bdf4378ac8567264e97b7c86 Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5025970
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi index a1c6b41..14f3fe4 100644 --- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi +++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
@@ -290,7 +290,7 @@ reg = <0 0x11008000 0 0x90>, <0 0x10217080 0 0x80>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; - clock-div = <16>; + clock-div = <5>; clocks = <&infracfg_ao CK_INFRA_I2CO_CK>, <&infracfg_ao CK_INFRA_AP_DMA_CK>; clock-names = "main", "dma";