| commit | c4d8da714208ea1a0fc540eb106d1efdfb0f0b54 | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Thu Mar 16 14:37:28 2023 +0800 |
| committer | developer <developer@mediatek.com> | Mon Mar 20 08:58:13 2023 +0800 |
| tree | e4990a06551ba13e6ae8ca12e7de51e05456ac9b | |
| parent | a0ea30148359c682e9f2fef54ee19fd9bbaea3b1 [diff] [blame] |
[][kernel][common][eth][Refactor MDC divider support] [Description] Refactor MDC divider support. Refactor MDC setup function refers to Daniel Golle's upstream patch. - https://patchwork.kernel.org/project/linux-mediatek/patch/ 689e941a0408e5a54466d28d22c9130c0599cd0d.1678357225.git. daniel@makrotopia.org/ And move MDC setup function to mtk_hw_init(). If without this patch, MDC will revert to 2.5MHz after SER reset. [Release-log] N/A Change-Id: I33a5a6dc0b3c51fcd993a0d3a72f64814ced759c Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7255778
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h index c7510b3..5b860d6 100755 --- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -635,6 +635,8 @@ #define MTK_PPSC 0x10000 #define PPSC_MDC_CFG GENMASK(29, 24) #define PPSC_MDC_TURBO BIT(20) +#define MDC_MAX_FREQ 25000000 +#define MDC_MAX_DIVIDER 63 /* PHY Indirect Access Control registers */ #define MTK_PHY_IAC 0x10004