[][kernel][common][eth][Refactor MDC divider support]
[Description]
Refactor MDC divider support.
Refactor MDC setup function refers to Daniel Golle's upstream patch.
- https://patchwork.kernel.org/project/linux-mediatek/patch/
689e941a0408e5a54466d28d22c9130c0599cd0d.1678357225.git.
daniel@makrotopia.org/
And move MDC setup function to mtk_hw_init().
If without this patch, MDC will revert to 2.5MHz after SER reset.
[Release-log]
N/A
Change-Id: I33a5a6dc0b3c51fcd993a0d3a72f64814ced759c
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7255778
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 782ff76..3eaa951 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1081,10 +1081,10 @@
.mac_link_up = mtk_mac_link_up,
};
-static int mtk_mdio_init(struct mtk_eth *eth)
+static int mtk_mdc_init(struct mtk_eth *eth)
{
struct device_node *mii_np;
- int clk = 25000000, max_clk = 2500000, divider = 1;
+ int max_clk = 2500000, divider;
int ret;
u32 val;
@@ -1099,33 +1099,17 @@
goto err_put_node;
}
- eth->mii_bus = devm_mdiobus_alloc(eth->dev);
- if (!eth->mii_bus) {
- ret = -ENOMEM;
- goto err_put_node;
- }
-
- eth->mii_bus->name = "mdio";
- eth->mii_bus->read = mtk_mdio_read;
- eth->mii_bus->write = mtk_mdio_write;
- eth->mii_bus->reset = mtk_mdio_reset;
- eth->mii_bus->priv = eth;
- eth->mii_bus->parent = eth->dev;
-
- if(snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np) < 0) {
- ret = -ENOMEM;
- goto err_put_node;
- }
-
- if (!of_property_read_u32(mii_np, "mdc-max-frequency", &val))
+ if (!of_property_read_u32(mii_np, "clock-frequency", &val)) {
+ if (val > MDC_MAX_FREQ ||
+ val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
+ dev_err(eth->dev, "MDIO clock frequency out of range");
+ ret = -EINVAL;
+ goto err_put_node;
+ }
max_clk = val;
-
- while (clk / divider > max_clk) {
- if (divider >= 63)
- break;
+ }
- divider++;
- };
+ divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
/* Configure MDC Turbo Mode */
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
@@ -1144,7 +1128,46 @@
val |= FIELD_PREP(PPSC_MDC_CFG, divider);
mtk_w32(eth, val, MTK_PPSC);
+ dev_info(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
+
+err_put_node:
+ of_node_put(mii_np);
+ return ret;
+}
+
+static int mtk_mdio_init(struct mtk_eth *eth)
+{
+ struct device_node *mii_np;
+ int ret;
+
+ mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
+ if (!mii_np) {
+ dev_err(eth->dev, "no %s child node found", "mdio-bus");
+ return -ENODEV;
+ }
+
- dev_info(eth->dev, "MDC is running on %d Hz\n", clk / divider);
+ if (!of_device_is_available(mii_np)) {
+ ret = -ENODEV;
+ goto err_put_node;
+ }
+
+ eth->mii_bus = devm_mdiobus_alloc(eth->dev);
+ if (!eth->mii_bus) {
+ ret = -ENOMEM;
+ goto err_put_node;
+ }
+
+ eth->mii_bus->name = "mdio";
+ eth->mii_bus->read = mtk_mdio_read;
+ eth->mii_bus->write = mtk_mdio_write;
+ eth->mii_bus->reset = mtk_mdio_reset;
+ eth->mii_bus->priv = eth;
+ eth->mii_bus->parent = eth->dev;
+
+ if (snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np) < 0) {
+ ret = -ENOMEM;
+ goto err_put_node;
+ }
ret = of_mdiobus_register(eth->mii_bus, mii_np);
@@ -3659,6 +3682,9 @@
else
mtk_eth_cold_reset(eth);
+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
+ mtk_mdc_init(eth);
+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2)) {
/* Set FE to PDMAv2 if necessary */
mtk_w32(eth, mtk_r32(eth, MTK_FE_GLO_MISC) | MTK_PDMA_V2, MTK_FE_GLO_MISC);