tree 028d8589503a9edf72f8ea7bd02593f205a3c684
parent 4e191cd37a306d54bd412f054cce76c434fb9806
author developer <developer@mediatek.com> 1621223316 +0800
committer developer <developer@mediatek.com> 1621825093 +0800

[][Add the external 2.5G PHY support to switch port5 and CPU GMAC2]

[Description]
Add the external 2.5G PHY support to switch port5 and CPU GMAC2.
Also change the index of lan interfaces, from 0 to 5. After this patch,
the LAN/WAN interfaces of all RFB will follow the below rule.
    LAN: lan0~lan4 + lan5
    WAN: eth1

  Two external 2.5G PHYs use the same reset, gpio6 pin, on RFB so only
register the reset pin in the first PHY. The reset is asserted when
of_mdiobus_register() addthe phy devices from dts node. At this time,
external PHY id cannot be read from mdio bus, so add the static PHY id
in the PHY dts node for adding PHY device successfully. The deassert
delay is also required.

[Release-log]
N/A

Change-Id: I41802c294ff35d83477aa338e5c6177526123d6d
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/4546248