[][Add the external 2.5G PHY support to switch port5 and CPU GMAC2]
[Description]
Add the external 2.5G PHY support to switch port5 and CPU GMAC2.
Also change the index of lan interfaces, from 0 to 5. After this patch,
the LAN/WAN interfaces of all RFB will follow the below rule.
LAN: lan0~lan4 + lan5
WAN: eth1
Two external 2.5G PHYs use the same reset, gpio6 pin, on RFB so only
register the reset pin in the first PHY. The reset is asserted when
of_mdiobus_register() addthe phy devices from dts node. At this time,
external PHY id cannot be read from mdio bus, so add the static PHY id
in the PHY dts node for adding PHY device successfully. The deassert
delay is also required.
[Release-log]
N/A
Change-Id: I41802c294ff35d83477aa338e5c6177526123d6d
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/4546248
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
index 4eb459d..e72ea29 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
@@ -53,9 +53,23 @@
#address-cells = <1>;
#size-cells = <0>;
+ phy5: phy@5 {
+ compatible = "ethernet-phy-id67c9.de0a";
+ reg = <5>;
+ reset-gpios = <&pio 6 1>;
+ reset-deassert-us = <20000>;
+ phy-mode = "2500base-x";
+ };
+
+ phy6: phy@6 {
+ compatible = "ethernet-phy-id67c9.de0a";
+ reg = <6>;
+ phy-mode = "2500base-x";
+ };
+
switch@0 {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <31>;
reset-gpios = <&pio 5 0>;
ports {
@@ -64,27 +78,39 @@
port@0 {
reg = <0>;
- label = "lan1";
+ label = "lan0";
};
port@1 {
reg = <1>;
- label = "lan2";
+ label = "lan1";
};
port@2 {
reg = <2>;
- label = "lan3";
+ label = "lan2";
};
port@3 {
reg = <3>;
- label = "lan4";
+ label = "lan3";
};
port@4 {
reg = <4>;
- label = "wan";
+ label = "lan4";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan5";
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
};
port@6 {
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dtsi
index 4fa1ba1..f8885cb 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dtsi
@@ -53,9 +53,23 @@
#address-cells = <1>;
#size-cells = <0>;
+ phy5: phy@5 {
+ compatible = "ethernet-phy-id67c9.de0a";
+ reg = <5>;
+ reset-gpios = <&pio 6 1>;
+ reset-deassert-us = <20000>;
+ phy-mode = "2500base-x";
+ };
+
+ phy6: phy@6 {
+ compatible = "ethernet-phy-id67c9.de0a";
+ reg = <6>;
+ phy-mode = "2500base-x";
+ };
+
switch@0 {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <31>;
reset-gpios = <&pio 5 0>;
ports {
@@ -64,27 +78,39 @@
port@0 {
reg = <0>;
- label = "lan1";
+ label = "lan0";
};
port@1 {
reg = <1>;
- label = "lan2";
+ label = "lan1";
};
port@2 {
reg = <2>;
- label = "lan3";
+ label = "lan2";
};
port@3 {
reg = <3>;
- label = "lan4";
+ label = "lan3";
};
port@4 {
reg = <4>;
- label = "wan";
+ label = "lan4";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan5";
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
};
port@6 {
diff --git a/target/linux/mediatek/mt7986/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7986/base-files/etc/board.d/02_network
index 7820f11..0fd89a5 100755
--- a/target/linux/mediatek/mt7986/base-files/etc/board.d/02_network
+++ b/target/linux/mediatek/mt7986/base-files/etc/board.d/02_network
@@ -15,7 +15,7 @@
"0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6u@eth0" "5u@eth1"
;;
*)
- ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" wan
+ ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 lan4 lan5" eth1
;;
esac
}