[][MAC80211][MT76][Fix patch failed]
[Description]
Fix patch fail
[Release-log]
N/A
Change-Id: Id39214073eefc34651dbac7fc721e9042534d674
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6074564
diff --git a/autobuild_mac80211_release/package/kernel/mt76/patches/0001-mt76-mt7915-rework-testmode-init-registers.patch b/autobuild_mac80211_release/package/kernel/mt76/patches/0001-mt76-mt7915-rework-testmode-init-registers.patch
index 4b45104..abdd03f 100644
--- a/autobuild_mac80211_release/package/kernel/mt76/patches/0001-mt76-mt7915-rework-testmode-init-registers.patch
+++ b/autobuild_mac80211_release/package/kernel/mt76/patches/0001-mt76-mt7915-rework-testmode-init-registers.patch
@@ -1,7 +1,7 @@
-From 9d16552ff5dc96dd576d15f263ac1ae180ac615e Mon Sep 17 00:00:00 2001
+From 31be26088119f67efdc8dcb79c64765abb10d356 Mon Sep 17 00:00:00 2001
From: Shayne Chen <shayne.chen@mediatek.com>
-Date: Wed, 19 Jan 2022 15:46:06 +0800
-Subject: [PATCH 1/6] mt76: mt7915: rework testmode init registers
+Date: Mon, 6 Jun 2022 19:46:26 +0800
+Subject: [PATCH 1/7] mt76: mt7915: rework testmode init registers
---
mt7915/mmio.c | 2 ++
@@ -10,10 +10,10 @@
3 files changed, 54 insertions(+), 16 deletions(-)
diff --git a/mt7915/mmio.c b/mt7915/mmio.c
-index 5062e0d8..2466907e 100644
+index 46ee8a7d..71945ba9 100644
--- a/mt7915/mmio.c
+++ b/mt7915/mmio.c
-@@ -53,6 +53,7 @@ static const u32 mt7986_reg[] = {
+@@ -59,6 +59,7 @@ static const u32 mt7986_reg[] = {
};
static const u32 mt7915_offs[] = {
@@ -21,7 +21,7 @@
[TMAC_CDTR] = 0x090,
[TMAC_ODTR] = 0x094,
[TMAC_ATCR] = 0x098,
-@@ -126,6 +127,7 @@ static const u32 mt7915_offs[] = {
+@@ -132,6 +133,7 @@ static const u32 mt7915_offs[] = {
};
static const u32 mt7916_offs[] = {
@@ -30,10 +30,10 @@
[TMAC_ODTR] = 0x0cc,
[TMAC_ATCR] = 0x00c,
diff --git a/mt7915/regs.h b/mt7915/regs.h
-index e5f93c40..999dd7fc 100644
+index 77fd448b..c7c9e411 100644
--- a/mt7915/regs.h
+++ b/mt7915/regs.h
-@@ -34,6 +34,7 @@ enum reg_rev {
+@@ -36,6 +36,7 @@ enum reg_rev {
};
enum offs_rev {
@@ -41,9 +41,9 @@
TMAC_CDTR,
TMAC_ODTR,
TMAC_ATCR,
-@@ -172,6 +173,12 @@ enum offs_rev {
- #define MT_MDP_TO_HIF 0
- #define MT_MDP_TO_WM 1
+@@ -185,6 +186,12 @@ enum offs_rev {
+ #define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16)
+ #define MT_TRB_RXPSR0_RX_RMAC_PTR GENMASK(9, 0)
+#define MT_MDP_TOP_DBG_WDT_CTRL MT_MDP(0x0d0)
+#define MT_MDP_TOP_DBG_WDT_CTRL_TDP_DIS_BLK BIT(7)
@@ -54,7 +54,7 @@
/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
#define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
#define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))
-@@ -180,6 +187,9 @@ enum offs_rev {
+@@ -193,6 +200,9 @@ enum offs_rev {
#define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6)
#define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25)
@@ -64,7 +64,7 @@
#define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CDTR))
#define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ODTR))
#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
-@@ -451,8 +461,10 @@ enum offs_rev {
+@@ -464,8 +474,10 @@ enum offs_rev {
#define MT_AGG_PCR0_VHT_PROT BIT(13)
#define MT_AGG_PCR0_PTA_WIN_DIS BIT(15)