[][openwrt][common][Kernel from 5.4.271 to 5.4.281]
[Description]
Change kernel-5.4.271 to kernel-5.4.281
[Release-log]
Change-Id: If7d67f96c111ad48b5e66df42f425012a5880361
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/9456237
diff --git a/21.02/files/target/linux/mediatek/patches-5.4/999-1402-v6.4-mtd-spinand-backport-series-flash.patch b/21.02/files/target/linux/mediatek/patches-5.4/999-1402-v6.4-mtd-spinand-backport-series-flash.patch
index d3434eb..e0c59d5 100644
--- a/21.02/files/target/linux/mediatek/patches-5.4/999-1402-v6.4-mtd-spinand-backport-series-flash.patch
+++ b/21.02/files/target/linux/mediatek/patches-5.4/999-1402-v6.4-mtd-spinand-backport-series-flash.patch
@@ -442,7 +442,7 @@
NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -116,51 +118,194 @@ static const struct spinand_info macroni
+@@ -116,23 +118,76 @@ static const struct spinand_info macroni
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
@@ -455,16 +455,18 @@
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
+- SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
+- SPINAND_INFO("MX35LF4GE4AD", 0x37,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+ SPINAND_INFO("MX35LF4GE4AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37),
-+ NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
+ NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+ SPINAND_INFO("MX35LF1G24AD",
@@ -476,30 +478,16 @@
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
-- SPINAND_INFO("MX35LF4GE4AD", 0x37,
-- NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1),
+- SPINAND_INFO("MX35LF2G14AC", 0x20,
+ SPINAND_INFO("MX35LF2G24AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
- NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
--};
--
--static int macronix_spinand_detect(struct spinand_device *spinand)
--{
-- u8 *id = spinand->id.data;
-- int ret;
--
-- /*
-- * Macronix SPI NAND read ID needs a dummy byte, so the first byte in
-- * raw_id is garbage.
-- */
-- if (id[1] != SPINAND_MFR_MACRONIX)
-- return 0;
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_variants,
++ &update_cache_variants),
++ SPINAND_HAS_QE_BIT,
++ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
+ SPINAND_INFO("MX35LF4G24AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1),
@@ -529,131 +517,133 @@
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
-
-- ret = spinand_match_and_init(spinand, macronix_spinand_table,
-- ARRAY_SIZE(macronix_spinand_table),
-- id[2]);
-- if (ret)
-- return ret;
++
+ SPINAND_INFO("MX35LF2G14AC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20),
-+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
-+ NAND_ECCREQ(4, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+ mx35lf1ge4ab_ecc_get_status)),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -141,7 +196,8 @@ static const struct spinand_info macroni
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+- SPINAND_INFO("MX35UF4G24AD", 0xb5,
+ SPINAND_INFO("MX35UF4G24AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5),
-+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+ mx35lf1ge4ab_ecc_get_status)),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -150,7 +206,8 @@ static const struct spinand_info macroni
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+- SPINAND_INFO("MX35UF4GE4AD", 0xb7,
+ SPINAND_INFO("MX35UF4GE4AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7),
-+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+ mx35lf1ge4ab_ecc_get_status)),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -159,7 +216,8 @@ static const struct spinand_info macroni
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+- SPINAND_INFO("MX35UF2G14AC", 0xa0,
+ SPINAND_INFO("MX35UF2G14AC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0),
-+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
-+ NAND_ECCREQ(4, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+ mx35lf1ge4ab_ecc_get_status)),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -168,7 +226,8 @@ static const struct spinand_info macroni
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+- SPINAND_INFO("MX35UF2G24AD", 0xa4,
+ SPINAND_INFO("MX35UF2G24AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4),
-+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+ mx35lf1ge4ab_ecc_get_status)),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -177,7 +236,8 @@ static const struct spinand_info macroni
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+- SPINAND_INFO("MX35UF2GE4AD", 0xa6,
+ SPINAND_INFO("MX35UF2GE4AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6),
-+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+ mx35lf1ge4ab_ecc_get_status)),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -186,7 +246,8 @@ static const struct spinand_info macroni
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+- SPINAND_INFO("MX35UF2GE4AC", 0xa2,
+ SPINAND_INFO("MX35UF2GE4AC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2),
-+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
-+ NAND_ECCREQ(4, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+ mx35lf1ge4ab_ecc_get_status)),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -195,7 +256,8 @@ static const struct spinand_info macroni
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+- SPINAND_INFO("MX35UF1G14AC", 0x90,
+ SPINAND_INFO("MX35UF1G14AC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90),
-+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+ NAND_ECCREQ(4, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+ mx35lf1ge4ab_ecc_get_status)),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -204,7 +266,8 @@ static const struct spinand_info macroni
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+- SPINAND_INFO("MX35UF1G24AD", 0x94,
+ SPINAND_INFO("MX35UF1G24AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94),
-+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+ mx35lf1ge4ab_ecc_get_status)),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -213,7 +276,8 @@ static const struct spinand_info macroni
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+- SPINAND_INFO("MX35UF1GE4AD", 0x96,
+ SPINAND_INFO("MX35UF1GE4AD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96),
-+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+ mx35lf1ge4ab_ecc_get_status)),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -222,7 +286,8 @@ static const struct spinand_info macroni
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
+- SPINAND_INFO("MX35UF1GE4AC", 0x92,
+ SPINAND_INFO("MX35UF1GE4AC",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
-+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+ NAND_ECCREQ(4, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+ mx35lf1ge4ab_ecc_get_status)),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+@@ -231,6 +296,7 @@ static const struct spinand_info macroni
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+ mx35lf1ge4ab_ecc_get_status)),
++
+ };
-- return 1;
--}
-+};
+ static int macronix_spinand_detect(struct spinand_device *spinand)
+--- a/drivers/mtd/nand/spi/macronix.c
++++ b/drivers/mtd/nand/spi/macronix.c
+@@ -255,7 +255,6 @@ static int macronix_spinand_detect(struc
+ }
static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
- .detect = macronix_spinand_detect,
};
+ const struct spinand_manufacturer macronix_spinand_manufacturer = {
+--- a/drivers/mtd/nand/spi/macronix.c
++++ b/drivers/mtd/nand/spi/macronix.c
+@@ -326,5 +326,7 @@ static const struct spinand_manufacturer
const struct spinand_manufacturer macronix_spinand_manufacturer = {
.id = SPINAND_MFR_MACRONIX,
.name = "Macronix",
@@ -661,6 +651,7 @@
+ .nchips = ARRAY_SIZE(macronix_spinand_table),
.ops = ¯onix_spinand_manuf_ops,
};
+
Index: linux-5.4.260/drivers/mtd/nand/spi/micron.c
===================================================================
--- linux-5.4.260.orig/drivers/mtd/nand/spi/micron.c
diff --git a/21.02/files/target/linux/mediatek/patches-5.4/999-1802-v6.4-backport-pinctrl-pinconf-setting-combo.patch b/21.02/files/target/linux/mediatek/patches-5.4/999-1802-v6.4-backport-pinctrl-pinconf-setting-combo.patch
index 43ca0c5..cea4fe8 100644
--- a/21.02/files/target/linux/mediatek/patches-5.4/999-1802-v6.4-backport-pinctrl-pinconf-setting-combo.patch
+++ b/21.02/files/target/linux/mediatek/patches-5.4/999-1802-v6.4-backport-pinctrl-pinconf-setting-combo.patch
@@ -109,109 +109,82 @@
return err;
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-@@ -506,6 +506,404 @@ int mtk_pinconf_bias_get_rev1(struct mtk
- return 0;
+@@ -6,7 +6,6 @@
+ *
+ */
+
+-#include <dt-bindings/pinctrl/mt65xx.h>
+ #include <linux/device.h>
+ #include <linux/err.h>
+ #include <linux/gpio/driver.h>
+@@ -67,44 +66,34 @@ static int mtk_hw_pin_field_lookup(struc
+ const struct mtk_pin_desc *desc,
+ int field, struct mtk_pin_field *pfd)
+ {
+- const struct mtk_pin_field_calc *c;
++ const struct mtk_pin_field_calc *c, *e;
+ const struct mtk_pin_reg_calc *rc;
+- int start = 0, end, check;
+- bool found = false;
+ u32 bits;
+
+ if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
+ rc = &hw->soc->reg_cal[field];
+ } else {
+ dev_dbg(hw->dev,
+- "Not support field %d for this soc\n", field);
++ "Not support field %d for pin %d (%s)\n",
++ field, desc->number, desc->name);
+ return -ENOTSUPP;
+ }
+
+- end = rc->nranges - 1;
++ c = rc->range;
++ e = c + rc->nranges;
+
+- while (start <= end) {
+- check = (start + end) >> 1;
+- if (desc->number >= rc->range[check].s_pin
+- && desc->number <= rc->range[check].e_pin) {
+- found = true;
+- break;
+- } else if (start == end)
++ while (c < e) {
++ if (desc->number >= c->s_pin && desc->number <= c->e_pin)
+ break;
+- else if (desc->number < rc->range[check].s_pin)
+- end = check - 1;
+- else
+- start = check + 1;
++ c++;
+ }
+
+- if (!found) {
++ if (c >= e) {
+ dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
+ field, desc->number, desc->name);
+ return -ENOTSUPP;
+ }
+
+- c = rc->range + check;
+-
+ if (c->i_base > hw->nbase - 1) {
+ dev_err(hw->dev,
+ "Invalid base for field %d for pin = %d (%s)\n",
+@@ -193,9 +182,6 @@ int mtk_hw_set_value(struct mtk_pinctrl
+ if (err)
+ return err;
+
+- if (value < 0 || value > pf.mask)
+- return -EINVAL;
+-
+ if (!pf.next)
+ mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
+ (value & pf.mask) << pf.bitpos);
+@@ -619,6 +605,186 @@ out:
+ return err;
}
-+/* Combo for the following pull register type:
-+ * 1. PU + PD
-+ * 2. PULLSEL + PULLEN
-+ * 3. PUPD + R0 + R1
-+ */
-+static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 pullup, u32 arg)
-+{
-+ int err, pu, pd;
-+
-+ if (arg == MTK_DISABLE) {
-+ pu = 0;
-+ pd = 0;
-+ } else if ((arg == MTK_ENABLE) && pullup) {
-+ pu = 1;
-+ pd = 0;
-+ } else if ((arg == MTK_ENABLE) && !pullup) {
-+ pu = 0;
-+ pd = 1;
-+ } else {
-+ err = -EINVAL;
-+ goto out;
-+ }
-+
-+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
-+ if (err)
-+ goto out;
-+
-+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
-+
-+out:
-+ return err;
-+}
-+
-+static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 pullup, u32 arg)
-+{
-+ int err, enable;
-+
-+ if (arg == MTK_DISABLE)
-+ enable = 0;
-+ else if (arg == MTK_ENABLE)
-+ enable = 1;
-+ else {
-+ err = -EINVAL;
-+ goto out;
-+ }
-+
-+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
-+ if (err)
-+ goto out;
-+
-+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
-+
-+out:
-+ return err;
-+}
-+
-+static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 pullup, u32 arg)
-+{
-+ int err, r0, r1;
-+
-+ if ((arg == MTK_DISABLE) || (arg == MTK_PUPD_SET_R1R0_00)) {
-+ pullup = 0;
-+ r0 = 0;
-+ r1 = 0;
-+ } else if (arg == MTK_PUPD_SET_R1R0_01) {
-+ r0 = 1;
-+ r1 = 0;
-+ } else if (arg == MTK_PUPD_SET_R1R0_10) {
-+ r0 = 0;
-+ r1 = 1;
-+ } else if (arg == MTK_PUPD_SET_R1R0_11) {
-+ r0 = 1;
-+ r1 = 1;
-+ } else {
-+ err = -EINVAL;
-+ goto out;
-+ }
-+
-+ /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
-+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, !pullup);
-+ if (err)
-+ goto out;
-+
-+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, r0);
-+ if (err)
-+ goto out;
-+
-+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, r1);
-+
-+out:
-+ return err;
-+}
-+
+static int mtk_hw_pin_rsel_lookup(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 pullup, u32 arg, u32 *rsel_val)
@@ -392,105 +365,59 @@
+ return err;
+}
+
-+static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 *pullup, u32 *enable)
-+{
-+ int err, pu, pd;
-+
-+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
-+ if (err)
-+ goto out;
-+
-+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
-+ if (err)
-+ goto out;
-+
-+ if (pu == 0 && pd == 0) {
-+ *pullup = 0;
-+ *enable = MTK_DISABLE;
-+ } else if (pu == 1 && pd == 0) {
-+ *pullup = 1;
-+ *enable = MTK_ENABLE;
-+ } else if (pu == 0 && pd == 1) {
-+ *pullup = 0;
-+ *enable = MTK_ENABLE;
-+ } else
-+ err = -EINVAL;
-+
-+out:
-+ return err;
-+}
-+
-+static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 *pullup, u32 *enable)
-+{
-+ int err;
-+
-+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
-+ if (err)
-+ goto out;
-+
-+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
-+
-+out:
-+ return err;
-+}
-+
-+static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 *pullup, u32 *enable)
-+{
-+ int err, r0, r1;
-+
-+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, pullup);
-+ if (err)
-+ goto out;
-+ /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
-+ *pullup = !(*pullup);
-+
-+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &r0);
-+ if (err)
-+ goto out;
-+
-+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &r1);
-+ if (err)
-+ goto out;
-+
-+ if ((r1 == 0) && (r0 == 0))
-+ *enable = MTK_PUPD_SET_R1R0_00;
-+ else if ((r1 == 0) && (r0 == 1))
-+ *enable = MTK_PUPD_SET_R1R0_01;
-+ else if ((r1 == 1) && (r0 == 0))
-+ *enable = MTK_PUPD_SET_R1R0_10;
-+ else if ((r1 == 1) && (r0 == 1))
-+ *enable = MTK_PUPD_SET_R1R0_11;
-+ else
-+ err = -EINVAL;
-+
-+out:
-+ return err;
-+}
-+
-+int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 *pullup, u32 *enable)
-+{
+ static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 *pullup, u32 *enable)
+@@ -700,45 +866,43 @@ out:
+ return err;
+ }
+
+-int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
+- const struct mtk_pin_desc *desc,
+- u32 pullup, u32 arg)
+-{
+- int err;
+-
+- err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
+- if (!err)
+- goto out;
+-
+- err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg);
+- if (!err)
+- goto out;
+-
+- err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
+-
+-out:
+- return err;
+-}
+-
+ int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 *pullup, u32 *enable)
+ {
+- int err;
+ int err = -ENOTSUPP;
+ u32 try_all_type;
-+
+
+- err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
+- if (!err)
+- goto out;
+ if (hw->soc->pull_type)
+ try_all_type = hw->soc->pull_type[desc->number];
+ else
+ try_all_type = MTK_PULL_TYPE_MASK;
-+
+
+- err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable);
+- if (!err)
+- goto out;
+ if (try_all_type & MTK_PULL_RSEL_TYPE) {
+ err = mtk_pinconf_bias_get_rsel(hw, desc, pullup, enable);
+ if (!err)
+ return err;
+ }
-+
+
+- err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
+ if (try_all_type & MTK_PULL_PU_PD_TYPE) {
+ err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
+ if (!err)
@@ -506,14 +433,44 @@
+
+ if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE)
+ err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
-+
-+ return err;
-+}
+
+-out:
+ return err;
+ }
+EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo);
-+
+
/* Revision 0 */
int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
- const struct mtk_pin_desc *desc, u32 arg)
+@@ -831,18 +995,6 @@ int mtk_pinconf_drive_get_rev1(struct mt
+ return 0;
+ }
+
+-int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw,
+- const struct mtk_pin_desc *desc, u32 arg)
+-{
+- return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg);
+-}
+-
+-int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw,
+- const struct mtk_pin_desc *desc, int *val)
+-{
+- return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val);
+-}
+-
+ int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup,
+ u32 arg)
+@@ -876,9 +1028,7 @@ int mtk_pinconf_adv_pull_set(struct mtk_
+ if (err)
+ return err;
+ } else {
+- err = mtk_pinconf_bias_set_rev1(hw, desc, pullup);
+- if (err)
+- err = mtk_pinconf_bias_set(hw, desc, pullup);
++ return -ENOTSUPP;
+ }
+ }
+
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -17,6 +17,34 @@
@@ -593,19 +550,22 @@
/* Specific pinconfig operations */
int (*bias_disable_set)(struct mtk_pinctrl *hw,
-@@ -215,7 +264,10 @@ struct mtk_pin_soc {
+@@ -215,12 +264,10 @@ struct mtk_pin_soc {
const struct mtk_pin_desc *desc, bool pullup);
int (*bias_get)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup, int *res);
-
-+ int (*bias_set_combo)(struct mtk_pinctrl *hw,
+ int (*bias_set_combo)(struct mtk_pinctrl *hw,
+- const struct mtk_pin_desc *desc, u32 pullup, u32 arg);
+ const struct mtk_pin_desc *desc, u32 pullup, u32 arg);
-+ int (*bias_get_combo)(struct mtk_pinctrl *hw,
+ int (*bias_get_combo)(struct mtk_pinctrl *hw,
+- const struct mtk_pin_desc *desc, u32 *pullup, u32 *arg);
+-
+ const struct mtk_pin_desc *desc, u32 *pullup, u32 *arg);
int (*drive_set)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg);
int (*drive_get)(struct mtk_pinctrl *hw,
-@@ -246,6 +298,10 @@ struct mtk_pinctrl {
+@@ -251,6 +298,10 @@ struct mtk_pinctrl {
struct mtk_eint *eint;
struct mtk_pinctrl_group *groups;
const char **grp_names;
@@ -616,7 +576,18 @@
};
void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set);
-@@ -282,7 +338,12 @@ int mtk_pinconf_drive_set(struct mtk_pin
+@@ -282,28 +333,22 @@ int mtk_pinconf_bias_set_rev1(struct mtk
+ int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup,
+ int *res);
+-int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
+- const struct mtk_pin_desc *desc,
+- u32 pullup, u32 enable);
+-int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
+- const struct mtk_pin_desc *desc,
+- u32 *pullup, u32 *enable);
+
+ int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg);
int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *val);
@@ -630,3 +601,13 @@
int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg);
int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, int *val);
+
+-int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw,
+- const struct mtk_pin_desc *desc, u32 arg);
+-int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw,
+- const struct mtk_pin_desc *desc, int *val);
+-
+ int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc, bool pullup,
+ u32 arg);
diff --git a/21.02/patches-base/201-change_kernel_version_and_hash_due_to_upgrading_from_5.4.260_to_5.4.271.patch b/21.02/patches-base/201-change_kernel_version_and_hash_due_to_upgrading_from_5.4.260_to_5.4.271.patch
deleted file mode 100644
index 4e56921..0000000
--- a/21.02/patches-base/201-change_kernel_version_and_hash_due_to_upgrading_from_5.4.260_to_5.4.271.patch
+++ /dev/null
@@ -1,47 +0,0 @@
---- a/include/kernel-5.4
-+++ b/include/kernel-5.4
-@@ -1,2 +1,2 @@
--LINUX_VERSION-5.4 = .238
--LINUX_KERNEL_HASH-5.4.238 = 70a2b2da85598eba6a73cdc0749e441cbdf3011d9babcb7028a46aa8d98aa91f
-+LINUX_VERSION-5.4 = .271
-+LINUX_KERNEL_HASH-5.4.271 = cdbc61334cdadbd3945b08f03ed197c65bdf358c3383a4334b3e5b483bd95850
-
---- a/target/linux/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch
-+++ b/target/linux/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch
-@@ -81,7 +81,7 @@
- };
-
- cpus {
--@@ -40,23 +39,36 @@
-+@@ -39,23 +39,36 @@
-
- gpio-keys {
- compatible = "gpio-keys";
-@@ -99,9 +99,9 @@
- linux,code = <KEY_WPS_BUTTON>;
- - gpios = <&pio 102 0>;
- + gpios = <&pio 102 GPIO_ACTIVE_LOW>;
--+ };
--+ };
--+
-+ };
-+ };
-+
- + leds {
- + compatible = "gpio-leds";
- +
-@@ -113,10 +113,10 @@
- + red {
- + label = "bpi-r64:pio:red";
- + gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-- };
-- };
--
-- memory {
-++ };
-++ };
-++
-+ memory@40000000 {
- - reg = <0 0x40000000 0 0x20000000>;
- + reg = <0 0x40000000 0 0x40000000>;
- };
diff --git a/21.02/patches-base/201-change_kernel_version_and_hash_due_to_upgrading_from_5.4.271_to_5.4.281.patch b/21.02/patches-base/201-change_kernel_version_and_hash_due_to_upgrading_from_5.4.271_to_5.4.281.patch
new file mode 100644
index 0000000..3df59d2
--- /dev/null
+++ b/21.02/patches-base/201-change_kernel_version_and_hash_due_to_upgrading_from_5.4.271_to_5.4.281.patch
@@ -0,0 +1,120 @@
+--- a/include/kernel-5.4
++++ b/include/kernel-5.4
+@@ -1,2 +1,2 @@
+-LINUX_VERSION-5.4 = .238
+-LINUX_KERNEL_HASH-5.4.238 = 70a2b2da85598eba6a73cdc0749e441cbdf3011d9babcb7028a46aa8d98aa91f
++LINUX_VERSION-5.4 = .281
++LINUX_KERNEL_HASH-5.4.281 = 44a0c3e76031f7513ce43e22e2a9dcbf7d6a6dee065dca9b8001843a075272b2
+
+--- a/target/linux/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch
++++ b/target/linux/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch
+@@ -81,7 +81,7 @@
+ };
+
+ cpus {
+-@@ -40,23 +39,36 @@
++@@ -39,23 +39,36 @@
+
+ gpio-keys {
+ compatible = "gpio-keys";
+@@ -99,9 +99,9 @@
+ linux,code = <KEY_WPS_BUTTON>;
+ - gpios = <&pio 102 0>;
+ + gpios = <&pio 102 GPIO_ACTIVE_LOW>;
+-+ };
+-+ };
+-+
++ };
++ };
++
+ + leds {
+ + compatible = "gpio-leds";
+ +
+@@ -113,12 +113,13 @@
+ + red {
+ + label = "bpi-r64:pio:red";
+ + gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
+- };
+- };
+-
+- memory {
+++ };
+++ };
+++
++ memory@40000000 {
+ - reg = <0 0x40000000 0 0x20000000>;
+ + reg = <0 0x40000000 0 0x40000000>;
++ device_type = "memory";
+ };
+
+ reg_1p8v: regulator-1p8v {
+
+--- a/target/linux/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
++++ b/target/linux/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
+@@ -389,25 +389,20 @@ Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
+ <0 0 0 2 &pcie_intc1 1>,
+ --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+ +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+-@@ -254,18 +254,16 @@
++@@ -184,14 +184,16 @@
+ };
+ };
+
+ -&pcie {
+ +&pcie0 {
+ pinctrl-names = "default";
+-- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
+-+ pinctrl-0 = <&pcie0_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
+ +};
+
+ - pcie@0,0 {
+ - status = "okay";
+ - };
+--
+-- pcie@1,0 {
+-- status = "okay";
+-- };
+ +&pcie1 {
+ + pinctrl-names = "default";
+ + pinctrl-0 = <&pcie1_pins>;
+
+--- a/target/linux/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
++++ b/target/linux/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
+@@ -115,35 +115,3 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
+ call_netdevice_notifiers(NETDEV_CHANGEADDR, dev);
+ add_device_randomness(dev->dev_addr, dev->addr_len);
+ return 0;
+---- a/net/ethernet/eth.c
+-+++ b/net/ethernet/eth.c
+-@@ -143,6 +143,18 @@ u32 eth_get_headlen(const struct net_dev
+- }
+- EXPORT_SYMBOL(eth_get_headlen);
+-
+-+static inline bool
+-+eth_check_local_mask(const void *addr1, const void *addr2, const void *mask)
+-+{
+-+ const u16 *a1 = addr1;
+-+ const u16 *a2 = addr2;
+-+ const u16 *m = mask;
+-+
+-+ return (((a1[0] ^ a2[0]) & ~m[0]) |
+-+ ((a1[1] ^ a2[1]) & ~m[1]) |
+-+ ((a1[2] ^ a2[2]) & ~m[2]));
+-+}
+-+
+- /**
+- * eth_type_trans - determine the packet's protocol ID.
+- * @skb: received socket data
+-@@ -174,6 +186,10 @@ __be16 eth_type_trans(struct sk_buff *sk
+- } else {
+- skb->pkt_type = PACKET_OTHERHOST;
+- }
+-+
+-+ if (eth_check_local_mask(eth->h_dest, dev->dev_addr,
+-+ dev->local_addr_mask))
+-+ skb->gro_skip = 1;
+- }
+-
+- /*
diff --git a/autobuild/autobuild_5.4_mac80211_release/target/linux/mediatek/patches-5.4/999-3001-mt7622-backport-nf-hw-offload-framework-and-upstream.patch b/autobuild/autobuild_5.4_mac80211_release/target/linux/mediatek/patches-5.4/999-3001-mt7622-backport-nf-hw-offload-framework-and-upstream.patch
index b0eb98b..ec39c96 100644
--- a/autobuild/autobuild_5.4_mac80211_release/target/linux/mediatek/patches-5.4/999-3001-mt7622-backport-nf-hw-offload-framework-and-upstream.patch
+++ b/autobuild/autobuild_5.4_mac80211_release/target/linux/mediatek/patches-5.4/999-3001-mt7622-backport-nf-hw-offload-framework-and-upstream.patch
@@ -3101,10 +3101,10 @@
static struct dst_entry *ip6_dst_check(struct dst_entry *dst, u32 cookie);
static unsigned int ip6_default_advmss(const struct dst_entry *dst);
-static unsigned int ip6_mtu(const struct dst_entry *dst);
-+static unsigned int ip6_mtu(const struct dst_entry *dst);
- static struct dst_entry *ip6_negative_advice(struct dst_entry *);
++static unsigned int ip6_mtu(const struct dst_entry *dst);
+ static void ip6_negative_advice(struct sock *sk,
+ struct dst_entry *dst);
static void ip6_dst_destroy(struct dst_entry *);
- static void ip6_dst_ifdown(struct dst_entry *,
@@ -3125,25 +3125,7 @@ static unsigned int ip6_default_advmss(const struct dst_entry *dst)
static unsigned int ip6_mtu(const struct dst_entry *dst)