[][change 7981 clk drivers]
[Description]
Change 7981 clk drivers
[Release-log]
N/A
Change-Id: I04c6fc2a95811096de427b5d051b8293efc06c7d
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5329206
diff --git a/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7981.c b/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7981.c
index 8cce0fd..eafe722 100644
--- a/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7981.c
+++ b/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7981.c
@@ -431,10 +431,7 @@
};
static const char * const infra_pwm1_parents[] __initconst = {
- "infra_pwm",
- "infra_66m_mck",
- "infra_ck_f26m",
- "infra_ck_f32k"
+ "infra_pwm"
};
static const char * const infra_pwm_bsel_parents[] __initconst = {
@@ -466,9 +463,11 @@
MUX_GATE_CLR_SET_UPD(CK_INFRA_SPI2_SEL, "infra_spi2_sel",
infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM1_SEL, "infra_pwm1_sel",
- infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 2, -1, -1, -1),
+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM2_SEL, "infra_pwm2_sel",
- infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 2, -1, -1, -1),
+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1, -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM3_SEL, "infra_pwm3_sel",
+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_BSEL, "infra_pwm_bsel",
infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, 2, -1, -1, -1),
/* MODULE_CLK_SEL_1 */
@@ -543,6 +542,7 @@
GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", "infra_ck_f26m", 25),
+ GATE_INFRA0(CK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
/* INFRA1 */
GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", "infra_ck_f26m", 0),
GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", "infra_i2cs", 1),
@@ -769,7 +769,7 @@
return;
}
- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_AO_NR_CLK);
mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, &mt7981_clk_lock, clk_data);
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data);
diff --git a/target/linux/mediatek/files-5.4/include/dt-bindings/clock/mt7981-clk.h b/target/linux/mediatek/files-5.4/include/dt-bindings/clock/mt7981-clk.h
index af019ae..4846717 100644
--- a/target/linux/mediatek/files-5.4/include/dt-bindings/clock/mt7981-clk.h
+++ b/target/linux/mediatek/files-5.4/include/dt-bindings/clock/mt7981-clk.h
@@ -180,56 +180,58 @@
#define CK_INFRA_SPI2_SEL 5
#define CK_INFRA_PWM1_SEL 6
#define CK_INFRA_PWM2_SEL 7
-#define CK_INFRA_PWM_BSEL 8
-#define CK_INFRA_PCIE_SEL 9
-#define CK_INFRA_GPT_STA 10
-#define CK_INFRA_PWM_HCK 11
-#define CK_INFRA_PWM_STA 12
-#define CK_INFRA_PWM1_CK 13
-#define CK_INFRA_PWM2_CK 14
-#define CK_INFRA_CQ_DMA_CK 15
-#define CK_INFRA_AUD_BUS_CK 16
-#define CK_INFRA_AUD_26M_CK 17
-#define CK_INFRA_AUD_L_CK 18
-#define CK_INFRA_AUD_AUD_CK 19
-#define CK_INFRA_AUD_EG2_CK 20
-#define CK_INFRA_DRAMC_26M_CK 21
-#define CK_INFRA_DBG_CK 22
-#define CK_INFRA_AP_DMA_CK 23
-#define CK_INFRA_SEJ_CK 24
-#define CK_INFRA_SEJ_13M_CK 25
-#define CK_INFRA_THERM_CK 26
-#define CK_INFRA_I2CO_CK 27
-#define CK_INFRA_UART0_CK 28
-#define CK_INFRA_UART1_CK 29
-#define CK_INFRA_UART2_CK 30
-#define CK_INFRA_SPI2_CK 31
-#define CK_INFRA_SPI2_HCK_CK 32
-#define CK_INFRA_NFI1_CK 33
-#define CK_INFRA_SPINFI1_CK 34
-#define CK_INFRA_NFI_HCK_CK 35
-#define CK_INFRA_SPI0_CK 36
-#define CK_INFRA_SPI1_CK 37
-#define CK_INFRA_SPI0_HCK_CK 38
-#define CK_INFRA_SPI1_HCK_CK 39
-#define CK_INFRA_FRTC_CK 40
-#define CK_INFRA_MSDC_CK 41
-#define CK_INFRA_MSDC_HCK_CK 42
-#define CK_INFRA_MSDC_133M_CK 43
-#define CK_INFRA_MSDC_66M_CK 44
-#define CK_INFRA_ADC_26M_CK 45
-#define CK_INFRA_ADC_FRC_CK 46
-#define CK_INFRA_FBIST2FPC_CK 47
-#define CK_INFRA_I2C_MCK_CK 48
-#define CK_INFRA_I2C_PCK_CK 49
-#define CK_INFRA_IUSB_133_CK 50
-#define CK_INFRA_IUSB_66M_CK 51
-#define CK_INFRA_IUSB_SYS_CK 52
-#define CK_INFRA_IUSB_CK 53
-#define CK_INFRA_IPCIE_CK 54
-#define CK_INFRA_IPCIER_CK 55
-#define CK_INFRA_IPCIEB_CK 56
-#define CLK_INFRA_AO_NR_CLK 57
+#define CK_INFRA_PWM3_SEL 8
+#define CK_INFRA_PWM_BSEL 9
+#define CK_INFRA_PCIE_SEL 10
+#define CK_INFRA_GPT_STA 11
+#define CK_INFRA_PWM_HCK 12
+#define CK_INFRA_PWM_STA 13
+#define CK_INFRA_PWM1_CK 14
+#define CK_INFRA_PWM2_CK 15
+#define CK_INFRA_PWM3_CK 16
+#define CK_INFRA_CQ_DMA_CK 17
+#define CK_INFRA_AUD_BUS_CK 18
+#define CK_INFRA_AUD_26M_CK 19
+#define CK_INFRA_AUD_L_CK 20
+#define CK_INFRA_AUD_AUD_CK 21
+#define CK_INFRA_AUD_EG2_CK 22
+#define CK_INFRA_DRAMC_26M_CK 23
+#define CK_INFRA_DBG_CK 24
+#define CK_INFRA_AP_DMA_CK 25
+#define CK_INFRA_SEJ_CK 26
+#define CK_INFRA_SEJ_13M_CK 27
+#define CK_INFRA_THERM_CK 28
+#define CK_INFRA_I2CO_CK 29
+#define CK_INFRA_UART0_CK 30
+#define CK_INFRA_UART1_CK 31
+#define CK_INFRA_UART2_CK 32
+#define CK_INFRA_SPI2_CK 33
+#define CK_INFRA_SPI2_HCK_CK 34
+#define CK_INFRA_NFI1_CK 35
+#define CK_INFRA_SPINFI1_CK 36
+#define CK_INFRA_NFI_HCK_CK 37
+#define CK_INFRA_SPI0_CK 38
+#define CK_INFRA_SPI1_CK 39
+#define CK_INFRA_SPI0_HCK_CK 40
+#define CK_INFRA_SPI1_HCK_CK 41
+#define CK_INFRA_FRTC_CK 42
+#define CK_INFRA_MSDC_CK 43
+#define CK_INFRA_MSDC_HCK_CK 44
+#define CK_INFRA_MSDC_133M_CK 45
+#define CK_INFRA_MSDC_66M_CK 46
+#define CK_INFRA_ADC_26M_CK 47
+#define CK_INFRA_ADC_FRC_CK 48
+#define CK_INFRA_FBIST2FPC_CK 49
+#define CK_INFRA_I2C_MCK_CK 50
+#define CK_INFRA_I2C_PCK_CK 51
+#define CK_INFRA_IUSB_133_CK 52
+#define CK_INFRA_IUSB_66M_CK 53
+#define CK_INFRA_IUSB_SYS_CK 54
+#define CK_INFRA_IUSB_CK 55
+#define CK_INFRA_IPCIE_CK 56
+#define CK_INFRA_IPCIER_CK 57
+#define CK_INFRA_IPCIEB_CK 58
+#define CLK_INFRA_AO_NR_CLK 59
/* APMIXEDSYS */