commit	2dddc739fc9881fae39ddb955bc697f0ededef2a	[log] [tgz]
author	developer <developer@mediatek.com>	Tue Oct 22 14:45:03 2024 +0800
committer	developer <developer@mediatek.com>	Wed Oct 23 13:22:06 2024 +0800
tree	279f37e06854a8e4918e978695b5298f0eeddeab
parent	9cab936df3732b16086aff9b301b7ae042761277 [diff]

[][HIGH][kernel][common][eth][Update Airoha EN8811H 2.5G PHY driver to v1.2.7]

[Description]
Change Airoha EN8811H 2.5G PHY driver to v1.2.7.

Change Log:
[2024/10/22] v1.2.7
1. Add releated API for phy-handle

[2024/09/04] v1.2.6
1. Support DTS settings for Co-clock output.
2. Mute Tx before loading MD32 FW
3. Enhance cable diag feature
4. The default setting for CKO(Co-clock output) is disabled.
* MD32 FW 24082302 updated:
1. Reinitialize the FNPLL clock during MD32 startup.
2. Optimize cable diag
3. Set Co-Clock default enable
4. Enable EMI Calibration Function
5. Enhance AN control mechanism
6. Fix internal bus arbitrator issue

=====================================================================
If your board that GMAC2 connects with Airoha EN8811H, please change
the eth node as following.

&eth {
	...

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-mode = "2500base-x";
		phy-handle = <&phy15>;
	};

	mdio: mdio-bus {
      		#address-cells = <1>;
      		#size-cells = <0>;

      		phy15: phy@15 {
       			compatible = "ethernet-phy-id03a2.a411";
			reg = <15>;
			phy-mode = "2500base-x";
			airoha,polarity = <1>;
			airoha,surge = <0>;
		};

       		...
	};
};

Note:
SerDes polarity setting could be configured in dts. Please refer to the
following description.
Tx Reverse, Rx Normal:
		airoha,polarity = <0>;
Tx Normal, Rx Normal:
		airoha,polarity = <1>;
Tx Reverse, Rx Reverse:
		airoha,polarity = <2>;
Tx Normal, Rx Reverse:
		airoha,polarity = <3>;

Surge protection setting could be configured in dts. Please refer to the
following description.
Surge protection - 0R
		airoha,surge = <0>;
Surge protection - 5R
		airoha,surge = <1>;

=====================================================================
In addition, if EN8811H connects with a RESET GPIO, please check the
GPIO number, and then add reset-gpio related definition to above phy
node.
=====================================================================
reset-gpios = <&gpio 6 1>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
=====================================================================

If without this patch, kernel cannot load up-to-date PHY driver
for the Airoha EN8811H.

[Release-log]
N/A


Change-Id: I7946e9251d2847f05a1b9fae5a80ed89c5ba6ed6
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/9785613

12 files changed

tree: 279f37e06854a8e4918e978695b5298f0eeddeab

Readme.md

Brief introduction for using MediaTek released OpenWrt SDK

1. Build system setup

Please refer to https://openwrt.org/docs/guide-developer/toolchain/install-buildsystem

2. Clone vanilla OpenWrt

Currently two release branches are supported:

21.02 This is the current in-use branch

git clone -b openwrt-21.02 https://git.openwrt.org/openwrt/openwrt.git

master (will be 24.0x branch later) The next version in development
```
git clone https://git.openwrt.org/openwrt/openwrt.git
```

3. Add MediaTek OpenWrt feed

cd openwrt
echo "src-git mtk_openwrt_feed https://git01.mediatek.com/openwrt/feeds/mtk-openwrt-feeds" >> feeds.conf.default
./scripts/feeds update -a
./scripts/feeds install -a

4. Apply MediaTek OpenWrt files and patches

21.02 branch

cp -af ./feeds/mtk_openwrt_feed/21.02/files/* .
cp -af ./feeds/mtk_openwrt_feed/tools .
for file in $(find ./feeds/mtk_openwrt_feed/21.02/patches-base -name "*.patch" | sort); do patch -f -p1 -i ${file}; done
for file in $(find ./feeds/mtk_openwrt_feed/21.02/patches-feeds -name "*.patch" | sort); do patch -f -p1 -i ${file}; done

master branch

cp -af ./feeds/mtk_openwrt_feed/master/files/* .
for file in $(find ./feeds/mtk_openwrt_feed/master/patches-base -name "*.patch" | sort); do patch -f -p1 -i ${file}; done

5. Configuration

make menuconfig

21.02 branch

Target System -> MediaTek Ralink ARM
Subtarget -> MT7981 / MT7986 / MT7988
Target Profile -> select as needed

master branch

Target System -> MediaTek Ralink ARM
Subtarget -> Filogic 8x0 (MT798x)
Target Profile -> select as needed

6. Build

make V=s -j$(nproc)