commit abfa2338ef46aace658a43e8be89970bd533f6ba
author developer <developer@mediatek.com> Wed Aug 09 09:11:12 2023 +0800
committer developer <developer@mediatek.com> Thu Aug 17 08:41:58 2023 +0800
tree f2a55ae38ea465f924cb8c3e26c0ad5fb984635c
parent e5e687da6750cafd0f6095fcf1d1790fe1a85a95

[][openwrt][mt7988][arm64: dts: mt7988: add tops pce device tree node]

[Description]
Add TOPS and PCE device tree node.
TOPS is used for tunnel offload engine.
PCE is used for packet classification engine.

[Release-log]
N/A

Change-Id: I297a0c2054030544aa366549743d39088b76ebc8
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7854797

target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi

diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
index 3033801..92b32c5 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
@@ -370,6 +370,61 @@
 
 	};
 
+	tops: tops@09100000 {
+		compatible = "mediatek,tops";
+		reg = <0 0x09100000 0 0x01000000>;
+		reg-names = "tops-base";
+		clocks = <&topckgen CK_TOP_BUS_TOPS_SEL>,
+			 <&topckgen CK_TOP_TOPS_P2_26M_SEL>,
+			 <&topckgen CK_TOP_NETSYS_TOPS_400M_SEL>,
+			 <&topckgen CK_TOP_NPU_TOPS_SEL>,
+			 <&topckgen CK_TOP_CK_NPU_SEL_CM_TOPS_SEL>;
+		clock-names = "bus", "sram", "xdma", "offload", "mgmt";
+		power-domains = <&topmisc MT7988_POWER_DOMAIN_TOPS0>,
+				<&topmisc MT7988_POWER_DOMAIN_TOPS1>;
+
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "tdma-tx-pause", "mbox", "wdt";
+
+		dmas = <&hpdma1 0>;
+		dma-names = "tnl-sync";
+
+		fe_mem = <&eth>;
+	};
+
+	tops-mbox {
+		compatible = "mediatek,tops-mbox";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "mbox";
+		tops = <&tops>;
+	};
+
+	hpdma1: hpdma@09106000 {
+		compatible = "mediatek,hpdma-top";
+		reg = <0 0x09106000 0 0x1000>;
+		reg-names = "base";
+		#dma-cells = <1>;
+	};
+
+	hpdma2: hpdma@09606000 {
+		compatible = "mediatek,hpdma-sub";
+		reg = <0 0x09606000 0 0x1000>;
+		reg-names = "base";
+		#dma-cells = <2>;
+	};
+
+	tops-ocd@0e500000 {
+		compatible = "mediatek,tops-ocd";
+		reg = <0 0x0e500000 0 0x15000>;
+		reg-names = "tops-ocd-base";
+		clocks = <&infracfg_ao CK_INFRA_AUD_L>;
+		clock-names = "debugsys";
+	};
+
 	watchdog: watchdog@1001c000 {
 		compatible = "mediatek,mt7622-wdt",
 			     "mediatek,mt6589-wdt",
@@ -865,6 +920,12 @@
 		status = "disabled";
 	};
 
+	pce: pce@15100000 {
+		compatible = "mediatek,pce";
+
+		fe_mem = <&eth>;
+	};
+
 	sgmiisys0: syscon@10060000 {
 		compatible = "mediatek,mt7988-sgmiisys",
 			     "mediatek,mt7988-sgmiisys_0",