[][kernel][mt7988][eth][Refactor 8GB_ADDRESSING to the upstream style]
[Description]
Refactor 8GB_ADDRESSING to the upstream style.
[Release-log]
N/A
Change-Id: I16abc9101aeb7b42000b7d007e578d8c7cbe4f21
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/9236901
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 52ff3ca..cb77ed0 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1699,7 +1699,6 @@
dma_addr_t phy_ring_tail;
int cnt = soc->txrx.fq_dma_size;
dma_addr_t dma_addr;
- u64 addr64 = 0;
int i, j, len;
if (!eth->soc->has_sram) {
@@ -1739,10 +1738,10 @@
txd->txd2 = eth->phy_scratch_ring +
(j * MTK_FQ_DMA_LENGTH + i + 1) * soc->txrx.txd_size;
- addr64 = (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) ?
- TX_DMA_SDP1(dma_addr + i * MTK_QDMA_PAGE_SIZE) : 0;
+ txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
+ txd->txd3 |= TX_DMA_PREP_ADDR64(dma_addr + i * MTK_QDMA_PAGE_SIZE);
- txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE) | addr64;
txd->txd4 = 0;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
@@ -1839,8 +1838,8 @@
dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
dma_unmap_len_set(tx_buf, dma_len0, size);
} else {
- addr64 = (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) ?
- TX_DMA_SDP1(mapped_addr) : 0;
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
+ addr64 = TX_DMA_PREP_ADDR64(mapped_addr);
if (idx & 1) {
txd->txd3 = mapped_addr;
@@ -1957,18 +1956,18 @@
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
struct mtk_tx_dma_v2 *desc = txd;
- u64 addr64 = 0;
u32 data = 0;
- addr64 = (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) ?
- TX_DMA_SDP1(info->addr) : 0;
-
WRITE_ONCE(desc->txd1, info->addr);
data = TX_DMA_PLEN0(info->size);
if (info->last)
data |= TX_DMA_LS0;
- WRITE_ONCE(desc->txd3, data | addr64);
+
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
+ data |= TX_DMA_PREP_ADDR64(info->addr);
+
+ WRITE_ONCE(desc->txd3, data);
data = ((mac->id == MTK_GMAC3_ID) ?
PSE_GDM3_PORT : (mac->id + 1)) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
@@ -2444,8 +2443,8 @@
goto release_desc;
}
- addr64 = (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) ?
- ((u64)(trxd.rxd2 & 0xf)) << 32 : 0;
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
+ addr64 = RX_DMA_GET_ADDR64(trxd.rxd2);
dma_unmap_single(eth->dma_dev,
((u64)(trxd.rxd1) | addr64),
@@ -2532,11 +2531,11 @@
rxd->rxd1 = (unsigned int)dma_addr;
release_desc:
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) {
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
if (unlikely(dma_addr == DMA_MAPPING_ERROR))
- addr64 = RX_DMA_GET_SDP1(rxd->rxd2);
+ addr64 = RX_DMA_GET_ADDR64(rxd->rxd2);
else
- addr64 = RX_DMA_SDP1(dma_addr);
+ addr64 = RX_DMA_PREP_ADDR64(dma_addr);
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
@@ -2952,7 +2951,6 @@
struct mtk_rx_ring *ring;
int rx_data_len, rx_dma_size;
int i;
- u64 addr64 = 0;
if (rx_flag == MTK_RX_FLAGS_QDMA) {
if (ring_no)
@@ -3024,13 +3022,13 @@
rxd = ring->dma + i * eth->soc->txrx.rxd_size;
rxd->rxd1 = (unsigned int)dma_addr;
- addr64 = (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) ?
- RX_DMA_SDP1(dma_addr) : 0;
-
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
rxd->rxd2 = RX_DMA_LSO;
else
- rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size) | addr64;
+ rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
+
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
+ rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr);
rxd->rxd3 = 0;
rxd->rxd4 = 0;
@@ -3093,9 +3091,8 @@
if (!rxd->rxd1)
continue;
- addr64 = (MTK_HAS_CAPS(eth->soc->caps,
- MTK_8GB_ADDRESSING)) ?
- ((u64)(rxd->rxd2 & 0xf)) << 32 : 0;
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
+ addr64 = RX_DMA_GET_ADDR64(rxd->rxd2);
dma_unmap_single(eth->dma_dev,
((u64)(rxd->rxd1) | addr64),
@@ -5619,7 +5616,7 @@
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
eth->ip_align = NET_IP_ALIGN;
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) {
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
if (!err) {
err = dma_set_coherent_mask(&pdev->dev,
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 66c2a54..8a01325 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -653,7 +653,14 @@
#define TX_DMA_PLEN1(_x) ((_x) & eth->soc->txrx.dma_max_len)
#endif
#define TX_DMA_SWC BIT(14)
-#define TX_DMA_SDP1(_x) ((((u64)(_x)) >> 32) & 0xf)
+#define TX_DMA_ADDR64_MASK GENMASK(3, 0)
+#if IS_ENABLED(CONFIG_64BIT)
+# define TX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(TX_DMA_ADDR64_MASK, (x))) << 32)
+# define TX_DMA_PREP_ADDR64(x) FIELD_PREP(TX_DMA_ADDR64_MASK, ((x) >> 32))
+#else
+# define TX_DMA_GET_ADDR64(x) (0)
+# define TX_DMA_PREP_ADDR64(x) (0)
+#endif
/* PDMA on MT7628 */
#define TX_DMA_DONE BIT(31)
@@ -676,8 +683,14 @@
#define RX_DMA_GET_AGG_CNT(_x) (((_x) >> 2) & 0xff)
#define RX_DMA_GET_REV(_x) (((_x) >> 10) & 0x1f)
#define RX_DMA_VTAG BIT(15)
-#define RX_DMA_SDP1(_x) ((((u64)(_x)) >> 32) & 0xf)
-#define RX_DMA_GET_SDP1(_x) ((_x) & 0xf)
+#define RX_DMA_ADDR64_MASK GENMASK(3, 0)
+#if IS_ENABLED(CONFIG_64BIT)
+# define RX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(RX_DMA_ADDR64_MASK, (x))) << 32)
+# define RX_DMA_PREP_ADDR64(x) FIELD_PREP(RX_DMA_ADDR64_MASK, ((x) >> 32))
+#else
+# define RX_DMA_GET_ADDR64(x) (0)
+# define RX_DMA_PREP_ADDR64(x) (0)
+#endif
/* QDMA descriptor rxd3 */
#define RX_DMA_VID(_x) ((_x) & VLAN_VID_MASK)
@@ -1489,7 +1502,7 @@
MTK_RSTCTRL_PPE1_BIT,
MTK_RSTCTRL_PPE2_BIT,
MTK_U3_COPHY_V2_BIT,
- MTK_8GB_ADDRESSING_BIT,
+ MTK_36BIT_DMA_BIT,
/* MUX BITS*/
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
@@ -1541,7 +1554,7 @@
#define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
#define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT)
-#define MTK_8GB_ADDRESSING BIT_ULL(MTK_8GB_ADDRESSING_BIT)
+#define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT)
#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
@@ -1655,7 +1668,7 @@
MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \
MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII | \
MTK_GMAC2_XGMII | MTK_MUX_GMAC2_TO_XGMII | MTK_RSS | \
- MTK_NETSYS_RX_V2 | MTK_8GB_ADDRESSING)
+ MTK_NETSYS_RX_V2 | MTK_36BIT_DMA)
struct mtk_tx_dma_desc_info {
dma_addr_t addr;
diff --git a/21.02/files/target/linux/mediatek/patches-5.4/999-4102-mtk-crypto-offload-support.patch b/21.02/files/target/linux/mediatek/patches-5.4/999-4102-mtk-crypto-offload-support.patch
index e814f34..f765ed5 100644
--- a/21.02/files/target/linux/mediatek/patches-5.4/999-4102-mtk-crypto-offload-support.patch
+++ b/21.02/files/target/linux/mediatek/patches-5.4/999-4102-mtk-crypto-offload-support.patch
@@ -6,8 +6,8 @@
u8 tport = 0;
+ u8 cdrt = 0;
- addr64 = (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) ?
- TX_DMA_SDP1(info->addr) : 0;
+ WRITE_ONCE(desc->txd1, info->addr);
+
@@ -2019,11 +2020,25 @@ static void mtk_tx_set_dma_desc_v3(struc
trace_printk("[%s] skb_shinfo(skb)->nr_frags=%x HNAT_SKB_CB2(skb)->magic=%x txd4=%x<-----\n",
__func__, skb_shinfo(skb)->nr_frags, HNAT_SKB_CB2(skb)->magic, data);
diff --git a/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3021-mtk-wed-add-dma-mask-limitation-and-GFP_DMA32-for-bo.patch b/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3021-mtk-wed-add-dma-mask-limitation-and-GFP_DMA32-for-bo.patch
index d3747af..0ad8ba7 100644
--- a/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3021-mtk-wed-add-dma-mask-limitation-and-GFP_DMA32-for-bo.patch
+++ b/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3021-mtk-wed-add-dma-mask-limitation-and-GFP_DMA32-for-bo.patch
@@ -45,7 +45,7 @@
desc->info = 0;
} else {
- desc->ctrl = cpu_to_le32(token << 16);
-+ ctrl = token << 16 | TX_DMA_SDP1(buf_phys);
++ ctrl = token << 16 | TX_DMA_PREP_ADDR64(buf_phys);
}
+ desc->ctrl = cpu_to_le32(ctrl);
@@ -64,7 +64,7 @@
buf_phys = page_phys;
for (s = 0; s < MTK_WED_RX_PAGE_BUF_PER_PAGE; s++) {
desc->buf0 = cpu_to_le32(buf_phys);
-+ desc->token = cpu_to_le32(RX_DMA_SDP1(buf_phys));
++ desc->token = cpu_to_le32(RX_DMA_PREP_ADDR64(buf_phys));
desc++;
buf += MTK_WED_PAGE_BUF_SIZE;
buf_phys += MTK_WED_PAGE_BUF_SIZE;