diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.c b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.c
index 9b4c7f9..64076b7 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.c
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.c
@@ -42,6 +42,41 @@
 	reset_event->count[id]++;
 }
 
+static void mtk_dump_reg(void *_eth, char *name, u32 offset, u32 range)
+{
+	struct mtk_eth *eth = _eth;
+	u32 cur = offset;
+
+	pr_info("\n============ %s ============\n", name);
+	while (cur < offset + range) {
+		pr_info("0x%x: %08x %08x %08x %08x\n",
+			cur, mtk_r32(eth, cur), mtk_r32(eth, cur + 0x4),
+			mtk_r32(eth, cur + 0x8), mtk_r32(eth, cur + 0xc));
+		cur += 0x10;
+	}
+}
+
+static void mtk_dump_regmap(struct regmap *pmap, char *name,
+			    u32 offset, u32 range)
+{
+	unsigned int cur = offset;
+	unsigned int val1 = 0, val2 = 0, val3 = 0, val4 = 0;
+
+	if (!pmap)
+		return;
+
+	pr_info("\n============ %s ============\n", name);
+	while (cur < offset + range) {
+		regmap_read(pmap, cur, &val1);
+		regmap_read(pmap, cur + 0x4, &val2);
+		regmap_read(pmap, cur + 0x8, &val3);
+		regmap_read(pmap, cur + 0xc, &val4);
+		pr_info("0x%x: %08x %08x %08x %08x\n",
+			cur, val1, val2, val3, val4);
+		cur += 0x10;
+	}
+}
+
 int mtk_eth_cold_reset(struct mtk_eth *eth)
 {
 	u32 reset_bits = 0;
@@ -89,6 +124,7 @@
 	}
 
 	if (i < 1000) {
+		done = 1;
 		reset_bits = RSTCTRL_ETH | RSTCTRL_PPE0;
 		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
 			reset_bits |= RSTCTRL_PPE1;
@@ -105,27 +141,51 @@
 
 		udelay(1);
 		regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val2);
-		if (!(val2 & reset_bits))
+		if (!(val2 & reset_bits)) {
 			pr_info("[%s] error val2=0x%x reset_bits=0x%x !\n",
 				__func__, val2, reset_bits);
+			done = 0;
+		}
 		reset_bits |= RSTCTRL_FE;
 		regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
 				   reset_bits, ~reset_bits);
-
 		udelay(1);
 		regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val3);
-		if (val3 & reset_bits)
+		if (val3 & reset_bits) {
 			pr_info("[%s] error val3=0x%x reset_bits=0x%x !\n",
 				__func__, val3, reset_bits);
-		done = 1;
+			done = 0;
+		}
 		mtk_reset_event_update(eth, MTK_EVENT_WARM_CNT);
 	}
 
 	pr_info("[%s] reset record val1=0x%x, val2=0x%x, val3=0x%x i:%d done:%d\n",
 		__func__, val1, val2, val3, i, done);
 
-	if (!done)
+	if (!done) {
+		mtk_dump_reg(eth, "FE", 0x0, 0x300);
+		mtk_dump_reg(eth, "ADMA", PDMA_BASE + 0x200, 0x10);
+		mtk_dump_reg(eth, "QDMA", QDMA_BASE + 0x200, 0x10);
+		mtk_dump_reg(eth, "WDMA0", WDMA_BASE(0) + 0x200, 0x10);
+		mtk_dump_reg(eth, "WDMA1", WDMA_BASE(1) + 0x200, 0x10);
+		mtk_dump_reg(eth, "PPE0", PPE_BASE(0), 0x10);
+		mtk_dump_reg(eth, "PPE0", PPE_BASE(0) + 0x180, 0x20);
+		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
+			mtk_dump_reg(eth, "PPE1", PPE_BASE(1), 0x10);
+			mtk_dump_reg(eth, "PPE1", PPE_BASE(1) + 0x180, 0x20);
+		}
+		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
+			mtk_dump_reg(eth, "PPE2", PPE_BASE(2), 0x10);
+			mtk_dump_reg(eth, "PPE2", PPE_BASE(2) + 0x180, 0x20);
+			regmap_write(eth->ethsys, ETHSYS_LP_NONE_IDLE_LAT0, 0xffffffff);
+			regmap_write(eth->ethsys, ETHSYS_LP_NONE_IDLE_LAT1, 0xffffffff);
+			regmap_read(eth->ethsys, ETHSYS_LP_NONE_IDLE_LAT0, &val1);
+			regmap_read(eth->ethsys, ETHSYS_LP_NONE_IDLE_LAT1, &val2);
+			pr_info("ETHSYS_LP_NONE_IDLE_LAT0:%x\n", val1);
+			pr_info("ETHSYS_LP_NONE_IDLE_LAT1:%x\n", val2);
+		}
 		mtk_eth_cold_reset(eth);
+	}
 
 	return 0;
 }
@@ -187,41 +247,6 @@
 	return IRQ_HANDLED;
 }
 
-static void mtk_dump_reg(void *_eth, char *name, u32 offset, u32 range)
-{
-	struct mtk_eth *eth = _eth;
-	u32 cur = offset;
-
-	pr_info("\n============ %s ============\n", name);
-	while(cur < offset + range) {
-		pr_info("0x%x: %08x %08x %08x %08x\n",
-			cur, mtk_r32(eth, cur), mtk_r32(eth, cur + 0x4),
-			mtk_r32(eth, cur + 0x8), mtk_r32(eth, cur + 0xc));
-		cur += 0x10;
-	}
-}
-
-static void mtk_dump_regmap(struct regmap *pmap, char *name,
-			    u32 offset, u32 range)
-{
-	unsigned int cur = offset;
-	unsigned int val1 = 0, val2 = 0, val3 = 0, val4 = 0;
-
-	if (!pmap)
-		return;
-
-	pr_info("\n============ %s ============\n", name);
-	while (cur < offset + range) {
-		regmap_read(pmap, cur, &val1);
-		regmap_read(pmap, cur + 0x4, &val2);
-		regmap_read(pmap, cur + 0x8, &val3);
-		regmap_read(pmap, cur + 0xc, &val4);
-		pr_info("0x%x: %08x %08x %08x %08x\n",
-			cur, val1, val2, val3, val4);
-		cur += 0x10;
-	}
-}
-
 void mtk_dump_netsys_info(void *_eth)
 {
 	struct mtk_eth *eth = _eth;
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 5a0f9e9..16b7141 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -4774,6 +4774,7 @@
 				if (!wait_for_completion_timeout(&wait_ser_done,
 								 msecs_to_jiffies(3000)))
 					pr_warn("wait for MTK_FE_START_RESET\n");
+				mtk_stop_fail = 0;
 			}
 			pr_warn("wait for MTK_FE_START_RESET\n");
 		}
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 305ede6..0a59c78 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -894,6 +894,10 @@
 /* ethernet reset check idle register */
 #define ETHSYS_FE_RST_CHK_IDLE_EN 	0x28
 
+/* ethernet non-idle check register */
+#define ETHSYS_LP_NONE_IDLE_LAT0 (0x144)
+#define ETHSYS_LP_NONE_IDLE_LAT1 (0x148)
+
 /* ethernet dma channel agent map */
 #define ETHSYS_DMA_AG_MAP	0x408
 #define ETHSYS_DMA_AG_MAP_PDMA	BIT(0)