[][Critical][mt7988][SPI][Change SPI1 clk]
[Description]
Change SPI1 source clk.
The clock structure of SPI1 is diffrent from SPI0/SPI2.
Without this patch, you will not be able to use SPI1 normally.
[Release-log]
N/A
Change-Id: I4ad5e1104b1b4f6e620f76e7c82f8f6c185e99c8
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/9014489
diff --git a/21.02/files/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi b/21.02/files/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
index 0fd2d47..9abe45f 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
+++ b/21.02/files/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
@@ -1057,7 +1057,7 @@
reg = <0 0x11008000 0 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_TOP_SPI_SEL>,
+ <&topckgen CK_TOP_SPIM_MST_SEL>,
<&infracfg_ao CK_INFRA_104M_SPI1>,
<&infracfg_ao CK_INFRA_66M_SPI1_HCK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";