[][openwrt][mt7988][eth][Add Ethernet RSS full support for Jaguar]
[Description]
Add Ethernet RSS full support for Jaguar.
In the past, RSS events are assigned to FE interrupts (GIC_ID: 196~199);
currently, RSS events would be assigned to ADMA-dedicated
interrupts (GIC_ID: 189~192) instead. In this way, RSS won't be limited
by the number of FE interrupts anymore, and thus can be extended
to 4-RSS Rx rings.
If without this patch, Ethernet can only enable 2-RSS Rx rings
due to the limitation of FE interrupt number.
[Usage]
Assume IRQ numbers of Ethernet Rx interrupts are 124~127 (shown in
cat /proc/interrupts).
Then we can adjust smp affinity to decide which CPU is going to
process those Rx interrupts.
The below example shows how we utilize 3-CPU to process Rx interrupts.
- echo 1 > /proc/irq/124/smp_affinity (CPU0 processes IRQ 124)
- echo 2 > /proc/irq/125/smp_affinity (CPU1 processes IRQ 125)
- echo 4 > /proc/irq/126/smp_affinity (CPU2 processes IRQ 126)
- echo 4 > /proc/irq/127/smp_affinity (CPU2 processes IRQ 127)
[Release-log]
N/A
Change-Id: I3df05df5863e9cb5288bb6db5113d3bc75ce46ad
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7514813
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 2082ec6..e95e3dc 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -86,6 +86,9 @@
#define MTK_FE_INT_RFIFO_UF BIT(19)
#define MTK_GDM1_AF BIT(28)
#define MTK_GDM2_AF BIT(29)
+#define MTK_FE_IRQ_NUM (4)
+#define MTK_PDMA_IRQ_NUM (4)
+#define MTK_MAX_IRQ_NUM (MTK_FE_IRQ_NUM + MTK_PDMA_IRQ_NUM)
/* PDMA HW LRO Alter Flow Timer Register */
#define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
@@ -254,14 +257,12 @@
/* PDMA RSS Control Registers */
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
#define MTK_PDMA_RSS_GLO_CFG (PDMA_BASE + 0x800)
-#define MTK_RX_NAPI_NUM (2)
-#define MTK_MAX_IRQ_NUM (4)
+#define MTK_RX_NAPI_NUM (4)
#else
#define MTK_PDMA_RSS_GLO_CFG 0x2800
#define MTK_RX_NAPI_NUM (1)
-#define MTK_MAX_IRQ_NUM (3)
#endif
-#define MTK_RSS_RING1 (1)
+#define MTK_RSS_RING(x) (x)
#define MTK_RSS_EN BIT(0)
#define MTK_RSS_CFG_REQ BIT(2)
#define MTK_RSS_IPV6_STATIC_HASH (0x7 << 8)
@@ -274,7 +275,7 @@
#define MTK_RSS_INDR_TABLE_DW5 (MTK_PDMA_RSS_GLO_CFG + 0x64)
#define MTK_RSS_INDR_TABLE_DW6 (MTK_PDMA_RSS_GLO_CFG + 0x68)
#define MTK_RSS_INDR_TABLE_DW7 (MTK_PDMA_RSS_GLO_CFG + 0x6C)
-#define MTK_RSS_INDR_TABLE_SIZE4 0x44444444
+#define MTK_RSS_INDR_TABLE_SIZE4 0x39393939
/* PDMA Global Configuration Register */
#define MTK_PDMA_GLO_CFG (PDMA_BASE + 0x204)
@@ -445,12 +446,13 @@
/* QDMA Interrupt Status Register */
#define MTK_QDMA_INT_STATUS (QDMA_BASE + 0x218)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
-#define MTK_RX_DONE_INT(ring_no) \
+#define MTK_RX_DONE_INT(ring_no) \
(MTK_HAS_CAPS(eth->soc->caps, MTK_RSS) ? (BIT(24 + (ring_no))) : \
((ring_no) ? BIT(16 + (ring_no)) : BIT(14)))
#else
-#define MTK_RX_DONE_INT(ring_no) \
- ((ring_no)? BIT(24 + (ring_no)) : BIT(30))
+#define MTK_RX_DONE_INT(ring_no) \
+ (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS) ? (BIT(16 + (ring_no))) : \
+ ((ring_no) ? BIT(24 + (ring_no)) : BIT(30)))
#endif
#define MTK_RX_DONE_INT3 BIT(19)
#define MTK_RX_DONE_INT2 BIT(18)
@@ -1767,7 +1769,8 @@
struct net_device dummy_dev;
struct net_device *netdev[MTK_MAX_DEVS];
struct mtk_mac *mac[MTK_MAX_DEVS];
- int irq[MTK_MAX_IRQ_NUM];
+ int irq_fe[MTK_FE_IRQ_NUM];
+ int irq_pdma[MTK_PDMA_IRQ_NUM];
u8 hwver;
u32 msg_enable;
unsigned long sysclk;