commit 94806ecf62f6e2c511dc5e5be69867d41ea12671
author developer <developer@mediatek.com> Fri May 19 14:16:44 2023 +0800
committer developer <developer@mediatek.com> Mon May 22 17:15:58 2023 +0800
tree ac0325c691703c6b02e5191e845c0c7a706fc4de
parent a0210aa6e4aa990cbff8b5cb343b4f39249cdc19

[][openwrt][mt7988][eth][Add Ethernet RSS full support for Jaguar]

[Description]
Add Ethernet RSS full support for Jaguar.
In the past, RSS events are assigned to FE interrupts (GIC_ID: 196~199);
currently, RSS events would be assigned to ADMA-dedicated
interrupts (GIC_ID: 189~192) instead. In this way, RSS won't be limited
by the number of FE interrupts anymore, and thus can be extended
to 4-RSS Rx rings.

If without this patch, Ethernet can only enable 2-RSS Rx rings
due to the limitation of FE interrupt number.

[Usage]
Assume IRQ numbers of Ethernet Rx interrupts are 124~127 (shown in
cat /proc/interrupts).
Then we can adjust smp affinity to decide which CPU is going to
process those Rx interrupts.
The below example shows how we utilize 3-CPU to process Rx interrupts.
   - echo 1 > /proc/irq/124/smp_affinity  (CPU0 processes IRQ 124)
   - echo 2 > /proc/irq/125/smp_affinity  (CPU1 processes IRQ 125)
   - echo 4 > /proc/irq/126/smp_affinity  (CPU2 processes IRQ 126)
   - echo 4 > /proc/irq/127/smp_affinity  (CPU2 processes IRQ 127)

[Release-log]
N/A


Change-Id: I3df05df5863e9cb5288bb6db5113d3bc75ce46ad
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7514813

target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi

diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
index 666fddb..96c68a5 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
@@ -377,10 +377,14 @@
         eth: ethernet@15100000 {
                 compatible = "mediatek,mt7986-eth";
                 reg = <0 0x15100000 0 0x80000>;
-                interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&ethsys CK_ETH_FE_EN>,
                          <&ethsys CK_ETH_GP2_EN>,
                          <&ethsys CK_ETH_GP1_EN>,