[][MT7981 SPIM NAND: backport gigadevice.c of kernel v6.4 to v5.4]
[Description]
Add new serial gigadevice nand, and fix dummy byte issue, align with
kernel v6.4, and remove unnecessary device support.
source code link:
https://elixir.bootlin.com/linux/v6.4.9/source/drivers/mtd/nand/spi/gigadevice.c
[Release-log]
N/A
Change-Id: I25701d600439d546d876142a812d9ec7b8bbc266
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7871637
diff --git a/target/linux/mediatek/patches-5.4/999-2333-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB-and-GD5F1GQ5UExxG.patch b/target/linux/mediatek/patches-5.4/999-2333-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB-and-GD5F1GQ5UExxG.patch
deleted file mode 100644
index d37dd56..0000000
--- a/target/linux/mediatek/patches-5.4/999-2333-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB-and-GD5F1GQ5UExxG.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 39ee4e9fb5fd3ce678223147df9d9bef0ce822cd Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:15 +0800
-Subject: [PATCH]
- [spi-and-storage][999-2333-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB-and-GD5F1GQ5UExxG.patch]
-
----
- drivers/mtd/nand/spi/gigadevice.c | 21 ++++++++++++++++++++-
- 1 file changed, 20 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
-index 937a04ce6..ce88f0c91 100644
---- a/drivers/mtd/nand/spi/gigadevice.c
-+++ b/drivers/mtd/nand/spi/gigadevice.c
-@@ -39,6 +39,15 @@ static SPINAND_OP_VARIANTS(read_cache_variants_f,
- SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
-
-+/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */
-+static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants,
-+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
-+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
-+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
-+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
-+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-+
- static SPINAND_OP_VARIANTS(write_cache_variants,
- SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
- SPINAND_PROG_LOAD(true, 0, NULL, 0));
-@@ -236,6 +245,16 @@ static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
- }
-
- static const struct spinand_info gigadevice_spinand_table[] = {
-+ SPINAND_INFO("F50L1G41LB",
-+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
-+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ 0,
-+ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
-+ gd5fxgq4xa_ecc_get_status)),
- SPINAND_INFO("GD5F1GQ4xA",
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
- NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-@@ -290,7 +309,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
- NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
- NAND_ECCREQ(4, 512),
-- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- SPINAND_HAS_QE_BIT,
---
-2.34.1
-
diff --git a/target/linux/mediatek/patches-5.4/999-2334-mtd-spinand-gigadevice-Add-support-for-GD5FxGQxUExxG-GD5FxGQxUExxH-and-GD5FxGMxUExxG-series.patch b/target/linux/mediatek/patches-5.4/999-2334-mtd-spinand-gigadevice-Add-support-for-GD5FxGQxUExxG-GD5FxGQxUExxH-and-GD5FxGMxUExxG-series.patch
deleted file mode 100644
index c609bd7..0000000
--- a/target/linux/mediatek/patches-5.4/999-2334-mtd-spinand-gigadevice-Add-support-for-GD5FxGQxUExxG-GD5FxGQxUExxH-and-GD5FxGMxUExxG-series.patch
+++ /dev/null
@@ -1,143 +0,0 @@
-From b8ffe42101eb8abfb6530396e0c74a85b43eed44 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:15 +0800
-Subject: [PATCH]
- [spi-and-storage][999-2334-mtd-spinand-gigadevice-Add-support-for-GD5FxGQxUExxG-GD5FxGQxUExxH-and-GD5FxGMxUExxG-series.patch]
-
----
- drivers/mtd/nand/spi/gigadevice.c | 98 +++++++++++++++++++++++++++++--
- 1 file changed, 94 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
-index ce88f0c91..a4e89529d 100644
---- a/drivers/mtd/nand/spi/gigadevice.c
-+++ b/drivers/mtd/nand/spi/gigadevice.c
-@@ -39,8 +39,9 @@ static SPINAND_OP_VARIANTS(read_cache_variants_f,
- SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
-
--/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */
--static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants,
-+/* For Q5 devices, QUADIO use different dummy byte settings */
-+/* Q5 1Gb */
-+static SPINAND_OP_VARIANTS(dummy2_read_cache_variants,
- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
-@@ -48,6 +49,15 @@ static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants,
- SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-
-+/* Q5 2Gb & 4Gb */
-+static SPINAND_OP_VARIANTS(dummy4_read_cache_variants,
-+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
-+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
-+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
-+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
-+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-+
- static SPINAND_OP_VARIANTS(write_cache_variants,
- SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
- SPINAND_PROG_LOAD(true, 0, NULL, 0));
-@@ -249,7 +259,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
- NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
- NAND_ECCREQ(8, 512),
-- SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants,
-+ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- 0,
-@@ -309,7 +319,87 @@ static const struct spinand_info gigadevice_spinand_table[] = {
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
- NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
- NAND_ECCREQ(4, 512),
-- SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants,
-+ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+ gd5fxgq5xexxg_ecc_get_status)),
-+ SPINAND_INFO("GD5F2GQ5UExxG",
-+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
-+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+ NAND_ECCREQ(4, 512),
-+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+ gd5fxgq5xexxg_ecc_get_status)),
-+ SPINAND_INFO("GD5F4GQ6UExxG",
-+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55),
-+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
-+ NAND_ECCREQ(4, 512),
-+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+ gd5fxgq5xexxg_ecc_get_status)),
-+ SPINAND_INFO("GD5F1GM7UExxG",
-+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91),
-+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+ gd5fxgq4uexxg_ecc_get_status)),
-+ SPINAND_INFO("GD5F2GM7UExxG",
-+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92),
-+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+ gd5fxgq4uexxg_ecc_get_status)),
-+ SPINAND_INFO("GD5F4GM8UExxG",
-+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95),
-+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+ gd5fxgq4uexxg_ecc_get_status)),
-+ SPINAND_INFO("GD5F1GQ5UExxH",
-+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31),
-+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+ NAND_ECCREQ(4, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+ gd5fxgq5xexxg_ecc_get_status)),
-+ SPINAND_INFO("GD5F2GQ5UExxH",
-+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
-+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
-+ NAND_ECCREQ(4, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+ gd5fxgq5xexxg_ecc_get_status)),
-+ SPINAND_INFO("GD5F4GQ6UExxH",
-+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
-+ NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
-+ NAND_ECCREQ(4, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- SPINAND_HAS_QE_BIT,
---
-2.34.1
-
diff --git a/target/linux/mediatek/patches-5.4/999-2335-mtd-spinand-fix-gigadevice-read-dummy.patch b/target/linux/mediatek/patches-5.4/999-2335-mtd-spinand-fix-gigadevice-read-dummy.patch
deleted file mode 100644
index 977c65c..0000000
--- a/target/linux/mediatek/patches-5.4/999-2335-mtd-spinand-fix-gigadevice-read-dummy.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From be41be0e740933fa976ad2990b94ef1e62542a8e Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:15 +0800
-Subject: [PATCH]
- [spi-and-storage][999-2335-mtd-spinand-fix-gigadevice-read-dummy.patch]
-
----
- drivers/mtd/nand/spi/gigadevice.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
-index a4e89529d..b163ea5dc 100644
---- a/drivers/mtd/nand/spi/gigadevice.c
-+++ b/drivers/mtd/nand/spi/gigadevice.c
-@@ -379,7 +379,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31),
- NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
- NAND_ECCREQ(4, 512),
-- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- SPINAND_HAS_QE_BIT,
-@@ -389,17 +389,17 @@ static const struct spinand_info gigadevice_spinand_table[] = {
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
- NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
- NAND_ECCREQ(4, 512),
-- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
- gd5fxgq5xexxg_ecc_get_status)),
- SPINAND_INFO("GD5F4GQ6UExxH",
-- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
-+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
- NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
- NAND_ECCREQ(4, 512),
-- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- SPINAND_HAS_QE_BIT,
---
-2.34.1
-
diff --git a/target/linux/mediatek/patches-5.4/999-2336-mtd-spinand-fix-F50L1G41LB-ecc-check.patch b/target/linux/mediatek/patches-5.4/999-2336-mtd-spinand-fix-F50L1G41LB-ecc-check.patch
deleted file mode 100644
index 644c6b3..0000000
--- a/target/linux/mediatek/patches-5.4/999-2336-mtd-spinand-fix-F50L1G41LB-ecc-check.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From c93adec4ad0e8ca47f1a622fb3a5ae445251af36 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 2 Jun 2023 13:06:16 +0800
-Subject: [PATCH]
- [spi-and-storage][999-2336-mtd-spinand-fix-F50L1G41LB-ecc-check.patch]
-
----
- drivers/mtd/nand/spi/gigadevice.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
-index b163ea5dc..6ee569de2 100644
---- a/drivers/mtd/nand/spi/gigadevice.c
-+++ b/drivers/mtd/nand/spi/gigadevice.c
-@@ -263,8 +263,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
- &write_cache_variants,
- &update_cache_variants),
- 0,
-- SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
-- gd5fxgq4xa_ecc_get_status)),
-+ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, NULL)),
- SPINAND_INFO("GD5F1GQ4xA",
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
- NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
---
-2.34.1
-
diff --git a/target/linux/mediatek/patches-5.4/999-2343-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB.patch b/target/linux/mediatek/patches-5.4/999-2343-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB.patch
new file mode 100644
index 0000000..acf4775
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/999-2343-mtd-spinand-gigadevice-Add-support-for-F50L1G41LB.patch
@@ -0,0 +1,20 @@
+Index: linux-5.4.246/drivers/mtd/nand/spi/gigadevice.c
+===================================================================
+--- linux-5.4.246.orig/drivers/mtd/nand/spi/gigadevice.c
++++ linux-5.4.246/drivers/mtd/nand/spi/gigadevice.c
+@@ -281,6 +281,15 @@ static int gd5fxgq4ufxxg_ecc_get_status(
+ }
+
+ static const struct spinand_info gigadevice_spinand_table[] = {
++ SPINAND_INFO("F50L1G41LB",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
++ &write_cache_variants,
++ &update_cache_variants),
++ 0,
++ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, NULL)),
+ SPINAND_INFO("GD5F1GQ4xA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),