// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2021 MediaTek Inc.
 * Author: Sam.Shih <sam.shih@mediatek.com>
 */

/dts-v1/;
#include "mt7988.dtsi"

/ {
	model = "MediaTek MT7988C DSA 10G SPIM-NOR RFB";
	compatible = "mediatek,mt7988c-dsa-10g-spim-nor",
		     /* Reserve this for DVFS if creating new dts */
		     "mediatek,mt7988";

	chosen {
		bootargs = "console=ttyS0,115200n1 loglevel=8  \
			    earlycon=uart8250,mmio32,0x11000000 \
			    pci=pcie_bus_perf";
	};

	memory {
		reg = <0 0x40000000 0 0x10000000>;
	};

	wsys_adie: wsys_adie@0 {
	// fpga cases need to manual change adie_id / sku_type for dvt only
		compatible = "mediatek,rebb-mt7988-adie";
		adie_id = <7976>;
		sku_type = <3000>;
	};
};

&fan {
	pwms = <&pwm 0 50000 0>;
	status = "okay";
};

&pwm {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&spi1 {
	pinctrl-names = "default";
	/* pin shared with snfi */
	pinctrl-0 = <&spic_pins>;
	status = "disabled";
};

&spi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi2_flash_pins>;
	status = "okay";
	spi_nor@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cal-enable;
		spi-cal-mode = "read-data";
		spi-cal-datalen = <7>;
		spi-cal-data = /bits/ 8 <
			0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */
		spi-cal-addrlen = <1>;
		spi-cal-addr = /bits/ 32 <0x0>;
		reg = <0>;
		spi-max-frequency = <52000000>;

		partition@00000 {
			label = "BL2";
			reg = <0x00000 0x0040000>;
		};
		partition@40000 {
			label = "u-boot-env";
			reg = <0x40000 0x0010000>;
		};
		factory: partition@50000 {
			label = "Factory";
			reg = <0x50000 0x0200000>;
		};
		partition@250000 {
			label = "FIP";
			reg = <0x250000 0x0080000>;
		};
		partition@2D0000 {
			label = "firmware";
			reg = <0x2D0000 0x1D30000>;
		};
	};
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie0_pins>;
	status = "okay";
};

&pcie1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie1_pins>;
	status = "disabled";
};

&pcie2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie2_pins>;
	status = "disabled";
};

&pcie3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie3_pins>;
	status = "okay";
};

&pio {
	mdio0_pins: mdio0-pins {
		mux {
			function = "mdio";
			groups = "mdc_mdio0";
		};

		conf {
			groups = "mdc_mdio0";
			drive-strength = <MTK_DRIVE_8mA>;
		};
	};

	pcie0_pins: pcie0-pins {
		mux {
			function = "pcie";
			groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
				 "pcie_wake_n0_0";
		};
	};

	pcie1_pins: pcie1-pins {
		mux {
			function = "pcie";
			groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
				 "pcie_wake_n1_0";
		};
	};

	pcie2_pins: pcie2-pins {
		mux {
			function = "pcie";
			groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
				 "pcie_wake_n2_0";
		};
	};

	pcie3_pins: pcie3-pins {
		mux {
			function = "pcie";
			groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
				 "pcie_wake_n3_0";
		};
	};

	spic_pins: spi1-pins {
		mux {
			function = "spi";
			groups = "spi1";
		};
	};

	spi2_flash_pins: spi2-pins {
		mux {
			function = "spi";
			groups = "spi2", "spi2_wp_hold";
		};
	};
};

&watchdog {
	status = "disabled";
};

&eth {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio0_pins>;
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		mac-type = "xgdm";
		phy-mode = "10gbase-kr";

		fixed-link {
			speed = <10000>;
			full-duplex;
			pause;
		};
	};

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		mac-type = "xgdm";
		phy-mode = "usxgmii";
		phy-handle = <&phy0>;
	};

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <10500000>;

		phy0: ethernet-phy@0 {
			reg = <0>;
			compatible = "ethernet-phy-ieee802.3-c45";
			reset-gpios = <&pio 72 1>;
			reset-assert-us = <100000>;
			reset-deassert-us = <221000>;
		};

		switch@0 {
			compatible = "mediatek,mt7988";
			reg = <31>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "lan0";
					phy-mode = "gmii";
					phy-handle = <&sphy0>;
				};

				port@1 {
					reg = <1>;
					label = "lan1";
					phy-mode = "gmii";
					phy-handle = <&sphy1>;
				};

				port@2 {
					reg = <2>;
					label = "lan2";
					phy-mode = "gmii";
					phy-handle = <&sphy2>;
				};

				port@3 {
					reg = <3>;
					label = "lan3";
					phy-mode = "gmii";
					phy-handle = <&sphy3>;
				};

				port@6 {
					reg = <6>;
					label = "cpu";
					ethernet = <&gmac0>;
					phy-mode = "10gbase-kr";

					fixed-link {
						speed = <10000>;
						full-duplex;
						pause;
					};
				};
			};

			mdio {
				compatible = "mediatek,dsa-slave-mdio";
				#address-cells = <1>;
				#size-cells = <0>;

				sphy0: switch_phy0@0 {
					compatible = "ethernet-phy-id03a2.9481";
					reg = <0>;
					phy-mode = "gmii";
					rext = "efuse";
					tx_r50 = "efuse";
					nvmem-cells = <&phy_calibration_p0>;
					nvmem-cell-names = "phy-cal-data";
				};

				sphy1: switch_phy1@1 {
					compatible = "ethernet-phy-id03a2.9481";
					reg = <1>;
					phy-mode = "gmii";
					rext = "efuse";
					tx_r50 = "efuse";
					nvmem-cells = <&phy_calibration_p1>;
					nvmem-cell-names = "phy-cal-data";
				};

				sphy2: switch_phy2@2 {
					compatible = "ethernet-phy-id03a2.9481";
					reg = <2>;
					phy-mode = "gmii";
					rext = "efuse";
					tx_r50 = "efuse";
					nvmem-cells = <&phy_calibration_p2>;
					nvmem-cell-names = "phy-cal-data";
				};

				sphy3: switch_phy3@3 {
					compatible = "ethernet-phy-id03a2.9481";
					reg = <3>;
					phy-mode = "gmii";
					rext = "efuse";
					tx_r50 = "efuse";
					nvmem-cells = <&phy_calibration_p3>;
					nvmem-cell-names = "phy-cal-data";
				};
			};
		};
	};
};

&hnat {
	mtketh-wan = "eth1";
	mtketh-lan = "lan";
	mtketh-lan2 = "eth2";
	mtketh-max-gmac = <3>;
	status = "okay";
};

&wed {
	dy_txbm_enable = "true";
	dy_txbm_budge = <8>;
	txbm_init_sz = <10>;
	status = "okay";
};