tree b4ce981733f5463b4eef3cccca4f90cc9936fc4a
parent fa27733a3c6ed6194c785de56351b1ea5167fe4c
author developer <developer@mediatek.com> 1664185189 +0800
committer developer <developer@mediatek.com> 1664416924 +0800

[][[Merlin][AX3000][MT76][Performance] DBDC 5G HE160,peak throughput test , HWNAT CPU idle only 50.77%]

[Description]
Fix CPU idle only 50.77% issue when binding

DL: MT76 handle txfree notify interrupt
    when all token are belongs to wed
UL: Merlin Rx data interrupt bit changes
    to bit[19:18] from bit[23:22] when wed on

[Release-log]
N/A

[[Info to Customer]]
none

Change-Id: Icbfb4e0b6714e74ce2f7c501078bf37d164bda0e
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6563470
Build: srv_hbgsm110