diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
index 6cc0f9c..274f897 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
@@ -952,6 +952,7 @@
 			      "dma_ck";
 		#address-cells = <2>;
 		#size-cells = <2>;
+		mediatek,p0_speed_fixup;
 		status = "okay";
 	};
 
@@ -1026,6 +1027,8 @@
 			clocks = <&system_clk>;
 			clock-names = "ref";
 			#phy-cells = <1>;
+			mediatek,usb3-pll-ssc-delta;
+			mediatek,usb3-pll-ssc-delta1;
 			status = "okay";
 		};
 	};
diff --git a/target/linux/mediatek/patches-5.4/8000-PATCH-1-4-tphy-support-type-switch-by-pericfg.patch b/target/linux/mediatek/patches-5.4/8000-PATCH-1-4-tphy-support-type-switch-by-pericfg.patch
index 4ae4991..032ef35 100644
--- a/target/linux/mediatek/patches-5.4/8000-PATCH-1-4-tphy-support-type-switch-by-pericfg.patch
+++ b/target/linux/mediatek/patches-5.4/8000-PATCH-1-4-tphy-support-type-switch-by-pericfg.patch
@@ -1,7 +1,7 @@
-From ddeda571f3d79dcccef6541b6413cb184de40afd Mon Sep 17 00:00:00 2001
+From 34687407776d46f08926b91f118adc484c4ac231 Mon Sep 17 00:00:00 2001
 From: Zhanyong Wang <zhanyong.wang@mediatek.com>
 Date: Fri, 17 Sep 2021 15:56:53 +0800
-Subject: [PATCH] phy: phy-mtk-tphy: support type switch by pericfg
+Subject: [PATCH 1/8] phy: phy-mtk-tphy: support type switch by pericfg
 
 Add support type switch between USB3, PCIe, SATA and SGMII by
 pericfg register, this is used to take the place of efuse or
@@ -11,14 +11,14 @@
 Signed-off-by: Vinod Koul <vkoul@kernel.org>
 Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
 ---
- drivers/phy/mediatek/phy-mtk-tphy.c | 84 +++++++++++++++++++++++++++--
- 1 file changed, 81 insertions(+), 3 deletions(-)
+ drivers/phy/mediatek/phy-mtk-tphy.c | 83 ++++++++++++++++++++++++++++-
+ 1 file changed, 81 insertions(+), 2 deletions(-)
 
 diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
-index d1ecf088032b..759e1c0c370a 100644
+index cb2ed3b25068..a59fe65f69e5 100644
 --- a/drivers/phy/mediatek/phy-mtk-tphy.c
 +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -10,12 +10,12 @@
+@@ -10,6 +10,7 @@
  #include <linux/delay.h>
  #include <linux/io.h>
  #include <linux/iopoll.h>
@@ -26,15 +26,9 @@
  #include <linux/module.h>
  #include <linux/of_address.h>
  #include <linux/of_device.h>
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
--#include <linux/mfd/syscon.h>
- #include <linux/regmap.h>
- 
- /* version V1 sub-banks offset base address */
-@@ -268,6 +268,14 @@
- #define HIF_SYSCFG1			0x14
- #define HIF_SYSCFG1_PHY2_MASK		(0x3 << 20)
+@@ -263,6 +264,14 @@
+ #define RG_CDR_BIRLTD0_GEN3_MSK		GENMASK(4, 0)
+ #define RG_CDR_BIRLTD0_GEN3_VAL(x)	(0x1f & (x))
  
 +/* PHY switch between pcie/usb3/sgmii/sata */
 +#define USB_PHY_SWITCH_CTRL	0x0
@@ -47,7 +41,7 @@
  enum mtk_phy_version {
  	MTK_PHY_V1 = 1,
  	MTK_PHY_V2,
-@@ -301,7 +309,10 @@ struct mtk_phy_instance {
+@@ -296,7 +305,10 @@ struct mtk_phy_instance {
  	};
  	struct clk *ref_clk;	/* reference clock of anolog phy */
  	u32 index;
@@ -59,7 +53,7 @@
  	int eye_src;
  	int eye_vrt;
  	int eye_term;
-@@ -900,6 +911,64 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
+@@ -890,6 +902,64 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
  	}
  }
  
@@ -124,7 +118,7 @@
  static int mtk_phy_init(struct phy *phy)
  {
  	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
-@@ -932,6 +1001,9 @@ static int mtk_phy_init(struct phy *phy)
+@@ -922,6 +992,9 @@ static int mtk_phy_init(struct phy *phy)
  	case PHY_TYPE_SATA:
  		sata_phy_instance_init(tphy, instance);
  		break;
@@ -134,7 +128,7 @@
  	default:
  		dev_err(tphy->dev, "incompatible PHY type\n");
  		return -EINVAL;
-@@ -1020,7 +1092,8 @@ static struct phy *mtk_phy_xlate(struct device *dev,
+@@ -1010,7 +1083,8 @@ static struct phy *mtk_phy_xlate(struct device *dev,
  	if (!(instance->type == PHY_TYPE_USB2 ||
  	      instance->type == PHY_TYPE_USB3 ||
  	      instance->type == PHY_TYPE_PCIE ||
@@ -144,7 +138,7 @@
  		dev_err(dev, "unsupported device type: %d\n", instance->type);
  		return ERR_PTR(-EINVAL);
  	}
-@@ -1035,6 +1108,7 @@ static struct phy *mtk_phy_xlate(struct device *dev,
+@@ -1025,6 +1099,7 @@ static struct phy *mtk_phy_xlate(struct device *dev,
  	}
  
  	phy_parse_property(tphy, instance);
@@ -152,7 +146,7 @@
  
  	return instance->phy;
  }
-@@ -1183,6 +1257,10 @@ static int mtk_tphy_probe(struct platform_device *pdev)
+@@ -1163,6 +1238,10 @@ static int mtk_tphy_probe(struct platform_device *pdev)
  			retval = PTR_ERR(instance->ref_clk);
  			goto put_child;
  		}
diff --git a/target/linux/mediatek/patches-5.4/8006-phy-phy-mtk-tphy-add-support-efuse-setting.patch b/target/linux/mediatek/patches-5.4/8006-phy-phy-mtk-tphy-add-support-efuse-setting.patch
index 5cc8a65..05eb738 100644
--- a/target/linux/mediatek/patches-5.4/8006-phy-phy-mtk-tphy-add-support-efuse-setting.patch
+++ b/target/linux/mediatek/patches-5.4/8006-phy-phy-mtk-tphy-add-support-efuse-setting.patch
@@ -1,7 +1,7 @@
-From afb123e0f9992d35d0fb28ed875f2b7b7884652f Mon Sep 17 00:00:00 2001
+From a2eaa93a5887ddd20af0373244481139627d0d77 Mon Sep 17 00:00:00 2001
 From: Zhanyong Wang <zhanyong.wang@mediatek.com>
 Date: Mon, 8 Nov 2021 14:51:38 +0800
-Subject: [PATCH 3/5] phy: phy-mtk-tphy: add support efuse setting
+Subject: [PATCH 2/8] phy: phy-mtk-tphy: add support efuse setting
 
 Due to some SoCs have a bit shift issue that will drop a bit for usb3
 phy or pcie phy, fix it by adding software efuse reading and setting,
@@ -11,22 +11,22 @@
 Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
 Change-Id: Ibf88868668b3889f18c7930531981400cac732f1
 ---
- drivers/phy/mediatek/phy-mtk-tphy.c | 194 ++++++++++++++++++++++++++++
- 1 file changed, 194 insertions(+)
+ drivers/phy/mediatek/phy-mtk-tphy.c | 195 ++++++++++++++++++++++++++++
+ 1 file changed, 195 insertions(+)
 
 diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
-index cb2ed3b25068..05a1ad4ff334 100644
+index a59fe65f69e5..ce2731b2f5ff 100644
 --- a/drivers/phy/mediatek/phy-mtk-tphy.c
 +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -11,6 +11,7 @@
- #include <linux/io.h>
+@@ -12,6 +12,7 @@
  #include <linux/iopoll.h>
+ #include <linux/mfd/syscon.h>
  #include <linux/module.h>
 +#include <linux/nvmem-consumer.h>
  #include <linux/of_address.h>
  #include <linux/of_device.h>
  #include <linux/phy/phy.h>
-@@ -38,11 +39,16 @@
+@@ -39,11 +40,16 @@
  #define SSUSB_SIFSLV_V2_U3PHYD		0x200
  #define SSUSB_SIFSLV_V2_U3PHYA		0x400
  
@@ -43,7 +43,7 @@
  #define PA1_RG_VRT_SEL			GENMASK(14, 12)
  #define PA1_RG_VRT_SEL_VAL(x)	((0x7 & (x)) << 12)
  #define PA1_RG_TERM_SEL		GENMASK(10, 8)
-@@ -114,6 +120,8 @@
+@@ -115,6 +121,8 @@
  #define P3C_RG_SWRST_U3_PHYD_FORCE_EN	BIT(24)
  
  #define U3P_U3_PHYA_REG0	0x000
@@ -52,7 +52,7 @@
  #define P3A_RG_CLKDRV_OFF		GENMASK(3, 2)
  #define P3A_RG_CLKDRV_OFF_VAL(x)	((0x3 & (x)) << 2)
  
-@@ -168,6 +176,25 @@
+@@ -169,6 +177,25 @@
  #define P3D_RG_FWAKE_TH		GENMASK(21, 16)
  #define P3D_RG_FWAKE_TH_VAL(x)	((0x3f & (x)) << 16)
  
@@ -78,7 +78,7 @@
  #define U3P_U3_PHYD_CDR1		0x05c
  #define P3D_RG_CDR_BIR_LTD1		GENMASK(28, 24)
  #define P3D_RG_CDR_BIR_LTD1_VAL(x)	((0x1f & (x)) << 24)
-@@ -266,11 +293,23 @@
+@@ -275,11 +302,23 @@
  enum mtk_phy_version {
  	MTK_PHY_V1 = 1,
  	MTK_PHY_V2,
@@ -102,7 +102,7 @@
  	enum mtk_phy_version version;
  };
  
-@@ -295,6 +334,10 @@ struct mtk_phy_instance {
+@@ -304,6 +343,10 @@ struct mtk_phy_instance {
  		struct u3phy_banks u3_banks;
  	};
  	struct clk *ref_clk;	/* reference clock of anolog phy */
@@ -111,10 +111,10 @@
 +	u32 efuse_tx_imp;
 +	u32 efuse_rx_imp;
  	u32 index;
- 	u8 type;
- 	int eye_src;
-@@ -890,6 +933,138 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
- 	}
+ 	u32 type;
+ 	struct regmap *type_sw;
+@@ -960,6 +1003,139 @@ static int phy_type_set(struct mtk_phy_instance *instance)
+ 	return 0;
  }
  
 +static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instance)
@@ -249,10 +249,11 @@
 +	}
 +}
 +
++
  static int mtk_phy_init(struct phy *phy)
  {
  	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
-@@ -908,6 +1083,8 @@ static int mtk_phy_init(struct phy *phy)
+@@ -978,6 +1154,8 @@ static int mtk_phy_init(struct phy *phy)
  		return ret;
  	}
  
@@ -261,7 +262,7 @@
  	switch (instance->type) {
  	case PHY_TYPE_USB2:
  		u2_phy_instance_init(tphy, instance);
-@@ -989,6 +1166,7 @@ static struct phy *mtk_phy_xlate(struct device *dev,
+@@ -1062,6 +1240,7 @@ static struct phy *mtk_phy_xlate(struct device *dev,
  	struct mtk_phy_instance *instance = NULL;
  	struct device_node *phy_np = args->np;
  	int index;
@@ -269,7 +270,7 @@
  
  	if (args->args_count != 1) {
  		dev_err(dev, "invalid number of cells in 'phy' property\n");
-@@ -1024,6 +1202,10 @@ static struct phy *mtk_phy_xlate(struct device *dev,
+@@ -1098,6 +1277,10 @@ static struct phy *mtk_phy_xlate(struct device *dev,
  		return ERR_PTR(-EINVAL);
  	}
  
@@ -278,9 +279,9 @@
 +		return ERR_PTR(ret);
 +
  	phy_parse_property(tphy, instance);
+ 	phy_type_set(instance);
  
- 	return instance->phy;
-@@ -1045,14 +1227,26 @@ static const struct mtk_phy_pdata tphy_v1_pdata = {
+@@ -1120,14 +1303,26 @@ static const struct mtk_phy_pdata tphy_v1_pdata = {
  
  static const struct mtk_phy_pdata tphy_v2_pdata = {
  	.avoid_rx_sen_degradation = false,
diff --git a/target/linux/mediatek/patches-5.4/8007-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch b/target/linux/mediatek/patches-5.4/8007-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch
index b710695..1c6711f 100644
--- a/target/linux/mediatek/patches-5.4/8007-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch
+++ b/target/linux/mediatek/patches-5.4/8007-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch
@@ -1,7 +1,7 @@
-From 41ffe32e7ec23f592e21c508b5108899ad393059 Mon Sep 17 00:00:00 2001
+From 2abe803824f0331c42eb9853199d5f147cee3a06 Mon Sep 17 00:00:00 2001
 From: Zhanyong Wang <zhanyong.wang@mediatek.com>
 Date: Tue, 25 Jan 2022 16:50:47 +0800
-Subject: [PATCH 4/5] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support
+Subject: [PATCH 3/8] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support
 
 Add PCIe 2 lane efuse support in tphy driver.
 
@@ -12,10 +12,10 @@
  1 file changed, 140 insertions(+)
 
 diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
-index 05a1ad4..59d6ac3 100644
+index ce2731b2f5ff..b855e759b0da 100644
 --- a/drivers/phy/mediatek/phy-mtk-tphy.c
 +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -39,6 +39,15 @@
+@@ -40,6 +40,15 @@
  #define SSUSB_SIFSLV_V2_U3PHYD		0x200
  #define SSUSB_SIFSLV_V2_U3PHYA		0x400
  
@@ -31,7 +31,7 @@
  #define U3P_MISC_REG1		0x04
  #define MR1_EFUSE_AUTO_LOAD_DIS		BIT(6)
  
-@@ -294,6 +303,7 @@ enum mtk_phy_version {
+@@ -303,6 +312,7 @@ enum mtk_phy_version {
  	MTK_PHY_V1 = 1,
  	MTK_PHY_V2,
  	MTK_PHY_V3,
@@ -39,7 +39,7 @@
  };
  
  struct mtk_phy_pdata {
-@@ -338,6 +348,9 @@ struct mtk_phy_instance {
+@@ -347,6 +357,9 @@ struct mtk_phy_instance {
  	u32 efuse_intr;
  	u32 efuse_tx_imp;
  	u32 efuse_rx_imp;
@@ -47,9 +47,9 @@
 +	u32 efuse_tx_imp_ln1;
 +	u32 efuse_rx_imp_ln1;
  	u32 index;
- 	u8 type;
- 	int eye_src;
-@@ -878,6 +891,36 @@ static void phy_v2_banks_init(struct mtk_tphy *tphy,
+ 	u32 type;
+ 	struct regmap *type_sw;
+@@ -890,6 +903,36 @@ static void phy_v2_banks_init(struct mtk_tphy *tphy,
  	}
  }
  
@@ -86,7 +86,7 @@
  static void phy_parse_property(struct mtk_tphy *tphy,
  				struct mtk_phy_instance *instance)
  {
-@@ -1002,6 +1045,40 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
+@@ -1072,6 +1115,40 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
  		dev_info(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",
  			 instance->efuse_intr, instance->efuse_rx_imp,
  			 instance->efuse_tx_imp);
@@ -127,7 +127,7 @@
  		break;
  	default:
  		dev_err(dev, "no sw efuse for type %d\n", instance->type);
-@@ -1035,6 +1112,31 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
+@@ -1105,6 +1182,31 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
  
  		break;
  	case PHY_TYPE_USB3:
@@ -159,7 +159,7 @@
  	case PHY_TYPE_PCIE:
  		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
  		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
-@@ -1059,6 +1161,35 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
+@@ -1129,6 +1231,35 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
  		pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n",
  			__func__, instance->efuse_tx_imp,
  			instance->efuse_rx_imp, instance->efuse_intr);
@@ -195,7 +195,7 @@
  		break;
  	default:
  		dev_warn(dev, "no sw efuse for type %d\n", instance->type);
-@@ -1197,6 +1328,8 @@ static struct phy *mtk_phy_xlate(struct device *dev,
+@@ -1272,6 +1403,8 @@ static struct phy *mtk_phy_xlate(struct device *dev,
  		phy_v1_banks_init(tphy, instance);
  	} else if (tphy->pdata->version == MTK_PHY_V2) {
  		phy_v2_banks_init(tphy, instance);
@@ -204,7 +204,7 @@
  	} else {
  		dev_err(dev, "phy version is not supported\n");
  		return ERR_PTR(-EINVAL);
-@@ -1247,12 +1380,19 @@ static const struct mtk_phy_pdata mt8195_pdata = {
+@@ -1323,12 +1456,19 @@ static const struct mtk_phy_pdata mt8195_pdata = {
  	.version = MTK_PHY_V3,
  };
  
diff --git a/target/linux/mediatek/patches-5.4/8008-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch b/target/linux/mediatek/patches-5.4/8008-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch
index 1223fb6..e84ca6c 100644
--- a/target/linux/mediatek/patches-5.4/8008-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch
+++ b/target/linux/mediatek/patches-5.4/8008-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch
@@ -1,7 +1,7 @@
-From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001
+From 355e7f114a47819c3c6545a97ad308d627da5d1a Mon Sep 17 00:00:00 2001
 From: Zhanyong Wang <zhanyong.wang@mediatek.com>
 Date: Tue, 25 Jan 2022 19:03:34 +0800
-Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism
+Subject: [PATCH 4/8] phy: phy-mtk-tphy: add auto-load-valid check mechanism
  support
 
 add auto-load-valid check mechanism support
@@ -12,10 +12,10 @@
  1 file changed, 64 insertions(+), 3 deletions(-)
 
 diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
-index 59d6ac3..4adc505 100644
+index b855e759b0da..a5b17a1aed5c 100644
 --- a/drivers/phy/mediatek/phy-mtk-tphy.c
 +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -345,9 +345,13 @@ struct mtk_phy_instance {
+@@ -354,9 +354,13 @@ struct mtk_phy_instance {
  	};
  	struct clk *ref_clk;	/* reference clock of anolog phy */
  	u32 efuse_sw_en;
@@ -29,7 +29,7 @@
  	u32 efuse_intr_ln1;
  	u32 efuse_tx_imp_ln1;
  	u32 efuse_rx_imp_ln1;
-@@ -980,6 +984,7 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
+@@ -1050,6 +1054,7 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
  {
  	struct device *dev = &instance->phy->dev;
  	int ret = 0;
@@ -37,7 +37,7 @@
  
  	dev_err(dev, "try to get sw efuse\n");
  
-@@ -998,6 +1003,20 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
+@@ -1068,6 +1073,20 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
  
  	switch (instance->type) {
  	case PHY_TYPE_USB2:
@@ -58,7 +58,7 @@
  		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
  		if (ret) {
  			dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
-@@ -1015,6 +1034,20 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
+@@ -1085,6 +1104,20 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
  		break;
  	case PHY_TYPE_USB3:
  	case PHY_TYPE_PCIE:
@@ -79,7 +79,7 @@
  		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
  		if (ret) {
  			dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
-@@ -1049,6 +1082,20 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
+@@ -1119,6 +1152,20 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc
  		if (tphy->pdata->version != MTK_PHY_V4)
  			break;
  
@@ -100,7 +100,7 @@
  		ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
  		if (ret) {
  			dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
-@@ -1100,6 +1147,10 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
+@@ -1170,6 +1217,10 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
  
  	switch (instance->type) {
  	case PHY_TYPE_USB2:
@@ -111,7 +111,7 @@
  		tmp = readl(u2_banks->misc + U3P_MISC_REG1);
  		tmp |= MR1_EFUSE_AUTO_LOAD_DIS;
  		writel(tmp, u2_banks->misc + U3P_MISC_REG1);
-@@ -1112,6 +1163,10 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
+@@ -1182,6 +1233,10 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
  
  		break;
  	case PHY_TYPE_USB3:
@@ -122,7 +122,7 @@
  		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
  		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
  		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-@@ -1138,6 +1193,10 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
+@@ -1208,6 +1263,10 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
  
  		break;
  	case PHY_TYPE_PCIE:
@@ -133,7 +133,7 @@
  		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
  		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
  		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-@@ -1162,9 +1221,11 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
+@@ -1232,9 +1291,11 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
  			__func__, instance->efuse_tx_imp,
  			instance->efuse_rx_imp, instance->efuse_intr);
  
diff --git a/target/linux/mediatek/patches-5.4/8009-tphy-one-setting-of-TTSSC-Freq-Dev-for-all-IC-cases.patch b/target/linux/mediatek/patches-5.4/8009-tphy-one-setting-of-TTSSC-Freq-Dev-for-all-IC-cases.patch
new file mode 100644
index 0000000..5bf48b2
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/8009-tphy-one-setting-of-TTSSC-Freq-Dev-for-all-IC-cases.patch
@@ -0,0 +1,51 @@
+From 917388b73b89f2859d795d800a296151d77e6ece Mon Sep 17 00:00:00 2001
+From: Zhanyong Wang <zhanyong.wang@mediatek.com>
+Date: Sat, 15 Oct 2022 17:38:54 +0800
+Subject: [PATCH 5/8] tphy: one setting of TTSSC-Freq-Dev for all IC cases
+
+try to use one setting of TTSSC-Freq-Dev to covery all IC cases
+
+Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
+---
+ drivers/phy/mediatek/phy-mtk-tphy.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
+index a5b17a1aed5c..a38c50f4529f 100644
+--- a/drivers/phy/mediatek/phy-mtk-tphy.c
++++ b/drivers/phy/mediatek/phy-mtk-tphy.c
+@@ -219,6 +219,14 @@
+ #define P3D_RG_RXDET_STB2_SET_P3	GENMASK(8, 0)
+ #define P3D_RG_RXDET_STB2_SET_P3_VAL(x)	(0x1ff & (x))
+ 
++#define U3P_U3_PHYD_REG19		0x338
++#define P3D_RG_PLL_SSC_DELTA1           GENMASK(15, 0)
++#define P3D_RG_PLL_SSC_DELTA1_VAL(x)	(0xffff & (x))
++
++#define U3P_U3_PHYD_REG21		0x340
++#define P3D_RG_PLL_SSC_DELTA            GENMASK(31, 16)
++#define P3D_RG_PLL_SSC_DELTA_VAL(x)	((0xffff & (x)) << 16)
++
+ #define U3P_SPLLC_XTALCTL3		0x018
+ #define XC3_RG_U3_XTAL_RX_PWD		BIT(9)
+ #define XC3_RG_U3_FRC_XTAL_RX_PWD	BIT(8)
+@@ -514,6 +522,16 @@ static void u3_phy_instance_init(struct mtk_tphy *tphy,
+ 	tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
+ 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
+ 
++	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_REG19);
++	tmp &= ~P3D_RG_PLL_SSC_DELTA1;
++	tmp |= P3D_RG_PLL_SSC_DELTA1_VAL(0x1c3);
++	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_REG19);
++
++	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_REG21);
++	tmp &= ~P3D_RG_PLL_SSC_DELTA;
++	tmp |= P3D_RG_PLL_SSC_DELTA_VAL(0x1c3);
++	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_REG21);
++
+ 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
+ }
+ 
+-- 
+2.18.0
+
diff --git a/target/linux/mediatek/patches-5.4/9000-PATCH-1-1-xHCI-change-compliance-mode-de-emphasis-default-as-g.patch b/target/linux/mediatek/patches-5.4/9000-PATCH-1-1-xHCI-change-compliance-mode-de-emphasis-default-as-g.patch
index e82e1bc..9d1ca10 100644
--- a/target/linux/mediatek/patches-5.4/9000-PATCH-1-1-xHCI-change-compliance-mode-de-emphasis-default-as-g.patch
+++ b/target/linux/mediatek/patches-5.4/9000-PATCH-1-1-xHCI-change-compliance-mode-de-emphasis-default-as-g.patch
@@ -1,24 +1,26 @@
-From 5f8c12ffa661e3707790f59827a45ff4102f2886 Mon Sep 17 00:00:00 2001
-From: Zhanyong Wang <zhanyong.wang@mediatek.com>
-Date: Mon, 15 Aug 2022 14:13:50 +0800
-Subject: [PATCH] xHCI: change compliance mode de-emphasis default as gen1
+From 0df9413c8ff0df4ed69b6e1577d7cd5fd2d72e5e Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Tue, 25 Oct 2022 18:25:25 +0800
+Subject: [PATCH 1/3] xHCI: change compliance mode de-emphasis default as gen1
 
 Port0 is using Gen2 Phy for 10GHz, and Port0 is running
 on 5GHz actually. hence to change compliance mode de-
 emphasis default as Gen1.
 
 Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
 ---
- drivers/usb/host/xhci-mtk.c | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
+ drivers/usb/host/xhci-mtk.c | 18 +++++++++++++++++-
+ drivers/usb/host/xhci-mtk.h |  1 +
+ 2 files changed, 18 insertions(+), 1 deletion(-)
 
 diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
-index 2a4b73a658f9..b1201fb65fd6 100644
+index 5c0eb35cd007..77ddb8c05500 100644
 --- a/drivers/usb/host/xhci-mtk.c
 +++ b/drivers/usb/host/xhci-mtk.c
-@@ -24,6 +24,11 @@
+@@ -22,6 +22,11 @@
+ #include "xhci.h"
  #include "xhci-mtk.h"
- #include "xhci-mtk-test.h"
  
 +/* COMPLIANCE_CP5_CP7_TXDEEMPH_10G register */
 +#define COMPLIANCE_CP5_CP7_TXDEEMPH_10G  0x2428
@@ -28,7 +30,7 @@
  /* ip_pw_ctrl0 register */
  #define CTRL0_IP_SW_RST	BIT(0)
  
-@@ -415,6 +420,7 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
+@@ -413,6 +418,7 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
  {
  	struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
  	int ret;
@@ -36,12 +38,12 @@
  
  	if (usb_hcd_is_primary_hcd(hcd)) {
  		ret = xhci_mtk_ssusb_config(mtk);
-@@ -432,6 +438,15 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
+@@ -430,6 +436,15 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
  			return ret;
  	}
  
 +	/* change COMPLIANCE_CP5_CP7_TXDEEMPH_10G  as Gen1 instead Gen2 */
-+	if (hcd->rsrc_start == 0x11190000ULL) {
++	if (mtk->p0_speed_fixup) {
 +		val  = readl(mtk->hcd->regs + COMPLIANCE_CP5_CP7_TXDEEMPH_10G);
 +		val &= ~CP5_CP7_TXDEEMPH_10G;
 +		val |= 0x00001;
@@ -52,6 +54,28 @@
  	return ret;
  }
  
+@@ -475,7 +490,8 @@ static int xhci_mtk_probe(struct platform_device *pdev)
+ 	/* optional property, ignore the error if it does not exist */
+ 	of_property_read_u32(node, "mediatek,u3p-dis-msk",
+ 			     &mtk->u3p_dis_msk);
+-
++	mtk->p0_speed_fixup = of_property_read_bool(node,
++						    "mediatek,p0_speed_fixup");
+ 	ret = usb_wakeup_of_property_parse(mtk, node);
+ 	if (ret) {
+ 		dev_err(dev, "failed to parse uwk property\n");
+diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
+index 2f702342de66..8a884e7b481b 100644
+--- a/drivers/usb/host/xhci-mtk.h
++++ b/drivers/usb/host/xhci-mtk.h
+@@ -156,6 +156,7 @@ struct xhci_hcd_mtk {
+ 	struct regmap *uwk;
+ 	u32 uwk_reg_base;
+ 	u32 uwk_vers;
++	bool p0_speed_fixup;
+ };
+ 
+ static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
 -- 
 2.18.0
 
diff --git a/target/linux/mediatek/patches-5.4/9001-PATCH-1-2-xHCI-MT7986-USB-2.0-USBIF-compliance-toolkit.patch b/target/linux/mediatek/patches-5.4/9001-PATCH-1-2-xHCI-MT7986-USB-2.0-USBIF-compliance-toolkit.patch
index 0b3bf3c..07b87fc 100644
--- a/target/linux/mediatek/patches-5.4/9001-PATCH-1-2-xHCI-MT7986-USB-2.0-USBIF-compliance-toolkit.patch
+++ b/target/linux/mediatek/patches-5.4/9001-PATCH-1-2-xHCI-MT7986-USB-2.0-USBIF-compliance-toolkit.patch
@@ -1,4 +1,4 @@
-From 4d19c233a01598a28fdc528ebaeb7a1b4bb6884f Mon Sep 17 00:00:00 2001
+From 083b79c977495cafc70c5d044db1f3f6c0587b1c Mon Sep 17 00:00:00 2001
 From: Zhanyong Wang <zhanyong.wang@mediatek.com>
 Date: Mon, 15 Aug 2022 12:40:22 +0800
 Subject: [PATCH 2/3] xHCI: MT79xx USB 2.0 USBIF compliance toolkit
@@ -9,11 +9,11 @@
 ---
  drivers/usb/host/Kconfig    |  9 +++++++++
  drivers/usb/host/Makefile   | 10 ++++++++++
- drivers/usb/host/xhci-mtk.c |  5 ++++-
+ drivers/usb/host/xhci-mtk.c |  6 ++++--
  drivers/usb/host/xhci-mtk.h |  7 +++++++
  drivers/usb/host/xhci.c     |  2 +-
  drivers/usb/host/xhci.h     |  1 +
- 6 files changed, 32 insertions(+), 2 deletions(-)
+ 6 files changed, 32 insertions(+), 3 deletions(-)
 
 diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
 index 79b2e79dddd0..12b1bf9aa043 100644
@@ -57,10 +57,10 @@
  
  xhci-plat-hcd-y := xhci-plat.o
 diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
-index 104296fdd03e..d4345657945d 100644
+index 77ddb8c05500..7a200793169b 100644
 --- a/drivers/usb/host/xhci-mtk.c
 +++ b/drivers/usb/host/xhci-mtk.c
-@@ -19,9 +19,10 @@
+@@ -18,10 +18,10 @@
  #include <linux/pm_runtime.h>
  #include <linux/regmap.h>
  #include <linux/regulator/consumer.h>
@@ -68,11 +68,12 @@
 +#include <linux/usb/of.h>
  #include "xhci.h"
  #include "xhci-mtk.h"
+-
 +#include "xhci-mtk-test.h"
- 
- /* ip_pw_ctrl0 register */
- #define CTRL0_IP_SW_RST	BIT(0)
-@@ -581,6 +582,7 @@ static int xhci_mtk_probe(struct platform_device *pdev)
+ /* COMPLIANCE_CP5_CP7_TXDEEMPH_10G register */
+ #define COMPLIANCE_CP5_CP7_TXDEEMPH_10G  0x2428
+ #define CP5_CP7_TXDEEMPH_10G		 GENMASK(17, 0)
+@@ -586,6 +586,7 @@ static int xhci_mtk_probe(struct platform_device *pdev)
  	ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
  	if (ret)
  		goto dealloc_usb2_hcd;
@@ -80,7 +81,7 @@
  
  	return 0;
  
-@@ -615,6 +617,7 @@ static int xhci_mtk_remove(struct platform_device *dev)
+@@ -620,6 +621,7 @@ static int xhci_mtk_remove(struct platform_device *dev)
  	struct usb_hcd	*hcd = mtk->hcd;
  	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
  	struct usb_hcd  *shared_hcd = xhci->shared_hcd;
@@ -89,13 +90,13 @@
  	pm_runtime_put_noidle(&dev->dev);
  	pm_runtime_disable(&dev->dev);
 diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
-index 985e7a19f6f6..1540c66799d7 100644
+index 8a884e7b481b..e815d7091acc 100644
 --- a/drivers/usb/host/xhci-mtk.h
 +++ b/drivers/usb/host/xhci-mtk.h
-@@ -158,6 +158,13 @@ struct xhci_hcd_mtk {
- 	struct regmap *uwk;
+@@ -157,6 +157,13 @@ struct xhci_hcd_mtk {
  	u32 uwk_reg_base;
  	u32 uwk_vers;
+ 	bool p0_speed_fixup;
 +
 +#ifdef CONFIG_USB_XHCI_MTK_DEBUGFS
 +	int     test_mode;
@@ -107,10 +108,10 @@
  
  static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
 diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
-index 9fe35bb67731..4f62eddce6ab 100644
+index 5ce16a259e61..b6f8383f7371 100644
 --- a/drivers/usb/host/xhci.c
 +++ b/drivers/usb/host/xhci.c
-@@ -711,7 +711,7 @@ EXPORT_SYMBOL_GPL(xhci_run);
+@@ -713,7 +713,7 @@ EXPORT_SYMBOL_GPL(xhci_run);
   * Disable device contexts, disable IRQs, and quiesce the HC.
   * Reset the HC, finish any completed transactions, and cleanup memory.
   */
@@ -120,7 +121,7 @@
  	u32 temp;
  	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
-index a9031f494984..b54be4833ef7 100644
+index 0dc448630197..80b3124c43e2 100644
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
 @@ -2070,6 +2070,7 @@ int xhci_halt(struct xhci_hcd *xhci);