[][tphy][patch][fix patch conflict]
[Description]
Fix elder patch conflict in kernel-5.4.219
[Release-log]
N/A
Change-Id: I47642c61643fc9187fa8eb1d0a7afd17d3eb50df
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6690949
diff --git a/target/linux/mediatek/patches-5.4/9000-PATCH-1-1-xHCI-change-compliance-mode-de-emphasis-default-as-g.patch b/target/linux/mediatek/patches-5.4/9000-PATCH-1-1-xHCI-change-compliance-mode-de-emphasis-default-as-g.patch
index e82e1bc..9d1ca10 100644
--- a/target/linux/mediatek/patches-5.4/9000-PATCH-1-1-xHCI-change-compliance-mode-de-emphasis-default-as-g.patch
+++ b/target/linux/mediatek/patches-5.4/9000-PATCH-1-1-xHCI-change-compliance-mode-de-emphasis-default-as-g.patch
@@ -1,24 +1,26 @@
-From 5f8c12ffa661e3707790f59827a45ff4102f2886 Mon Sep 17 00:00:00 2001
-From: Zhanyong Wang <zhanyong.wang@mediatek.com>
-Date: Mon, 15 Aug 2022 14:13:50 +0800
-Subject: [PATCH] xHCI: change compliance mode de-emphasis default as gen1
+From 0df9413c8ff0df4ed69b6e1577d7cd5fd2d72e5e Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Tue, 25 Oct 2022 18:25:25 +0800
+Subject: [PATCH 1/3] xHCI: change compliance mode de-emphasis default as gen1
Port0 is using Gen2 Phy for 10GHz, and Port0 is running
on 5GHz actually. hence to change compliance mode de-
emphasis default as Gen1.
Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
---
- drivers/usb/host/xhci-mtk.c | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
+ drivers/usb/host/xhci-mtk.c | 18 +++++++++++++++++-
+ drivers/usb/host/xhci-mtk.h | 1 +
+ 2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
-index 2a4b73a658f9..b1201fb65fd6 100644
+index 5c0eb35cd007..77ddb8c05500 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
-@@ -24,6 +24,11 @@
+@@ -22,6 +22,11 @@
+ #include "xhci.h"
#include "xhci-mtk.h"
- #include "xhci-mtk-test.h"
+/* COMPLIANCE_CP5_CP7_TXDEEMPH_10G register */
+#define COMPLIANCE_CP5_CP7_TXDEEMPH_10G 0x2428
@@ -28,7 +30,7 @@
/* ip_pw_ctrl0 register */
#define CTRL0_IP_SW_RST BIT(0)
-@@ -415,6 +420,7 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
+@@ -413,6 +418,7 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
{
struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
int ret;
@@ -36,12 +38,12 @@
if (usb_hcd_is_primary_hcd(hcd)) {
ret = xhci_mtk_ssusb_config(mtk);
-@@ -432,6 +438,15 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
+@@ -430,6 +436,15 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
return ret;
}
+ /* change COMPLIANCE_CP5_CP7_TXDEEMPH_10G as Gen1 instead Gen2 */
-+ if (hcd->rsrc_start == 0x11190000ULL) {
++ if (mtk->p0_speed_fixup) {
+ val = readl(mtk->hcd->regs + COMPLIANCE_CP5_CP7_TXDEEMPH_10G);
+ val &= ~CP5_CP7_TXDEEMPH_10G;
+ val |= 0x00001;
@@ -52,6 +54,28 @@
return ret;
}
+@@ -475,7 +490,8 @@ static int xhci_mtk_probe(struct platform_device *pdev)
+ /* optional property, ignore the error if it does not exist */
+ of_property_read_u32(node, "mediatek,u3p-dis-msk",
+ &mtk->u3p_dis_msk);
+-
++ mtk->p0_speed_fixup = of_property_read_bool(node,
++ "mediatek,p0_speed_fixup");
+ ret = usb_wakeup_of_property_parse(mtk, node);
+ if (ret) {
+ dev_err(dev, "failed to parse uwk property\n");
+diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
+index 2f702342de66..8a884e7b481b 100644
+--- a/drivers/usb/host/xhci-mtk.h
++++ b/drivers/usb/host/xhci-mtk.h
+@@ -156,6 +156,7 @@ struct xhci_hcd_mtk {
+ struct regmap *uwk;
+ u32 uwk_reg_base;
+ u32 uwk_vers;
++ bool p0_speed_fixup;
+ };
+
+ static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
--
2.18.0