diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index bd33947..63c7bb8 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -173,30 +173,6 @@
 		#clock-cells = <0>;
 	};
 
-	spi0_clk: dummy_spi0_clk {
-		compatible = "fixed-clock";
-		clock-frequency = <208000000>;
-		#clock-cells = <0>;
-	};
-
-	spi1_clk: dummy_spi1_clk {
-		compatible = "fixed-clock";
-		clock-frequency = <40000000>;
-		#clock-cells = <0>;
-	};
-
-	uart_clk: dummy_uart_clk {
-		compatible = "fixed-clock";
-		clock-frequency = <40000000>;
-		#clock-cells = <0>;
-	};
-
-	gpt_clk: dummy_gpt_clk {
-		compatible = "fixed-clock";
-		clock-frequency = <13000000>;
-		#clock-cells = <0>;
-	};
-
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;
@@ -205,18 +181,17 @@
 			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-
 	};
 
 	infracfg_ao: infracfg_ao@10001000 {
 		compatible = "mediatek,mt7986-infracfg_ao", "syscon";
-		reg = <0 0x10001000 0 0x30>;
+		reg = <0 0x10001000 0 0x68>;
 		#clock-cells = <1>;
 	};
 
 	infracfg: infracfg@10001040 {
 		compatible = "mediatek,mt7986-infracfg", "syscon";
-		reg = <0 0x10001040 0 0x1000>;
+		reg = <0 0x1000106c 0 0x1000>;
 		#clock-cells = <1>;
 	};
 
@@ -251,12 +226,38 @@
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	pwm: pwm@10048000 {
+		compatible = "mediatek,mt7986-pwm";
+		reg = <0 0x10048000 0 0x1000>;
+		#clock-cells = <1>;
+		#pwm-cells = <2>;
+		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg CK_INFRA_PWM>,
+			 <&infracfg_ao CK_INFRA_PWM_BSEL>,
+			 <&infracfg_ao CK_INFRA_PWM1_CK>,
+			 <&infracfg_ao CK_INFRA_PWM2_CK>;
+		assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
+				  <&infracfg_ao CK_INFRA_PWM_BSEL>,
+				  <&infracfg_ao CK_INFRA_PWM1_SEL>,
+				  <&infracfg_ao CK_INFRA_PWM2_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>,
+					 <&infracfg CK_INFRA_PWM>,
+					 <&infracfg CK_INFRA_PWM>,
+					 <&infracfg CK_INFRA_PWM>;
+		clock-names = "top", "main", "pwm1", "pwm2";
+		status = "disabled";
+	};
+
 	uart0: serial@11002000 {
 		compatible = "mediatek,mt7986-uart",
 			     "mediatek,mt6577-uart";
 		reg = <0 0x11002000 0 0x400>;
 		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&uart_clk>;
+		clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+				  <&infracfg_ao CK_INFRA_UART0_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+					 <&infracfg CK_INFRA_UART>;
 		status = "disabled";
 	};
 
@@ -265,7 +266,9 @@
 			     "mediatek,mt6577-uart";
 		reg = <0 0x11003000 0 0x400>;
 		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&uart_clk>;
+		clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
+		assigned-clocks = <&infracfg_ao CK_INFRA_UART1_SEL>;
+		assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
 		status = "disabled";
 	};
 
@@ -274,10 +277,26 @@
 			     "mediatek,mt6577-uart";
 		reg = <0 0x11004000 0 0x400>;
 		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&uart_clk>;
+		clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
+		assigned-clocks = <&infracfg_ao CK_INFRA_UART2_SEL>;
+		assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
 		status = "disabled";
 	};
 
+        i2c0: i2c@11008000 {
+                compatible = "mediatek,mt7986-i2c";
+                reg = <0 0x11008000 0 0x90>,
+                      <0 0x10217080 0 0x80>;
+                interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+                clock-div = <16>;
+                clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
+                         <&infracfg_ao CK_INFRA_AP_DMA_CK>;
+                clock-names = "main", "dma";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
 	pcie: pcie@11280000 {
 		compatible = "mediatek,mt7986-pcie";
 		device_type = "pci";
@@ -345,7 +364,7 @@
 	ethsys: syscon@15000000 {
                 #address-cells = <1>;
                 #size-cells = <1>;
-                compatible = "mediatek,mt7986-ethsys",
+                compatible = "mediatek,mt7986-ethsys_ck",
                              "syscon";
                 reg = <0 0x15000000 0 0x1000>;
                 #clock-cells = <1>;
@@ -365,24 +384,28 @@
                              <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&system_clk>,
-                         <&system_clk>,
-                         <&system_clk>,
-                         <&system_clk>,
-                         <&system_clk>,
-                         <&system_clk>,
-                         <&system_clk>,
-                         <&system_clk>,
-                         <&system_clk>,
-                         <&system_clk>,
-                         <&system_clk>,
-                         <&system_clk>,
-                         <&system_clk>;
+                clocks = <&ethsys CK_ETH_FE_EN>,
+                         <&ethsys CK_ETH_GP2_EN>,
+                         <&ethsys CK_ETH_GP1_EN>,
+                         <&ethsys CK_ETH_WOCPU1_EN>,
+                         <&ethsys CK_ETH_WOCPU0_EN>,
+                         <&ethsys CK_SGM0_TX_EN>,
+                         <&ethsys CK_SGM0_RX_EN>,
+                         <&ethsys CK_SGM0_CK0_EN>,
+                         <&ethsys CK_SGM0_CDR_CK0_EN>,
+                         <&ethsys CK_SGM1_TX_EN>,
+                         <&ethsys CK_SGM1_RX_EN>,
+                         <&ethsys CK_SGM1_CK1_EN>,
+                         <&ethsys CK_SGM1_CDR_CK1_EN>;
                 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
                          "sgmii_tx250m", "sgmii_rx250m",
                          "sgmii_cdr_ref", "sgmii_cdr_fb",
                          "sgmii2_tx250m", "sgmii2_rx250m",
                          "sgmii2_cdr_ref", "sgmii2_cdr_fb";
+		assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>,
+				  <&topckgen CK_TOP_SGM_325M_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>,
+					 <&topckgen CK_TOP_CB_SGM_325M>;
                 mediatek,ethsys = <&ethsys>;
 		mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
                 #reset-cells = <1>;
@@ -420,10 +443,14 @@
 		reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
 		reg-names = "nfi", "ecc";
 		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&system_clk>,
-			 <&system_clk>,
-			 <&system_clk>;
+		clocks = <&topckgen CK_TOP_SPINFI_SEL>,
+			 <&infracfg_ao CK_INFRA_SPINFI1_CK>,
+			 <&topckgen CK_TOP_NFI1X_SEL>;
 		clock-names = "nfi_clk", "pad_clk", "ecc_clk";
+		assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
+			 	  <&topckgen CK_TOP_NFI1X_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M_D2>,
+					 <&topckgen CK_TOP_CB_CKSQ_40M>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
@@ -448,9 +475,9 @@
 		compatible = "mediatek,ipm-spi";
 		reg = <0 0x1100a000 0 0x100>;
 		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&spi0_clk>,
-			 <&spi0_clk>,
-			 <&spi0_clk>;
+		clocks = <&topckgen CK_TOP_CB_M_D2>,
+			 <&infracfg_ao CK_INFRA_SPI0_CK>,
+			 <&topckgen CK_TOP_SPI_SEL>;
 		clock-names = "parent-clk", "sel-clk", "spi-clk";
 		status = "disabled";
 	};
@@ -459,9 +486,9 @@
 		compatible = "mediatek,ipm-spi";
 		reg = <0 0x1100b000 0 0x100>;
 		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&spi1_clk>,
-			 <&spi1_clk>,
-			 <&spi1_clk>;
+		clocks = <&topckgen CK_TOP_CB_M_D2>,
+			 <&infracfg_ao CK_INFRA_SPI1_CK>,
+			 <&topckgen CK_TOP_SPIM_MST_SEL>;
 		clock-names = "parent-clk", "sel-clk", "spi-clk";
 		status = "disabled";
 	};
@@ -471,10 +498,14 @@
 		reg = <0 0x11230000 0 0x1000>,
 			<0 0x11c20000 0 0x1000>;
 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&uart_clk>,
-			<&uart_clk>,
-			<&uart_clk>;
+		clocks = <&topckgen CK_TOP_EMMC_416M>,
+			<&topckgen CK_TOP_EMMC_250M>,
+			<&infracfg_ao CK_INFRA_MSDC_CK>;
 		clock-names = "source", "hclk", "source_cg";
+		assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
+				  <&topckgen CK_TOP_EMMC_250M_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+					 <&topckgen CK_TOP_CB_CKSQ_40M>;
 		status = "disabled";
 	};
 
@@ -482,9 +513,10 @@
 		compatible = "mediatek,mt7986-auxadc",
 			     "mediatek,mt7622-auxadc";
 		reg = <0 0x1100d000 0 0x1000>;
-		clocks = <&system_clk>;
+		clocks = <&infracfg_ao CK_INFRA_ADC_26M_CK>;
 		clock-names = "main";
 		#io-channel-cells = <1>;
+		status = "disabled";
 	};
 
 	consys: consys@10000000 {
@@ -556,4 +588,4 @@
 	};
 };
 
-#include "mt7986-clkitg.dtsi"
\ No newline at end of file
+#include "mt7986-clkitg.dtsi"