[][Add clock and pinctrl setting and i2c pwm to mt7986 DT]
[Description]
Add more pinctrl pinmux list into DT
Modify DT according to releated clock driver
Add i2c and pwm in DT
Change since v1:
Add mt7986 compatiable string to i2c and pwm driver
Enable i2c in mt7986 kernel config
Fix pwm reg info in DT
Add memory node back to prevent hang when u-boot can't carry memery size info.
Change since v2:
fix pwm clock and it's pinctrl node
Change since v3:
Add ethernet clock parent
Change since v4:
Fix ethernet clock parent
Change since v5:
Fix auxadc and ethernet (ethsys)
[Release-log]
Build Pass
Boot-up from spim-nand flash pass
Update since v1:
I2C test pass with i2cdetect command
Update since v2:
PWM test pass with blinking led
Update since V5:
Ethernet test pass with ping
auxadc test pass with cat sysfs
INFRACFG driver in pwm2_ck_sel, and pwm1_ck_sel have bug,
We got 32k instead of csw_pwm_ck, need clock owner to fix this.
--> Fix by change 4619106
Change-Id: Icac52cae356796fec6b9e3652747e14fed9cf4e0
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/4610073
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
index b0c5254..c153e79 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
@@ -9,7 +9,6 @@
};
memory {
- // fpga ddr2: 128MB*2
reg = <0 0x40000000 0 0x10000000>;
};
@@ -74,10 +73,38 @@
};
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_pins>;
+ status = "okay";
+};
+
+&auxadc {
+ status = "okay";
+};
+
&watchdog {
status = "okay";
};
@@ -266,7 +293,6 @@
&snand {
pinctrl-names = "default";
- /* pin shared with spic */
pinctrl-0 = <&snfi_pins>;
status = "okay";
mediatek,quad-spi;
@@ -280,8 +306,7 @@
&spi1 {
pinctrl-names = "default";
- /* pin shared with snfi */
- pinctrl-0 = <&spic_pins>;
+ pinctrl-0 = <&spic_pins_g2>;
status = "okay";
};
@@ -300,38 +325,164 @@
};
&pio {
- spi_flash_pins: spi0-pins {
+ wifi_led_pins: wifi_led-pins-1-2 {
mux {
- function = "flash";
- groups = "spi0", "spi0_wp_hold";
+ function = "led";
+ groups = "wifi_led";
+ };
+ };
+
+ i2c_pins: i2c-pins-3-4 {
+ mux {
+ function = "i2c";
+ groups = "i2c";
+ };
+ };
+
+ uart1_pins_g0: uart1-pins-7-to-10 {
+ mux {
+ function = "uart";
+ groups = "uart1_0";
+ };
+ };
+
+ jtag_pins: jtag-pins-11-to-14 {
+ mux {
+ function = "jtag";
+ groups = "jtag";
+ };
+ };
+
+ spic_pins_g0: spic-pins-11-to-14 {
+ mux {
+ function = "spi";
+ groups = "spi1_0";
+ };
+ };
+
+ pwm1_pin_g0: pwm1-pin-20 {
+ mux {
+ function = "pwm";
+ groups = "pwm1_1";
+ };
+ };
+
+ pwm0_pin: pwm0-pin-21 {
+ mux {
+ function = "pwm";
+ groups = "pwm0";
+ };
+ };
+
+ pwm1_pin_g1: pwm1-pin-22 {
+ mux {
+ function = "pwm";
+ groups = "pwm1_0";
+ };
+ };
+
+ spic_pins_g1: spic-pins-23-to-26 {
+ mux {
+ function = "spi";
+ groups = "spi1_1";
+ };
+ };
+
+ uart1_pins_g1: uart1-pins-23-to-26 {
+ mux {
+ function = "uart";
+ groups = "uart1_1";
};
};
- snfi_pins: snfi-pins {
+ snfi_pins: snfi-pins-23-to-28 {
mux {
function = "flash";
groups = "snfi";
};
};
- spic_pins: spi1-pins {
+ spic_pins_g2: spic-pins-29-to-32 {
mux {
function = "spi";
groups = "spi1_2";
};
};
+ uart1_pins_g2: uart1-pins-29-to-32 {
+ mux {
+ function = "uart";
+ groups = "uart1_2";
+ };
+ };
+
- mmc0_pins_default: mmc0-pins-default {
+ uart2_pins_g0: uart1-pins-29-to-32 {
+ mux {
+ function = "uart";
+ groups = "uart1_2";
+ };
+ };
+
+ uart2_pins_g1: uart1-pins-23-to-36 {
+ mux {
+ function = "uart";
+ groups = "uart2_1";
+ };
+ };
+
+ spic_pins_g3: spic-pins-33-to-36 {
+ mux {
+ function = "spi";
+ groups = "spi1_3";
+ };
+ };
+
+ uart1_pins_g3: uart1-pins-35-to-38 {
+ mux {
+ function = "uart";
+ groups = "uart1_3_rx_tx", "uart1_3_cts_rts";
+ };
+ };
+
+ spi_flash_pins: spi-flash-pins-33-to-38 {
mux {
function = "flash";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ uart1_pins: uart1-pins-42-to-45 {
+ mux {
+ function = "uart";
+ groups = "uart1";
+ };
+ };
+
+ uart2_pins: uart1-pins-46-to-49 {
+ mux {
+ function = "uart";
+ groups = "uart2";
+ };
+ };
+
+ mmc0_pins_default: mmc0-pins-50-to-61-default {
+ mux {
+ function = "flash";
groups = "emmc_51";
};
};
- mmc0_pins_uhs: mmc0-pins-uhs {
+ mmc0_pins_uhs: mmc0-pins-50-to-61-uhs {
mux {
function = "flash";
groups = "emmc_51";
};
};
+
+ pcm_pins: pcm-pins-62-to-65 {
+ mux {
+ function = "pcm";
+ groups = "pcm";
+ };
+ };
};
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index bd33947..63c7bb8 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -173,30 +173,6 @@
#clock-cells = <0>;
};
- spi0_clk: dummy_spi0_clk {
- compatible = "fixed-clock";
- clock-frequency = <208000000>;
- #clock-cells = <0>;
- };
-
- spi1_clk: dummy_spi1_clk {
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- #clock-cells = <0>;
- };
-
- uart_clk: dummy_uart_clk {
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- #clock-cells = <0>;
- };
-
- gpt_clk: dummy_gpt_clk {
- compatible = "fixed-clock";
- clock-frequency = <13000000>;
- #clock-cells = <0>;
- };
-
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
@@ -205,18 +181,17 @@
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-
};
infracfg_ao: infracfg_ao@10001000 {
compatible = "mediatek,mt7986-infracfg_ao", "syscon";
- reg = <0 0x10001000 0 0x30>;
+ reg = <0 0x10001000 0 0x68>;
#clock-cells = <1>;
};
infracfg: infracfg@10001040 {
compatible = "mediatek,mt7986-infracfg", "syscon";
- reg = <0 0x10001040 0 0x1000>;
+ reg = <0 0x1000106c 0 0x1000>;
#clock-cells = <1>;
};
@@ -251,12 +226,38 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ pwm: pwm@10048000 {
+ compatible = "mediatek,mt7986-pwm";
+ reg = <0 0x10048000 0 0x1000>;
+ #clock-cells = <1>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CK_INFRA_PWM>,
+ <&infracfg_ao CK_INFRA_PWM_BSEL>,
+ <&infracfg_ao CK_INFRA_PWM1_CK>,
+ <&infracfg_ao CK_INFRA_PWM2_CK>;
+ assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
+ <&infracfg_ao CK_INFRA_PWM_BSEL>,
+ <&infracfg_ao CK_INFRA_PWM1_SEL>,
+ <&infracfg_ao CK_INFRA_PWM2_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>,
+ <&infracfg CK_INFRA_PWM>,
+ <&infracfg CK_INFRA_PWM>,
+ <&infracfg CK_INFRA_PWM>;
+ clock-names = "top", "main", "pwm1", "pwm2";
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_clk>;
+ clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+ <&infracfg_ao CK_INFRA_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+ <&infracfg CK_INFRA_UART>;
status = "disabled";
};
@@ -265,7 +266,9 @@
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_clk>;
+ clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
+ assigned-clocks = <&infracfg_ao CK_INFRA_UART1_SEL>;
+ assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
status = "disabled";
};
@@ -274,10 +277,26 @@
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_clk>;
+ clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
+ assigned-clocks = <&infracfg_ao CK_INFRA_UART2_SEL>;
+ assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
status = "disabled";
};
+ i2c0: i2c@11008000 {
+ compatible = "mediatek,mt7986-i2c";
+ reg = <0 0x11008000 0 0x90>,
+ <0 0x10217080 0 0x80>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clock-div = <16>;
+ clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
+ <&infracfg_ao CK_INFRA_AP_DMA_CK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
pcie: pcie@11280000 {
compatible = "mediatek,mt7986-pcie";
device_type = "pci";
@@ -345,7 +364,7 @@
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "mediatek,mt7986-ethsys",
+ compatible = "mediatek,mt7986-ethsys_ck",
"syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
@@ -365,24 +384,28 @@
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>,
- <&system_clk>;
+ clocks = <ðsys CK_ETH_FE_EN>,
+ <ðsys CK_ETH_GP2_EN>,
+ <ðsys CK_ETH_GP1_EN>,
+ <ðsys CK_ETH_WOCPU1_EN>,
+ <ðsys CK_ETH_WOCPU0_EN>,
+ <ðsys CK_SGM0_TX_EN>,
+ <ðsys CK_SGM0_RX_EN>,
+ <ðsys CK_SGM0_CK0_EN>,
+ <ðsys CK_SGM0_CDR_CK0_EN>,
+ <ðsys CK_SGM1_TX_EN>,
+ <ðsys CK_SGM1_RX_EN>,
+ <ðsys CK_SGM1_CK1_EN>,
+ <ðsys CK_SGM1_CDR_CK1_EN>;
clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
"sgmii_tx250m", "sgmii_rx250m",
"sgmii_cdr_ref", "sgmii_cdr_fb",
"sgmii2_tx250m", "sgmii2_rx250m",
"sgmii2_cdr_ref", "sgmii2_cdr_fb";
+ assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>,
+ <&topckgen CK_TOP_SGM_325M_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>,
+ <&topckgen CK_TOP_CB_SGM_325M>;
mediatek,ethsys = <ðsys>;
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
#reset-cells = <1>;
@@ -420,10 +443,14 @@
reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
reg-names = "nfi", "ecc";
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&system_clk>,
- <&system_clk>,
- <&system_clk>;
+ clocks = <&topckgen CK_TOP_SPINFI_SEL>,
+ <&infracfg_ao CK_INFRA_SPINFI1_CK>,
+ <&topckgen CK_TOP_NFI1X_SEL>;
clock-names = "nfi_clk", "pad_clk", "ecc_clk";
+ assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
+ <&topckgen CK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M_D2>,
+ <&topckgen CK_TOP_CB_CKSQ_40M>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -448,9 +475,9 @@
compatible = "mediatek,ipm-spi";
reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&spi0_clk>,
- <&spi0_clk>,
- <&spi0_clk>;
+ clocks = <&topckgen CK_TOP_CB_M_D2>,
+ <&infracfg_ao CK_INFRA_SPI0_CK>,
+ <&topckgen CK_TOP_SPI_SEL>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -459,9 +486,9 @@
compatible = "mediatek,ipm-spi";
reg = <0 0x1100b000 0 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&spi1_clk>,
- <&spi1_clk>,
- <&spi1_clk>;
+ clocks = <&topckgen CK_TOP_CB_M_D2>,
+ <&infracfg_ao CK_INFRA_SPI1_CK>,
+ <&topckgen CK_TOP_SPIM_MST_SEL>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -471,10 +498,14 @@
reg = <0 0x11230000 0 0x1000>,
<0 0x11c20000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_clk>,
- <&uart_clk>,
- <&uart_clk>;
+ clocks = <&topckgen CK_TOP_EMMC_416M>,
+ <&topckgen CK_TOP_EMMC_250M>,
+ <&infracfg_ao CK_INFRA_MSDC_CK>;
clock-names = "source", "hclk", "source_cg";
+ assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
+ <&topckgen CK_TOP_EMMC_250M_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+ <&topckgen CK_TOP_CB_CKSQ_40M>;
status = "disabled";
};
@@ -482,9 +513,10 @@
compatible = "mediatek,mt7986-auxadc",
"mediatek,mt7622-auxadc";
reg = <0 0x1100d000 0 0x1000>;
- clocks = <&system_clk>;
+ clocks = <&infracfg_ao CK_INFRA_ADC_26M_CK>;
clock-names = "main";
#io-channel-cells = <1>;
+ status = "disabled";
};
consys: consys@10000000 {
@@ -556,4 +588,4 @@
};
};
-#include "mt7986-clkitg.dtsi"
\ No newline at end of file
+#include "mt7986-clkitg.dtsi"
diff --git a/target/linux/mediatek/mt7986/config-5.4 b/target/linux/mediatek/mt7986/config-5.4
index 29e6556..2622dbe 100644
--- a/target/linux/mediatek/mt7986/config-5.4
+++ b/target/linux/mediatek/mt7986/config-5.4
@@ -82,8 +82,7 @@
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT7986=y
-# CONFIG_COMMON_CLK_MT2712=y
+CONFIG_COMMON_CLK_MT2712=y
# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
@@ -93,12 +92,13 @@
# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
# CONFIG_COMMON_CLK_MT6779 is not set
# CONFIG_COMMON_CLK_MT6797 is not set
-# CONFIG_COMMON_CLK_MT7622=y
-# CONFIG_COMMON_CLK_MT7622_AUDSYS=y
-# CONFIG_COMMON_CLK_MT7622_ETHSYS=y
-# CONFIG_COMMON_CLK_MT7622_HIFSYS=y
+CONFIG_COMMON_CLK_MT7622=y
+# CONFIG_COMMON_CLK_MT7622_AUDSYS is not set
+# CONFIG_COMMON_CLK_MT7622_ETHSYS is not set
+# CONFIG_COMMON_CLK_MT7622_HIFSYS is not set
+CONFIG_COMMON_CLK_MT7986=y
# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8183=y
+CONFIG_COMMON_CLK_MT8183=y
# CONFIG_COMMON_CLK_MT8183_AUDIOSYS is not set
# CONFIG_COMMON_CLK_MT8183_CAMSYS is not set
# CONFIG_COMMON_CLK_MT8183_IMGSYS is not set
@@ -110,7 +110,7 @@
# CONFIG_COMMON_CLK_MT8183_MMSYS is not set
# CONFIG_COMMON_CLK_MT8183_VDECSYS is not set
# CONFIG_COMMON_CLK_MT8183_VENCSYS is not set
-# CONFIG_COMMON_CLK_MT8516=y
+CONFIG_COMMON_CLK_MT8516=y
# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
CONFIG_COMPAT=y
CONFIG_COMPAT_32BIT_TIME=y
@@ -237,6 +237,10 @@
CONFIG_HW_RANDOM_MTK=y
CONFIG_HZ=250
CONFIG_HZ_250=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MT65XX=y
CONFIG_ICPLUS_PHY=y
CONFIG_IIO=y
CONFIG_IKCONFIG=y
@@ -251,6 +255,7 @@
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
CONFIG_JUMP_LABEL=y
+# CONFIG_LEDS_UBNT_LEDBAR is not set
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
@@ -310,11 +315,11 @@
CONFIG_NLS=y
CONFIG_NMBM=y
# CONFIG_NMBM_LOG_LEVEL_DEBUG is not set
-CONFIG_NMBM_LOG_LEVEL_INFO=y
-# CONFIG_NMBM_LOG_LEVEL_WARN is not set
-# CONFIG_NMBM_LOG_LEVEL_ERR is not set
# CONFIG_NMBM_LOG_LEVEL_EMERG is not set
+# CONFIG_NMBM_LOG_LEVEL_ERR is not set
+CONFIG_NMBM_LOG_LEVEL_INFO=y
# CONFIG_NMBM_LOG_LEVEL_NONE is not set
+# CONFIG_NMBM_LOG_LEVEL_WARN is not set
CONFIG_NMBM_MTD=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
@@ -361,6 +366,7 @@
CONFIG_PINCTRL_MT8516=y
CONFIG_PINCTRL_MTK=y
CONFIG_PINCTRL_MTK_MOORE=y
+CONFIG_PLUGIN_HOSTCC="g++"
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
diff --git a/target/linux/mediatek/patches-5.4/0001-clk-mtk-add-mt7986-support.patch b/target/linux/mediatek/patches-5.4/0001-clk-mtk-add-mt7986-support.patch
index 324be72..930e88b 100644
--- a/target/linux/mediatek/patches-5.4/0001-clk-mtk-add-mt7986-support.patch
+++ b/target/linux/mediatek/patches-5.4/0001-clk-mtk-add-mt7986-support.patch
@@ -5,10 +5,10 @@
@@ -258,6 +258,15 @@ config COMMON_CLK_MT7629_HIFSYS
This driver supports MediaTek MT7629 HIFSYS clocks providing
to PCI-E and USB.
-
+
+config COMMON_CLK_MT7986
+ bool "Clock driver for MediaTek MT7986"
-+ depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
++ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK && ARM
+ ---help---
diff --git a/target/linux/mediatek/patches-5.4/0900-i2c-busses-add-mt7986-support.patch b/target/linux/mediatek/patches-5.4/0900-i2c-busses-add-mt7986-support.patch
new file mode 100644
index 0000000..a375842
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/0900-i2c-busses-add-mt7986-support.patch
@@ -0,0 +1,32 @@
+diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
+index e1ef012..4fd4721 100644
+--- a/drivers/i2c/busses/i2c-mt65xx.c
++++ b/drivers/i2c/busses/i2c-mt65xx.c
+@@ -289,6 +289,19 @@ static const struct mtk_i2c_compatible mt7622_compat = {
+ .ltiming_adjust = 0,
+ };
+
++static const struct mtk_i2c_compatible mt7986_compat = {
++ .quirks = &mt7622_i2c_quirks,
++ .regs = mt_i2c_regs_v1,
++ .pmic_i2c = 0,
++ .dcm = 1,
++ .auto_restart = 1,
++ .aux_len_reg = 1,
++ .support_33bits = 0,
++ .timing_adjust = 0,
++ .dma_sync = 1,
++ .ltiming_adjust = 0,
++};
++
+ static const struct mtk_i2c_compatible mt8173_compat = {
+ .regs = mt_i2c_regs_v1,
+ .pmic_i2c = 0,
+@@ -319,6 +332,7 @@ static const struct of_device_id mtk_i2c_of_match[] = {
+ { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
+ { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
+ { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
++ { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
+ { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
+ { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
+ {}
diff --git a/target/linux/mediatek/patches-5.4/0930-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-5.4/0930-pwm-add-mt7986-support.patch
new file mode 100644
index 0000000..a791d3a
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/0930-pwm-add-mt7986-support.patch
@@ -0,0 +1,24 @@
+diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
+index b94e0d0..35a0db2 100644
+--- a/drivers/pwm/pwm-mediatek.c
++++ b/drivers/pwm/pwm-mediatek.c
+@@ -302,6 +302,11 @@ static const struct pwm_mediatek_of_data mt7629_pwm_data = {
+ .pwm45_fixup = false,
+ };
+
++static const struct pwm_mediatek_of_data mt7986_pwm_data = {
++ .num_pwms = 2,
++ .pwm45_fixup = false,
++};
++
+ static const struct pwm_mediatek_of_data mt8516_pwm_data = {
+ .num_pwms = 5,
+ .pwm45_fixup = false,
+@@ -313,6 +318,7 @@ static const struct of_device_id pwm_mediatek_of_match[] = {
+ { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
+ { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
+ { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
++ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
+ { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
+ { },
+ };