[][MAC80211][wed][Change WARN_RATELIMIT to pr_err for wed ext interrupt]
[Description]
Change WARN_RATELIMIT to pr_err for wed ext interrupt
[Release-log]
N/A
Change-Id: Ifb7427e1d7a3f3e3c949f6c3fb770bf18b0642b3
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7907591
diff --git a/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3008-add-wed-tx-support-for-mt7986.patch b/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3008-add-wed-tx-support-for-mt7986.patch
old mode 100755
new mode 100644
index 7734ce2..f2c4a1f
--- a/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3008-add-wed-tx-support-for-mt7986.patch
+++ b/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3008-add-wed-tx-support-for-mt7986.patch
@@ -832,20 +832,7 @@
}
return 0;
-@@ -706,10 +935,8 @@ mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
- val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
- wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
- val &= MTK_WED_EXT_INT_STATUS_ERROR_MASK;
-- if (!dev->hw->num_flows)
-- val &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
-- if (val && net_ratelimit())
-- pr_err("mtk_wed%d: error status=%08x\n", dev->hw->index, val);
-+ WARN_RATELIMIT(val, "mtk_wed%d: error status=%08x\n",
-+ dev->hw->index, val);
-
- val = wed_r32(dev, MTK_WED_INT_STATUS);
- val &= mask;
-@@ -780,7 +1007,8 @@ out:
+@@ -780,7 +1009,8 @@ out:
}
void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
@@ -855,7 +842,7 @@
{
static const struct mtk_wed_ops wed_ops = {
.attach = mtk_wed_attach,
-@@ -830,21 +1058,27 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
+@@ -830,21 +1060,27 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
hw->eth = eth;
hw->dev = &pdev->dev;
hw->wdma = wdma;
@@ -992,7 +979,7 @@
#define MTK_WED_RESET 0x008
#define MTK_WED_RESET_TX_BM BIT(0)
#define MTK_WED_RESET_TX_FREE_AGENT BIT(4)
-@@ -41,6 +51,7 @@ struct mtk_wdma_desc {
+@@ -41,6 +55,7 @@ struct mtk_wdma_desc {
#define MTK_WED_CTRL_RESERVE_EN BIT(12)
#define MTK_WED_CTRL_RESERVE_BUSY BIT(13)
#define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24)
@@ -1000,7 +987,7 @@
#define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28)
#define MTK_WED_EXT_INT_STATUS 0x020
-@@ -49,6 +60,10 @@ struct mtk_wdma_desc {
+@@ -49,6 +64,10 @@ struct mtk_wdma_desc {
#define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4)
#define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8)
#define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9)
@@ -1011,7 +998,7 @@
#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(12)
#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(13)
#define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16)
-@@ -57,16 +71,23 @@ struct mtk_wdma_desc {
+@@ -57,16 +76,23 @@ struct mtk_wdma_desc {
#define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19)
#define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20)
#define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21)
@@ -1038,7 +1025,7 @@
#define MTK_WED_EXT_INT_MASK 0x028
-@@ -80,10 +103,6 @@ struct mtk_wdma_desc {
+@@ -80,10 +106,6 @@ struct mtk_wdma_desc {
#define MTK_WED_TX_BM_BASE 0x084
@@ -1049,7 +1036,7 @@
#define MTK_WED_TX_BM_BUF_LEN 0x08c
#define MTK_WED_TX_BM_INTF 0x09c
-@@ -93,9 +112,38 @@ struct mtk_wdma_desc {
+@@ -93,9 +115,38 @@ struct mtk_wdma_desc {
#define MTK_WED_TX_BM_INTF_TKID_READ BIT(29)
#define MTK_WED_TX_BM_DYN_THR 0x0a0
@@ -1088,7 +1075,7 @@
#define MTK_WED_INT_STATUS 0x200
#define MTK_WED_INT_MASK 0x204
-@@ -125,6 +173,7 @@ struct mtk_wdma_desc {
+@@ -125,6 +176,7 @@ struct mtk_wdma_desc {
#define MTK_WED_RESET_IDX_RX GENMASK(17, 16)
#define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4)
@@ -1096,7 +1083,7 @@
#define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10)
-@@ -139,6 +188,19 @@ struct mtk_wdma_desc {
+@@ -139,6 +191,19 @@ struct mtk_wdma_desc {
#define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1)
#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2)
#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3)
@@ -1116,7 +1103,7 @@
#define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4)
#define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6)
#define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
-@@ -152,24 +214,54 @@ struct mtk_wdma_desc {
+@@ -152,24 +217,54 @@ struct mtk_wdma_desc {
#define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
#define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27)
#define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28)
@@ -1172,7 +1159,7 @@
#define MTK_WED_WPDMA_TX_MIB(_n) (0x5a0 + (_n) * 4)
#define MTK_WED_WPDMA_TX_COHERENT_MIB(_n) (0x5d0 + (_n) * 4)
-@@ -203,14 +295,22 @@ struct mtk_wdma_desc {
+@@ -203,14 +298,22 @@ struct mtk_wdma_desc {
#define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16)
#define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24)
@@ -1196,7 +1183,7 @@
#define MTK_WED_WDMA_RX_MIB(_n) (0xae0 + (_n) * 4)
#define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4)
-@@ -221,14 +321,21 @@ struct mtk_wdma_desc {
+@@ -221,14 +324,21 @@ struct mtk_wdma_desc {
#define MTK_WED_RING_OFS_CPU_IDX 0x08
#define MTK_WED_RING_OFS_DMA_IDX 0x0c