| commit | 3baea0530ebe13c840484fee5c7b51b906a0c435 | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Mon Sep 26 17:39:49 2022 +0800 |
| committer | developer <developer@mediatek.com> | Thu Sep 29 10:02:04 2022 +0800 |
| tree | b4ce981733f5463b4eef3cccca4f90cc9936fc4a | |
| parent | fa8ffcdf3912a331746a6401f644e1d879f81469 [diff] |
[][[Merlin][AX3000][MT76][Performance] DBDC 5G HE160,peak throughput test , HWNAT CPU idle only 50.77%]
[Description]
Fix CPU idle only 50.77% issue when binding
DL: MT76 handle txfree notify interrupt
when all token are belongs to wed
UL: Merlin Rx data interrupt bit changes
to bit[19:18] from bit[23:22] when wed on
[Release-log]
N/A
[[Info to Customer]]
none
Change-Id: Icbfb4e0b6714e74ce2f7c501078bf37d164bda0e
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6563470
Build: srv_hbgsm110