tree 0ff0ffa5db5732452047ed8d1cc96db7cbf98c49
parent 94806ecf62f6e2c511dc5e5be69867d41ea12671
author developer <developer@mediatek.com> 1684301988 +0800
committer developer <developer@mediatek.com> 1684767223 +0800

[][kernel][mt7988][eth][phy: mediatek-2p5ge: Fix LED0/LED1 polarity]

[Description]
Fix LED0/LED1 polarity:
1. Don't use "default" pinctrl-name or pinctrl driver will get and select
it before phy driver sets correct LED polarity.
2. Now, LED0 is on when internal 2.5Gphy links up @ 10/100/1000/2500 Mbps.
LED1 is on when internal 2.5Gphy links up with FDX/HDX.
3. Setup LED after FW is loaded and triggered. So remove probe().

Without this patch, internal 2.5Gphy's LED may blink unexpectedly.

[Release-log]
N/A

Change-Id: I09bfc2d517d1773566bb1f171cf8595a408db6cc
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7500812