[][kernel][mt7987][eth][Add the default configuration for the NETSYSv3.1]
[Description]
Add the default configuration for the NETSYSv3.1.
[Release-log]
N/A
Change-Id: Ia1c47e036e4b1dc37eb1b254498285738da107a6
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/9743592
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 1b9eabc..e7c7cd6 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -855,7 +855,8 @@
mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
+ MTK_HAS_CAPS(eth->soc->caps, MTK_ESW)) {
if (mac->id == MTK_GMAC1_ID)
mtk_setup_bridge_switch(eth);
}
@@ -4672,7 +4673,7 @@
if (eth->soc->caps != MT7988_CAPS || eth->hwver != MTK_HWID_V1)
mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) |
PSE_DUMMY_WORK_GDM(2) | PSE_DUMMY_WORK_GDM(3) |
- DUMMY_PAGE_THR, PSE_DUMY_REQ);
+ DUMMY_PAGE_THR(eth->soc->caps), PSE_DUMY_REQ);
/* PSE should not drop port8 and port9 packets */
mtk_w32(eth, 0x00000300, PSE_NO_DROP_CFG);
@@ -4680,17 +4681,21 @@
/* PSE should drop p8 and p9 packets when WDMA Rx ring full*/
mtk_w32(eth, 0x00000300, PSE_PPE0_DROP);
- /* PSE free buffer drop threshold */
- mtk_w32(eth, 0x00600009, PSE_IQ_REV(8));
+ if (eth->soc->caps == MT7988_CAPS) {
+ /* PSE free buffer drop threshold */
+ mtk_w32(eth, 0x00600009, PSE_IQ_REV(8));
- /* GDM and CDM Threshold */
- mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES);
- mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
+ /* GDM and CDM Threshold */
+ mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES);
+ mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
+ }
- /* Disable GDM1 RX CRC stripping */
- val = mtk_r32(eth, MTK_GDMA_FWD_CFG(0));
- val &= ~MTK_GDMA_STRP_CRC;
- mtk_w32(eth, val, MTK_GDMA_FWD_CFG(0));
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_ESW)) {
+ /* Disable GDM1 RX CRC stripping */
+ val = mtk_r32(eth, MTK_GDMA_FWD_CFG(0));
+ val &= ~MTK_GDMA_STRP_CRC;
+ mtk_w32(eth, val, MTK_GDMA_FWD_CFG(0));
+ }
/* PSE GDM3 MIB counter has incorrect hw default values,
* so the driver ought to read clear the values beforehand
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 7805edf..aa4a6f2 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -168,7 +168,7 @@
/* PSE Last FreeQ Page Request Control */
#define PSE_DUMY_REQ 0x10C
#define PSE_DUMMY_WORK_GDM(x) BIT(16 + (x))
-#define DUMMY_PAGE_THR 0x151
+#define DUMMY_PAGE_THR(x) ((x == MT7988_CAPS) ? 0x151 : 0x1)
/* PSE Input Queue Reservation Register*/
#define PSE_IQ_REV(x) (0x140 + ((x - 1) * 0x4))
@@ -1711,7 +1711,7 @@
#define MT7988_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC3_SGMII | \
MTK_PDMA_INT | MTK_MUX_GMAC123_TO_GEPHY_SGMII | MTK_QDMA | \
MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | \
- MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \
+ MTK_ESW | MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \
MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII | \
MTK_GMAC2_2P5GPHY | MTK_MUX_GMAC2_TO_2P5GPHY | MTK_RSS | \
MTK_HWLRO | MTK_NETSYS_RX_V2 | MTK_36BIT_DMA)